专利检索_...同时或顺序地显示多于一个变量的电路专利检索_...同时或顺序地显示多于一个变量的电路专利检索查询

序号	专利名	申请号	申请日	公开（公告）号	公开（公告）日	发明人
161	Synchronization of electronically switched displays	US6495260	1960-10-25	US3088050A	1963-04-30	MEYER MARON

162	Method and apparatus for visually analyzing a plurality of signals	US40762954	1954-02-02	US2858475A	1958-10-28	BLAKE FRANCIS G

163	Bar graph oscilloscopes	US58374556	1956-05-09	US2848648A	1958-08-19	WOLCOTT HENRY O

164	Electronic switch incorporated in a deflection circuit	US45251354	1954-08-27	US2829305A	1958-04-01	KOCHEVAR HENRY J

165	Cathode-ray oscillographic apparatus	US5785348	1948-11-02	US2483140A	1949-09-27	HIGHAM EDWARD H

166	Oscilloscope circuit	US59745845	1945-06-04	US2444338A	1948-06-29	DIMOND THOMAS L

167	Vibratory switching device for oscillographs	US55242544	1944-09-02	US2439050A	1948-04-06	ROGERS MALLORY HENRY

168	Cathode ray electrical measuring device	US21710438	1938-07-01	US2171216A	1939-08-29	KOCH GEORGE M

169	Switching device	US74576534	1934-09-27	US2122499A	1938-07-05	STOCKER ARTHUR C

170	Electrical test and measurement device, measurement extension device as well as test and measurement system	US15981531	2018-05-16	US11249115B2	2022-02-15	Philip Diegmann
An electrical test and measurement device is described that has at least one analog channel comprising an analog input, an attenuator circuit, an amplifier unit, and a digitizer. The electrical test and measurement device comprises another digitizer allocated to a digitizer input of the electrical test and measurement device. The digitizer input is configured to be connected to a measurement extension device. Further, a measurement extension device and a test and measurement system are described.
171	MEASURING SYSTEM AND METHOD	US17504167	2021-10-18	US20220034941A1	2022-02-03	Gerd Bresser; Friedrich Reich
A measuring system for measuring signals with multiple measurement probes comprises a multi probe measurement device comprising at least two probe interfaces that each couple the multi probe measurement device with at least one of the measurement probes, a data interface that couples the multi probe measurement device to a measurement data receiver, and a processing unit coupled to the at least two probe interfaces that records measurement, values via the at least two probe interfaces from the measurement probes, wherein the processing unit is further coupled to the data interface and provides the recorded measurement values to the measurement data receiver, and a measurement data receiver comprising a data interface, wherein the data interface of the measurement data receiver is coupled to the data interface of the multi probe measurement device.
172	Performance of signature-based diagnosis for logic BIST	US12918988	2009-02-23	US08448032B2	2013-05-21	Manish Sharma; Wu-Tung Cheng; Thomas H. Rinderknecht
Techniques are disclosed for reducing the set of initial candidates in signature based diagnosis methodology. These techniques are based on a unique way of making optimum use of information from logic back-cone tracing along with equations that describe the test response compactor.
173	Programmable extended compression mask for dynamic trace	US11566766	2006-12-05	US07606696B2	2009-10-20	Lewis Nardini; Manisha Agarwala; John M. Johnsen
This invention provides trace address compression by comparing respective bytes of a current trace address with a stored comparison address. Only the least significant bytes of the current trace address that do not match the comparison address or are less significant than any section of the current trace address that does not match the comparison address are transmitted. This sometimes reduces the amount of data that needs to be transmitted. The comparison address is specified by a central processing unit via a memory mapped register write operation.
174	System and method for accessing signals of a user design in a programmable logic device	US11405903	2006-04-18	US07353474B1	2008-04-01	Adam P. Donlin
Access to a signals of a user design in a programmable logic device (PLD) is provided without a compilation delay following selection of the signals. The system may include a generator, a compiler, a selector, the PLD, and a monitor. The generator selects sets of signals of the user design, and for each set of signals, generates a respective supplement of a subset of the user design supplementing the subset with a logic analyzer coupled to the set of signals. The compiler generates a respective configuration for each supplement. The selector selects a configuration or multiple configurations responsive to the specified set of signals and the sets of signals. The PLD implements the user design after the PLD is programmed with the selected configuration or configurations. The monitor accesses the specified set of signals in the PLD via the logic analyzer corresponding to each of the selected configuration or configurations.
175	Method of operating an oscilloscope	US09536205	2000-03-27	US06947043B1	2005-09-20	Kayla R. Klingman; Scott A. Davidson
An oscilloscope that is capable of displaying simultaneously multiple waveforms representing time evolution of a signal during respective acquisition intervals acquires waveform data using a first set of acquisition parameters and generates a display based on that waveform data. If the display includes a waveform that is visually distinct from other displayed waveforms, the user selects a feature that distinguishes the visually distinct waveform from other displayed waveforms. The oscilloscope automatically derives updated acquisition parameters that discriminate between the selected feature and other features of the displayed waveforms. The oscilloscope then acquires waveform data using the updated acquisition parameters and generates a display based on that waveform data.
176	Methods and apparatus for testing continuity of electrical paths through connectors of circuit assemblies	US10683693	2003-10-09	US06933730B2	2005-08-23	Kenneth P. Parker; Jacob L. Bell
A device for testing continuity of electrical paths through a connector of a circuit assembly has a package containing incomplete or no mission circuitry for the circuit assembly. The package is provided with a plurality of contacts for mating to a plurality of contacts of the connector. A test sensor port is integrated with the package. A plurality of passive circuit components are integrated with the package, ones of which are coupled in parallel between ones of the contacts on the package and the test sensor port.
177	Method of displaying continuously acquired data as multiple traces on a fixed length display	US560246	1995-11-21	US5684508A	1997-11-04	Klaas Jan Brilman
A method of displaying continuously acquired measurement values as a plurality of traces in a display with a fixed number of pixels is provided. An input signal is captured as a series of acquired input signals. Measurement values are calculated from the acquired input signals according to a set of measurement parameters. The measurement values are plotted to a display as a plurality of traces according to the measurement parameters. Each of the traces may be scaled vertically independently of one another. At the end of the fixed number of pixels of the display, the pixel values are compressed to half the fixed number of pixels and the pixel rate is halved, thereby doubling the time scale. As a minimum pixel rate is eventually reached, the traces are then scrolled in a roll mode in which the newest measurement value is added to one end of the display and the old value at the other end is discarded. This scrolling process can continue indefinitely, requiring no operator intervention or prior knowledge to set a total measurement time.
178	Logic signal extraction	US135099	1993-10-12	US5446650A	1995-08-29	Craig Overhage; Richard Austin
Methods for producing logic signal displays for an instrument known as a "logic oscilloscope" are disclosed. A digital input signal is first sampled as an analog signal to produce multi-bit digital samples that are representative of the amplitude of the input signal over time. The multi-bit digital samples are then processed using interpolative techniques to ascertain when the input signal crossed a hypothetical logic level threshold or pair of thresholds and when the signal was in one logic state or the other. The resulting transition times and logic states are then used as the basis for generating a variety of digital displays, including logic timing diagrams, state table displays, and cursor readouts similar to those available in a logic analyzer. Setup and hold time violations and measurements may also be obtained using this information. In a pseudo-synchronous mode of operation, one logic signal is treated as a virtual clock signal, so that the states of other (data) signals are determined at times controlled by the active transitions of this clock signal. A cursor provides a digital readout of the logic value of one or more signals, whether they are displayed in analog form or logic timing diagram form or not shown on the screen at all.
179	Method and apparatus for adjustment of acquisition parameters in a data acquisition system such as a digital oscilloscope	US989334	1992-12-11	US5375067A	1994-12-20	Gregory J. Berchin
A data acquisition system such as a digital oscilloscope includes a central processing unit which controls the waveform memory, analog to digital converter, trigger generator, and display to automatically adjust the acquisition parameters to optimal values for a particular repetitive waveform received by the data acquisition system. The system initially optimizes the acquisition parameters for determining the length of the input waveform and then determines the input waveform length. Parameters are then determined for best frequency analysis of the input waveform, and the waveform is then frequency analyzed to determine its spectral content. Based on this information, the acquisition parameters are adjusted such that the sampling rate is sufficient to avoid aliasing of the highest significant frequency components of the input waveform while accommodating all or substantially all of the waveform within the memory capacity of the waveform memory, and the voltage range of the analog to digital converter is set so that the range of the input signal will substantially match the input range of the converter.
180	Dynamic storage allocation in a logic analyzer	US910059	1992-07-08	US5347540A	1994-09-13	Kevin C. Karrick
An apparatus and method for dynamic memory allocation conserves memory resources while providing efficient and effective interaction between concurrent synchronous and asynchronous acquisition of data for logic analysis. The apparatus includes circuitry for acquiring synchronous data, circuitry for acquiring asynchronous data, circuitry for generating timestamp values, circuitry for determining when the synchronous data is valid, circuitry for determining when the asynchronous data is valid, and circuitry for packing valid synchronous data and valid asynchronous data into a memory according to the sequence in which it was acquired with sufficient timestamp values included to permit reconstruction of the relative timing between all of the acquired data, with each data and timestamp value being identified with status bits to indicate whether it was synchronous data, asynchronous data, or a timestamp value. The method of dynamic memory allocation includes the steps of acquiring synchronous data, acquiring asynchronous data, generating timestamp values, determining when the synchronous data is valid, also determining when the asynchronous data is valid, and packing valid synchronous data and valid asynchronous data into a memory according to the sequence in which it was acquired with sufficient timestamp values included to permit reconstruction of the relative timing between all of the acquired data, with each data and timestamp value being identified with status bits to indicate whether it was synchronous data, asynchronous data, or a timestamp value.

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