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11. 发明授权

US07268078B2 Chemical vapor deposition of titanium from titanium tetrachloride and hydrocarbon reactants 失效
标题翻译：来自四氯化钛和烃反应物的钛的化学气相沉积
公开(公告)号：US07268078B2
公开(公告)日：2007-09-11
申请号：US11298978
申请日：2005-12-09
申请人： Ravi Iyer , Sujit Sharan
发明人： Ravi Iyer , Sujit Sharan
IPC分类号： H01L21/44
CPC分类号： C23C16/08 , H01L21/28556 , H01L21/28568 , Y10S438/909
摘要： A process for depositing titanium metal layers via chemical vapor deposition is disclosed. The process provides deposited titanium layers having a high degree of conformality, even in trenches and contact openings having aspect ratios greater than 1:5.
摘要翻译：公开了一种通过化学气相沉积沉积钛金属层的工艺。该方法即使在具有大于1:5的纵横比的沟槽和接触开口中也提供具有高度保形性的沉积钛层。

12. 发明申请

US20070049015A1 Silicided recessed silicon 有权
标题翻译：硅胶凹槽硅
公开(公告)号：US20070049015A1
公开(公告)日：2007-03-01
申请号：US11219303
申请日：2005-09-01
申请人： Hasan Nejad , Thomas Figura , Gordon Haller , Ravi Iyer , John Meldrim , Justin Harnish
发明人： Hasan Nejad , Thomas Figura , Gordon Haller , Ravi Iyer , John Meldrim , Justin Harnish
IPC分类号： H01L21/4763
CPC分类号： H01L21/823835 , H01L21/28097 , H01L21/823418 , H01L21/823443 , H01L21/823814 , H01L27/10852 , H01L27/10876 , H01L27/10897 , H01L29/4975 , H01L29/66621 , H01L2924/0002 , H01L2924/00
摘要： Methods and structures are provided for full silicidation of recessed silicon. Silicon is provided within a trench. A mixture of metals is provided over the silicon in which one of the metals diffuses more readily in silicon than silicon does in the metal, and another of the metals diffuses less readily in silicon than silicon does in the metal. An exemplary mixture includes 80% nickel and 20% cobalt. The silicon within the trench is allowed to fully silicide without void formation, despite a relatively high aspect ratio for the trench. Among other devices, recessed access devices (RADs) can be formed by the method for memory arrays.
摘要翻译：为嵌入硅完全硅化提供了方法和结构。在沟槽内提供硅。在硅上提供了一种金属混合物，其中一种金属在硅中比硅中更容易扩散到金属中，而另一种金属在硅中比在金属中的硅更容易扩散。示例性的混合物包括80％的镍和20％的钴。尽管沟槽的纵横比相对较高，但沟槽内的硅可以完全无硅化物形成。在其他设备中，可以通过用于存储器阵列的方法形成凹陷接入设备（RAD）。

13. 发明授权

US07115492B2 Technique for elimination of pitting on silicon substrate during gate stack etch using material in a non-annealed state 有权
标题翻译：使用非退火状态的材料进行栅叠层蚀刻时消除硅衬底上点蚀的技术
公开(公告)号：US07115492B2
公开(公告)日：2006-10-03
申请号：US10630268
申请日：2003-07-30
申请人： Pai-Hung Pan , Louie Liu , Ravi Iyer
发明人： Pai-Hung Pan , Louie Liu , Ravi Iyer
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L21/28052
摘要： A method for forming a gate stack which minimizes or eliminates damage to the gate dielectric layer and/or silicon substrate during the gate stack formation by the reduction of the temperature during formation. The temperature reduction prevents the formation of silicon clusters within the metallic silicide film in the gate stack which has been found to cause damage during the gate etch step. The present invention also includes methods for dispersing silicon clusters prior to the gate etch step.
摘要翻译：一种用于形成栅堆叠的方法，其通过在形成期间的温度降低来最小化或消除在栅叠层形成期间对栅介质层和/或硅衬底的损坏。温度降低防止在栅极堆叠中的金属硅化物膜内形成硅团簇，这已被发现在栅极蚀刻步骤期间造成损坏。本发明还包括在栅极蚀刻步骤之前分散硅簇的方法。

14. 发明申请

US20060134912A1 Chemical vapor deposition of titanium from titanium tetrachloride and hydrocarbon reactants 失效
标题翻译：来自四氯化钛和烃反应物的钛的化学气相沉积
公开(公告)号：US20060134912A1
公开(公告)日：2006-06-22
申请号：US11298978
申请日：2005-12-09
申请人： Ravi Iyer , Sujit Sharan
发明人： Ravi Iyer , Sujit Sharan
IPC分类号： H01L21/44
CPC分类号： C23C16/08 , H01L21/28556 , H01L21/28568 , Y10S438/909
摘要： A process for depositing titanium metal layers via chemical vapor deposition is disclosed. The process provides deposited titanium layers having a high degree of conformality, even in trenches and contact openings having aspect ratios greater than 1:5.
摘要翻译：公开了一种通过化学气相沉积沉积钛金属层的工艺。该方法即使在具有大于1:5的纵横比的沟槽和接触开口中也提供具有高度保形性的沉积钛层。

15. 发明授权

US06952051B1 Interlevel dielectric structure 失效
标题翻译：电介质结构
公开(公告)号：US06952051B1
公开(公告)日：2005-10-04
申请号：US09627649
申请日：2000-07-28
申请人： Gurtej Sandhu , Anand Srinivasan , Ravi Iyer
发明人： Gurtej Sandhu , Anand Srinivasan , Ravi Iyer
IPC分类号： H01L21/768 , H01L23/48
CPC分类号： H01L21/76801 , H01L21/76834 , H01L21/76837
摘要： An interlevel dielectric structure includes first and second dielectric layers between which are located lines of a conductive material with a dielectric material in spaces between the lines of conductive material, with the lower surface of the dielectric material extending lower than the lower surface of lines of conductive material adjacent thereto, and the upper surface of the dielectric material extending higher than the upper surface of conductive material adjacent thereto, thus reducing fringe and total capacitance between the lines of conductive material. The dielectric material, which has a dielectric constant of less than about 3.6, does not extend directly above the upper surface of the lines of conductive material, allowing formation of subsequent contacts down to the lines of conductive material without exposing the dielectric material to further processing. Various methods for forming the interlevel dielectric structure are disclosed.
摘要翻译：层间电介质结构包括第一和第二电介质层，它们之间位于导电材料的导线之间，其中电介质材料位于导电材料线之间的空间中，电介质材料的下表面延伸低于导电线路的下表面材料相邻，并且电介质材料的上表面比邻近导电材料的上表面延伸得更高，从而减少导电材料线之间的条纹和总电容。具有小于约3.6的介电常数的电介质材料不直接在导电材料线的上表面的上方延伸，从而允许随后的触点形成至导电材料的线，而不会将电介质材料暴露于进一步的加工。公开了形成层间电介质结构的各种方法。

16. 发明授权

US06888212B2 Method for trench isolation by selective deposition of low temperature oxide films 失效
标题翻译：通过选择性沉积低温氧化膜进行沟槽隔离的方法
公开(公告)号：US06888212B2
公开(公告)日：2005-05-03
申请号：US10254756
申请日：2002-09-24
申请人： Ravi Iyer , Gurtej Sandhu , Pai Pan
发明人： Ravi Iyer , Gurtej Sandhu , Pai Pan
IPC分类号： H01L21/762 , H01L21/208
CPC分类号： H01L21/76224
摘要： A method of forming isolation regions in a silicon substrate comprising the steps of forming a trench in the silicon substrate, filling the trench with a silanol polymer material then heating the silanol polymer material so that silicon dioxide is formed in the trench and thereby forms the isolation region. In the preferred embodiment, the silicon substrate is covered by a masking stack which is then etched to expose the underlying silicon substrate. The silicon substrate is then etched to form the trench and the silanol polymer material is deposited in the trench and fills the trench from the bottom up thereby avoiding divots and other defects. The silanol polymer grows faster on the silicon substrate than it does on the nitride. After the silanol polymer is reacted to form the silicon dioxide, CMP polishing is then used to remove the remaining masking stack and silicon dioxide above the surface of the silicon substrate.
摘要翻译：一种在硅衬底中形成隔离区域的方法，包括以下步骤：在硅衬底中形成沟槽，用硅烷醇聚合物材料填充沟槽，然后加热硅烷醇聚合物材料，使得在沟槽中形成二氧化硅，从而形成隔离地区。在优选实施例中，硅衬底由掩模叠层覆盖，该掩模叠层然后被蚀刻以暴露下面的硅衬底。然后蚀刻硅衬底以形成沟槽，并且硅烷醇聚合物材料沉积在沟槽中并从底部向上填充沟槽，从而避免纹理和其它缺陷。在硅衬底上，硅烷醇聚合物比在氮化物上生长得更快。在硅烷醇聚合物反应形成二氧化硅之后，然后使用CMP研磨去除硅衬底表面上剩余的掩模叠层和二氧化硅。

17. 发明授权

US06822328B2 Integrated circuitry 有权
标题翻译：集成电路
公开(公告)号：US06822328B2
公开(公告)日：2004-11-23
申请号：US10229865
申请日：2002-08-27
申请人： Gurtej S. Sandhu , Ravi Iyer
发明人： Gurtej S. Sandhu , Ravi Iyer
IPC分类号： H01L2348
CPC分类号： H01L21/76843 , H01L21/32051 , H01L21/76846 , H01L21/7685
摘要： The invention includes integrated circuitry having an electrically insulative layer over a substrate and an opening within the electrically insulative layer. The opening has a periphery defined at least in part by a bottom surface and a sidewall surface. A first titanium layer is disposed within the opening in contact with the bottom surface and is thicker along the bottom surface than along the sidewall. A layer of TiN is provided over the first titanium layer along the bottom surface and along the sidewall surface of the opening, and a second layer of titanium is disposed over the electrically insulative layer but substantially not within the opening. The second titanium layer has a thickness of less then 50 Å along the sidewall surface and over the bottom surface. An aluminum-comprising layer is within the opening and over the second layer.
摘要翻译：本发明包括在基板上具有电绝缘层的集成电路和电绝缘层内的开口。开口具有至少部分地由底表面和侧壁表面限定的外围。第一钛层设置在与底表面接触的开口内，并且沿着底表面比沿侧壁更厚。沿着底表面并沿着开口的侧壁表面在第一钛层上提供TiN层，并且第二层钛层设置在电绝缘层上，但基本上不在开口内。第二钛层的侧壁表面和底面的厚度小于50埃。包含铝的层在开口内和第二层之上。

18. 发明授权

US06544876B1 Titanium boride gate electrode and interconnect and methods regarding same 有权
标题翻译：硼化钛栅电极及其相互连接及方法
公开(公告)号：US06544876B1
公开(公告)日：2003-04-08
申请号：US09635082
申请日：2000-08-08
申请人： Ravi Iyer
发明人： Ravi Iyer
IPC分类号： H01L2100
CPC分类号： H01L29/4941 , H01L21/28061 , H01L21/76895
摘要： A method for use in the fabrication of a gate electrode includes providing a gate oxide layer and forming a titanium boride layer on the oxide layer. An insulator cap layer is formed on the titanium boride layer and thereafter, the gate electrode is formed from the titanium boride layer. A barrier layer may be formed on the oxide layer prior to forming the titanium boride layer with the gate electrode being formed from the barrier layer and the titanium boride layer. Further, a polysilicon layer may be formed on the gate oxide layer prior to forming the titanium boride layer with the gate electrode being formed from the titanium boride layer and the polysilicon layer. Yet further, a polysilicon layer may be formed on the gate oxide layer and a barrier layer formed on the polysilicon layer prior to forming the titanium boride layer. The gate electrode is then formed from the polysilicon layer, the barrier layer, and the titanium boride layer. Similar methods can further be used in the formation of interconnects to connect contact regions. Gate electrode structures and interconnect structures resulting from the methods are also described. Further, in such methods and structures, the titanium boride layer may be a titanium diboride layer or a titanium boride layer having silicon incorporated therein.
摘要翻译：用于制造栅电极的方法包括提供栅极氧化层并在氧化物层上形成硼化钛层。在硼化钛层上形成绝缘体盖层，之后，由硼化钛层形成栅电极。在形成硼化钛层之前，可以在氧化物层上形成阻挡层，其中栅电极由阻挡层和硼化钛层形成。此外，在形成硼化钛层之前，可以在栅极氧化物层上形成多晶硅层，其中栅电极由硼化钛层和多晶硅层形成。此外，在形成硼化钛层之前，可以在栅极氧化物层上形成多晶硅层和在多晶硅层上形成的势垒层。然后，由多晶硅层，阻挡层和硼化钛层形成栅电极。类似的方法可以进一步用于形成互连以连接接触区域。还描述了由该方法产生的栅电极结构和互连结构。此外，在这些方法和结构中，硼化钛层可以是二硼化钛层或其中掺入硅的硼化钛层。

19. 发明授权

US06365530B1 Techniques for improving adhesion of silicon dioxide to titanium 失效
公开(公告)号：US06365530B1
公开(公告)日：2002-04-02
申请号：US09645958
申请日：2000-08-24
申请人： Ravi Iyer
发明人： Ravi Iyer
IPC分类号： H01L2131
CPC分类号： H01L21/02164 , H01L21/02304 , H01L21/02315 , H01L21/316 , H01L21/31612
摘要： The present invention is described in several embodiments depicting structures and methods to form these structures. A first embodiment is a structure having a silicon dioxide film bonded to a metal film comprising: a metal nitride film bonded to the metal film; and the silicon dioxide film bonded to the metal nitride film. A second embodiment is a structure having a silicon dioxide film bonded to a metal film comprising: a metal oxide film bonded to the metal film; and the silicon dioxide film bonded to the metal oxide film. A third embodiment is a structure having a silicon dioxide film bonded to a metal film comprising: a metal/oxide/nitride film bonded to the metal film; and the silicon dioxide film bonded to the metal/oxide/nitride film.

20. 发明授权

US06337286B1 Method for etching metals using organohalide compounds 失效
标题翻译：使用有机卤化物化合物蚀刻金属的方法
公开(公告)号：US06337286B1
公开(公告)日：2002-01-08
申请号：US09258741
申请日：1999-02-26
申请人： Ravi Iyer
发明人： Ravi Iyer
IPC分类号： H01L2100
CPC分类号： H01L21/67069 , H01L21/32136
摘要： A process for plasma etching metal films comprising the steps of forming a noble gas plasma, then transporting the noble gas plasma to a mixing chamber. An organohalide is added to the noble gas plasma in the mixing chamber. The organohalide is selected to have a vapor pressure allowing the formation of activated complexes to etch the metal films and form organometallic compounds as the etch byproducts. The activated complexes thus formed are transported downstream to an etching chamber. In the etching chamber the selected substrate is exposed to the activated complexes, causing the substrate to be etched and organometallic compounds to be formed as byproducts from the reaction of the activated complexes and etching of the substrate. The organometallic byproducts can then be removed from the etch chamber.
摘要翻译：一种用于等离子体蚀刻金属膜的方法，包括以下步骤：形成惰性气体等离子体，然后将稀有气体等离子体输送到混合室。在混合室中的惰性气体等离子体中加入有机卤化物。选择有机卤化物具有允许形成活化复合物的蒸汽压力以蚀刻金属膜并形成有机金属化合物作为蚀刻副产物。如此形成的活化的复合体在下游被传送到蚀刻室。在蚀刻室中，所选择的基底暴露于活化的复合物，导致基底被蚀刻，并且有机金属化合物由于活化复合物的反应和基底的蚀刻而被形成为副产物。然后可以从蚀刻室中除去有机金属副产物。

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