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1. 发明授权

US08084813B2 Short gate high power MOSFET and method of manufacture 有权
标题翻译：短路大功率MOSFET及其制造方法
公开(公告)号：US08084813B2
公开(公告)日：2011-12-27
申请号：US11949221
申请日：2007-12-03
申请人： Andrei Konstantinov , Christopher Harris , Jan-Olov Svederg
发明人： Andrei Konstantinov , Christopher Harris , Jan-Olov Svederg
IPC分类号： H01L29/66
CPC分类号： H01L29/7828 , H01L29/0696 , H01L29/0847 , H01L29/1608 , H01L29/2003 , H01L29/41766 , H01L29/4236 , H01L29/66666
摘要： A short gate high power metal oxide semiconductor field effect transistor formed in a trench includes a short gate having gate length defined by spacers within the trench. The transistor further includes a buried region that extends beneath the trench and beyond a corner of the trench, that effectively shields the gate from high drain voltage, to prevent short channel effects and resultantly improve device performance and reliability.
摘要翻译：形成在沟槽中的短栅极高功率金属氧化物半导体场效应晶体管包括具有由沟槽内的间隔物限定的栅极长度的短栅极。晶体管还包括在沟槽下方延伸并超出沟槽角部的掩埋区域，其有效地屏蔽栅极与高漏极电压，以防止短沟道效应并从而提高器件性能和可靠性。

2. 发明授权

US6100111A Method for fabricating a silicon carbide device 失效
标题翻译：制造碳化硅器件的方法
公开(公告)号：US6100111A
公开(公告)日：2000-08-08
申请号：US055281
申请日：1998-04-06
申请人： Andrei Konstantinov
发明人： Andrei Konstantinov
IPC分类号： H01L21/04 , H01L29/24 , H01L29/78 , H01L29/861 , H01L21/20
CPC分类号： H01L29/6606 , H01L21/0445 , H01L29/66068 , H01L29/7802 , H01L29/8611 , H01L29/1608
摘要： A method of fabricating a semiconductor device on a substrate, wherein the substrate comprises a first layer of doped silicon carbide of a first conducting type and exhibits at least one hollow defect. In a first step the positions of the hollow defects in the substrate are identified, whereafter a second SiC layer of a second conducting type is formed in contact with the first layer, whereafter the first and second layer constituting the pn junction are provided with at least one edge termination surrounding any hollow defect, whereby the defect is excluded from the high-field region of the device.
摘要翻译：一种在衬底上制造半导体器件的方法，其中所述衬底包括第一导电类型的第一掺杂碳化硅层，并且具有至少一个中空缺陷。在第一步骤中，识别基板中的中空缺陷的位置，之后形成与第一层接触的第二导电类型的第二SiC层，之后至少提供构成pn结的第一和第二层围绕任何中空缺陷的一个边缘终端，由此将缺陷从设备的高场区域排除。

3. 发明授权

US5804482A Method for producing a semiconductor device having a semiconductor layer of SiC 失效
标题翻译：制造具有SiC半导体层的半导体器件的方法
公开(公告)号：US5804482A
公开(公告)日：1998-09-08
申请号：US436486
申请日：1995-05-08
申请人： Andrei Konstantinov , Erik Janzen
发明人： Andrei Konstantinov , Erik Janzen
IPC分类号： H01L21/225 , C23C8/02 , C23C8/04 , H01L21/04 , H01L21/336 , H01L21/76
CPC分类号： H01L29/6606 , C23C8/02 , C23C8/04 , H01L21/0455 , H01L21/0465 , Y10S438/931
摘要： A method for producing a semiconductor device, having a semiconductor layer of a SiC comprises the steps of a) supplying dopants to the surface of the SiC layer during heating thereof for diffusion of the dopants into the SiC layer, and b) highly doping at least a portion of the surface layer of the SiC layer prior to step a) to control diffusion of the dopants into the SiC layer under the surface layer portion.
摘要翻译：一种制造具有SiC半导体层的半导体器件的方法包括以下步骤：a）在加热期间向SiC层的表面提供掺杂剂以将掺杂剂扩散到SiC层中，以及b）至少高度掺杂在步骤a）之前的SiC层的表面层的一部分，以控制掺杂剂在表面层部分下方的SiC层的扩散。

4. 发明授权

US5654208A Method for producing a semiconductor device having a semiconductor layer of SiC comprising a masking step 失效
标题翻译：用于制造具有包括掩模步骤的SiC的半导体层的半导体器件的方法
公开(公告)号：US5654208A
公开(公告)日：1997-08-05
申请号：US436487
申请日：1995-05-08
申请人： Christopher Harris , Andrei Konstantinov , Erik Janzen
发明人： Christopher Harris , Andrei Konstantinov , Erik Janzen
IPC分类号： H01L21/22 , H01L21/04 , H01L21/265 , H01L21/318 , H01L29/24 , H01L29/861
CPC分类号： H01L29/1608 , H01L21/0455 , H01L21/0465 , H01L21/318 , H01L29/6606 , Y10S148/126 , Y10S438/931 , Y10S438/945
摘要： The present invention relates to a method for producing a semiconductor device having a semiconductor layer of SiC. The method comprises the steps of a) applying a mask on at least a portion of the SiC layer to coat a first portion of the SiC layer leaving a second portion thereof uncoated, b) applying a heat treatment to the SiC layer, and c) supplying dopants to the SiC layer during the heat treatment for diffusion of the dopants into the SiC layer at the second portion thereof for doping the SiC layer. The mask is made of crystalline AIN as the only component or AIN as a major component of a crystalline alloy constituting the material.
摘要翻译：本发明涉及一种具有SiC半导体层的半导体器件的制造方法。该方法包括以下步骤：a）在SiC层的至少一部分上施加掩模，以涂覆SiC层的第一部分，留下未涂覆的第二部分，b）对SiC层进行热处理，以及c）在用于掺杂SiC层的第二部分期间将掺杂剂扩散到SiC层的热处理期间向SiC层提供掺杂剂。掩模由结晶AIN作为构成材料的结晶合金的主要成分的唯一成分或AlN。

5. 发明授权

US08823410B2 Method of manufacturing a SiC bipolar junction transistor and SiC bipolar junction transistor thereof 有权
标题翻译：制造SiC双极结型晶体管及其SiC双极结型晶体管的方法
公开(公告)号：US08823410B2
公开(公告)日：2014-09-02
申请号：US13279053
申请日：2011-10-21
申请人： Andrei Konstantinov
发明人： Andrei Konstantinov
IPC分类号： G01R31/02
CPC分类号： H01L29/73 , H01L21/02378 , H01L29/045 , H01L29/1608 , H01L29/32 , H01L29/66068 , H01L29/732
摘要： A method of manufacturing a silicon carbide (SiC) bipolar junction transistor (BJT) and a SiC BJT are provided. The SiC BJT comprises an emitter region, a base region and a collector region. The collector region is arranged on a substrate having an off-axis orientation of about 4 degrees or lower. Further, a defect termination layer (DTL) is arranged between the substrate and the collector region. A thickness and a doping level of the DTL are configured to terminate basal plane dislocations in the DTL and reduce the growth of defects from the DTL to the collector region. At least some of the embodiments are advantageous in that SiC BJTs with improved stability are provided. Further, a method of evaluating the degradation performance of a SiC BJT is provided.
摘要翻译：提供了制造碳化硅（SiC）双极结型晶体管（BJT）和SiC BJT的方法。 SiC BJT包括发射极区域，基极区域和集电极区域。集电极区域布置在离轴定向为约4度或更低的衬底上。此外，在基板和集电极区域之间配置缺陷终止层（DTL）。 DTL的厚度和掺杂水平被配置为终止DTL中的基底平面位错并且减少缺陷从DTL到收集器区域的生长。至少一些实施例是有利的，因为提供了具有改进的稳定性的SiC BJT。此外，提供了评估SiC BJT的降解性能的方法。

6. 发明申请

US20100041195A1 METHOD OF MANUFACTURING SILICON CARBIDE SELF-ALIGNED EPITAXIAL MOSFET FOR HIGH POWERED DEVICE APPLICATIONS 有权
标题翻译：用于高功率器件应用的硅碳化物自对准外延MOSFET的制造方法
公开(公告)号：US20100041195A1
公开(公告)日：2010-02-18
申请号：US12603603
申请日：2009-10-22
申请人： Christopher Harris , Kent Bertilsson , Andrei Konstantinov
发明人： Christopher Harris , Kent Bertilsson , Andrei Konstantinov
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/0878 , H01L29/1095 , H01L29/1608 , H01L29/41766 , H01L29/42368 , H01L29/66068 , Y10S438/903 , Y10S438/969
摘要： A self-aligned, silicon carbide power metal oxide semiconductor field effect transistor includes a trench formed in a first layer, with a base region and then a source region epitaxially regrown within the trench. A window is formed through the source region and into the base region within a middle area of the trench. A source contact is formed within the window in contact with a base and source regions. The gate oxide layer is formed on the source and base regions at a peripheral area of the trench and on a surface of the first layer. A gate electrode is formed on the gate oxide layer above the base region at the peripheral area of the trench, and a drain electrode is formed over a second surface of the first layer.
摘要翻译：自对准的碳化硅功率金属氧化物半导体场效应晶体管包括形成在第一层中的沟槽，其具有在沟槽内外延再生长的基极区域和源极区域。通过源区域形成窗口，并且在沟槽的中间区域内形成窗口。源极触点形成在与基极和源极区域接触的窗口内。栅极氧化层形成在沟槽的周边区域和第一层的表面上的源极和基极区域上。在沟槽的周边区域的基极区域上方的栅极氧化层上形成栅电极，在第一层的第二面上形成漏电极。

7. 发明申请

US20090224354A1 JUNCTION BARRIER SCHOTTKY DIODE WITH SUBMICRON CHANNELS 审中-公开
标题翻译：带有子通道的JUNCTION BARRIER肖特基二极管
公开(公告)号：US20090224354A1
公开(公告)日：2009-09-10
申请号：US12042614
申请日：2008-03-05
申请人： Andrei Konstantinov , Christopher Harris , Jan-Olov Svederg
发明人： Andrei Konstantinov , Christopher Harris , Jan-Olov Svederg
IPC分类号： H01L29/872 , H01L21/00
CPC分类号： H01L29/872 , H01L29/1608 , H01L29/2003 , H01L29/6606 , H01L29/66143 , H01L29/66212
摘要： A junction barrier Schottky diode is provided as having submicron channel width between implant regions by way of a process including the use of spacer technology. On-state resistance is lowered by providing the implant regions in a channel layer having increased dopant concentration.
摘要翻译：通过包括使用间隔物技术的方法，提供了一个结屏障肖特基二极管，其具有在植入区域之间的亚微米通道宽度。通过在具有增加的掺杂剂浓度的沟道层中提供注入区域来降低导通电阻。

8. 发明申请

US20070262321A1 Lateral Field Effect Transistor and Its Fabrication Comprising a Spacer Layer Above and Below the Channel Layer 有权
标题翻译：横向场效应晶体管及其制造包括通道层上方和下方的间隔层
公开(公告)号：US20070262321A1
公开(公告)日：2007-11-15
申请号：US11661962
申请日：2004-09-01
申请人： Christopher Harris , Andrei Konstantinov
发明人： Christopher Harris , Andrei Konstantinov
IPC分类号： H01L29/76 , H01L21/336
CPC分类号： H01L29/66068 , H01L21/0465 , H01L29/1029 , H01L29/1058 , H01L29/1608 , H01L29/2003 , H01L29/802 , H01L29/808 , H01L29/812
摘要： A lateral field effect transistor for high switching frequencies having a source region layer (4) and a drain region layer (5) laterally spaced and of highly doped first conductivity type, a first-conductivity-type channel layer (6) of lower doping concentration extending laterally and interconnecting the source region layer (4) and the drain region layer (5). The transistor has a gate electrode (7) arranged to control the properties of the channel layer (6), and a highly doped second-conductivity-type base layer (8) arranged under the channel layer (6) at least partially overlapping the gate electrode (7) and at a lateral distance to the drain region layer (5), the highly doped second-conductivity-type base layer (8) being shorted to the source region layer (4). The transistor also has at least one of the following: a) a spacer layer (10) having semiconductor material adjacent to the channel layer (6) and located between the channel layer (6) and gate electrode (7), at least in the vicinity of the gate electrode (7), and/or b) a spacer layer (9) having semiconductor material adjacent to the channel layer (6) and located between the channel layer (6) and the highly doped second-conductivity-type base layer (8).
摘要翻译：一种用于高开关频率的横向场效应晶体管，具有横向隔开的源区域层（4）和漏极区域层（5）以及高度掺杂的第一导电类型，具有较低掺杂浓度的第一导电型沟道层（6）横向延伸并互连源区域层（4）和漏极区域层（5）。晶体管具有布置成控制沟道层（6）的性质的栅电极（7），并且布置在沟道层（6）下方的高度掺杂的第二导电型基极层（8）至少部分地与栅极电极（7），并且在与漏极区域（5）的横向距离处，高掺杂的第二导电型基极层（8）与源区域层（4）短路。晶体管还具有以下至少一个：a）具有与沟道层（6）相邻并位于沟道层（6）和栅电极（7）之间的半导体材料的间隔层（10），至少在栅极电极（7）的附近，和/或b）具有与沟道层（6）相邻并位于沟道层（6）和高度掺杂的第二导电型基底之间的半导体材料的间隔层（9）层（8）。

9. 发明授权

US08421148B2 Grid-UMOSFET with electric field shielding of gate oxide 有权
公开(公告)号：US08421148B2
公开(公告)日：2013-04-16
申请号：US11855595
申请日：2007-09-14
申请人： Christopher Harris , Andrei Konstantinov , Jan-Olov Svederg
发明人： Christopher Harris , Andrei Konstantinov , Jan-Olov Svederg
IPC分类号： H01L29/66 , H01L29/94
CPC分类号： H01L29/7827 , H01L29/0623 , H01L29/1095 , H01L29/1608 , H01L29/2003 , H01L29/41741 , H01L29/41766 , H01L29/4238 , H01L29/45 , H01L29/66068 , H01L29/66727 , H01L29/66734 , H01L29/7813
摘要： A trench metal oxide semiconductor field effect transistor or UMOSFET, includes a buried region that extends beneath the trench and beyond a corner of the trench. The buried region is tied to a source potential of the UMOSFET, and splits the potential realized across the structure. This effectively shields the electric field from the corners of the trench to reduce gate oxide stress, and resultantly improves device performance and reliability.

10. 发明授权

US07994017B2 Method of manufacturing silicon carbide self-aligned epitaxial MOSFET for high powered device applications 有权
标题翻译：制造用于高功率器件应用的碳化硅自对准外延MOSFET的方法
公开(公告)号：US07994017B2
公开(公告)日：2011-08-09
申请号：US12603603
申请日：2009-10-22
申请人： Christopher Harris , Kent Bertilsson , Andrei Konstantinov
发明人： Christopher Harris , Kent Bertilsson , Andrei Konstantinov
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/0878 , H01L29/1095 , H01L29/1608 , H01L29/41766 , H01L29/42368 , H01L29/66068 , Y10S438/903 , Y10S438/969
摘要： A self-aligned, silicon carbide power metal oxide semiconductor field effect transistor includes a trench formed in a first layer, with a base region and then a source region epitaxially regrown within the trench. A window is formed through the source region and into the base region within a middle area of the trench. A source contact is formed within the window in contact with a base and source regions. The gate oxide layer is formed on the source and base regions at a peripheral area of the trench and on a surface of the first layer. A gate electrode is formed on the gate oxide layer above the base region at the peripheral area of the trench, and a drain electrode is formed over a second surface of the first layer.
摘要翻译：自对准的碳化硅功率金属氧化物半导体场效应晶体管包括形成在第一层中的沟槽，其具有在沟槽内外延再生长的基极区域和源极区域。通过源区域形成窗口，并且在沟槽的中间区域内形成窗口。源极触点形成在与基极和源极区域接触的窗口内。栅极氧化层形成在沟槽的周边区域和第一层的表面上的源极和基极区域上。在沟槽的周边区域的基极区域上方的栅极氧化层上形成栅电极，在第一层的第二面上形成漏电极。

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