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1. 发明申请

US20080059707A1 Selective storage of data in levels of a cache memory 失效
标题翻译：在高速缓冲存储器的级别中选择性地存储数据
公开(公告)号：US20080059707A1
公开(公告)日：2008-03-06
申请号：US11513554
申请日：2006-08-31
申请人： Srihari Makineni , Jaideep Moses , Ravishankar Iyer , Ramesh Illikkal , Don Newell , Li Zhao
发明人： Srihari Makineni , Jaideep Moses , Ravishankar Iyer , Ramesh Illikkal , Don Newell , Li Zhao
IPC分类号： G06F12/00
CPC分类号： G06F12/0897 , G06F12/128
摘要： In one embodiment, the present invention includes a method for incrementing a counter value associated with a cache line if the cache line is inserted into a first level cache, and storing the cache line into a second level cache coupled to the first level cache or a third level cache coupled to the second level cache based on the counter value, after eviction from the first level cache. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于在高速缓存行插入到第一级高速缓存中时递增与高速缓存线相关联的计数器值的方法，并且将高速缓存行存储到耦合到第一级高速缓存的第二级高速缓存或在从第一级高速缓存驱逐之后，基于计数器值耦合到第二级高速缓存的第三级缓存。描述和要求保护其他实施例。

2. 发明授权

US08799902B2 Priority based throttling for power/performance quality of service 有权
标题翻译：基于优先级的电源/性能质量服务节制
公开(公告)号：US08799902B2
公开(公告)日：2014-08-05
申请号：US11786019
申请日：2007-04-09
申请人： Ramesh Kumar Illikkal , Ravishankar Iyer , Jaideep Moses , Don Newell , Tryggve Fossum
发明人： Ramesh Kumar Illikkal , Ravishankar Iyer , Jaideep Moses , Don Newell , Tryggve Fossum
IPC分类号： G06F9/46 , G06F1/00 , G06F1/26 , G06F1/32 , G06F15/173
CPC分类号： G06F9/5077 , G06F9/5094 , G06F2209/504 , Y02D10/22 , Y02D10/36
摘要： A method and apparatus for throttling power and/or performance of processing elements based on a priority of software entities is herein described. Priority aware power management logic receives priority levels of software entities and modifies operating points of processing elements associated with the software entities accordingly. Therefore, in a power savings mode, processing elements executing low priority applications/tasks are reduced to a lower operating point, i.e. lower voltage, lower frequency, throttled instruction issue, throttled memory accesses, and/or less access to shared resources. In addition, utilization logic potentially trackes utilization of a resource per priority level, which allows the power manager to determine operating points based on the effect of each priority level on each other from the perspective of the resources themselves. Moreover, a software entity itself may assign operating points, which the power manager enforces.
摘要翻译：这里描述了一种基于软件实体的优先级来节制处理元件的功率和/或性能的方法和装置。优先级感知功率管理逻辑接收软件实体的优先级，并相应地修改与软件实体相关联的处理元件的工作点。因此，在省电模式中，执行低优先级应用/任务的处理元件被降低到较低的工作点，即较低的电压，较低的频率，节流的指令问题，节流的存储器访问和/或较少的对共享资源的访问。此外，利用逻辑潜在地追踪每个优先级别的资源的利用率，这允许电力管理者从资源本身的角度基于每个优先级的影响来确定工作点。此外，软件实体本身可以分配功率管理器执行的操作点。

3. 发明授权

US07596662B2 Selective storage of data in levels of a cache memory 失效
标题翻译：在高速缓冲存储器的级别中选择性地存储数据
公开(公告)号：US07596662B2
公开(公告)日：2009-09-29
申请号：US11513554
申请日：2006-08-31
申请人： Srihari Makineni , Jaideep Moses , Ravishankar Iyer , Ramesh Illikkal , Don Newell , Li Zhao
发明人： Srihari Makineni , Jaideep Moses , Ravishankar Iyer , Ramesh Illikkal , Don Newell , Li Zhao
IPC分类号： G06F12/00
CPC分类号： G06F12/0897 , G06F12/128
摘要： In one embodiment, the present invention includes a method for incrementing a counter value associated with a cache line if the cache line is inserted into a first level cache, and storing the cache line into a second level cache coupled to the first level cache or a third level cache coupled to the second level cache based on the counter value, after eviction from the first level cache. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于在高速缓存行插入到第一级高速缓存中时递增与高速缓存线相关联的计数器值的方法，并且将高速缓存行存储到耦合到第一级高速缓存的第二级高速缓存或在从第一级高速缓存驱逐之后，基于计数器值耦合到第二级高速缓存的第三级缓存。描述和要求保护其他实施例。

4. 发明申请

US20080250415A1 Priority based throttling for power/performance Quality of Service 有权
标题翻译：基于优先级的电源/性能调节服务质量
公开(公告)号：US20080250415A1
公开(公告)日：2008-10-09
申请号：US11786019
申请日：2007-04-09
申请人： Ramesh Kumar Illikkal , Ravishankar Iyer , Jaideep Moses , Don Newell , Tryggve Fossum
发明人： Ramesh Kumar Illikkal , Ravishankar Iyer , Jaideep Moses , Don Newell , Tryggve Fossum
IPC分类号： G06F9/46
CPC分类号： G06F9/5077 , G06F9/5094 , G06F2209/504 , Y02D10/22 , Y02D10/36
摘要： A method and apparatus for throttling power and/or performance of processing elements based on a priority of software entities is herein described. Priority aware power management logic receives priority levels of software entities and modifies operating points of processing elements associated with the software entities accordingly. Therefore, in a power savings mode, processing elements executing low priority applications/tasks are reduced to a lower operating point, i.e. lower voltage, lower frequency, throttled instruction issue, throttled memory accesses, and/or less access to shared resources. In addition, utilization logic potentially trackes utilization of a resource per priority level, which allows the power manager to determine operating points based on the effect of each priority level on each other from the perspective of the resources themselves. Moreover, a software entity itself may assign operating points, which the power manager enforces.
摘要翻译：这里描述了一种基于软件实体的优先级来节制处理元件的功率和/或性能的方法和装置。优先级感知功率管理逻辑接收软件实体的优先级，并相应地修改与软件实体相关联的处理元件的工作点。因此，在省电模式中，执行低优先级应用/任务的处理元件被降低到较低的工作点，即较低的电压，较低的频率，节流的指令问题，节流的存储器访问和/或较少的对共享资源的访问。此外，利用逻辑潜在地追踪每个优先级别的资源的利用率，这允许电力管理者从资源本身的角度基于每个优先级的影响来确定工作点。此外，软件实体本身可以分配功率管理器执行的操作点。

5. 发明授权

US07050394B2 Framer 有权
标题翻译：成帧器
公开(公告)号：US07050394B2
公开(公告)日：2006-05-23
申请号：US10323400
申请日：2002-12-18
申请人： Erik J. Johnson , Don Newell
发明人： Erik J. Johnson , Don Newell
IPC分类号： H04L12/56 , H04L12/26 , H04J1/16 , H04J3/14
CPC分类号： H04J3/1617 , Y10S370/912
摘要： A method includes extracting packets from within a received frame, generating digests of the extracted packets, and hashing the generated digests.
摘要翻译：一种方法包括从接收到的帧中提取分组，生成提取的分组的摘要，以及散列生成的摘要。

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