专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

GB2519259B Apparatus and method for reducing the flushing time of a cache 未知
公开(公告)号：GB2519259B
公开(公告)日：2020-08-19
申请号：GB201501454
申请日：2013-06-27
申请人： INTEL CORP , JAIDEEP MOSES , RAVISHANKAR IYER , RAMESH ILLIKKAL , SADAGOPAN SRINIVASAN
发明人： JAIDEEP MOSES , RAVISHANKAR IYER , RAMESH ILLIKKAL , SADAGOPAN SRINIVASAN
IPC分类号： G06F12/08
摘要： A processor is described having cache circuitry and logic circuitry. The logic circuitry is to manage the entry and removal of cache lines from the cache circuitry. The logic circuitry includes storage circuitry and control circuitry. The storage circuitry is to store information identifying a set of cache lines within the cache that are in a modified state. The control circuitry is coupled to the storage circuitry to receive the information from the storage circuitry, responsive to a signal to flush the cache, and determine addresses of the cache therefrom so that the set of cache lines are read from the cache so as to avoid reading cache lines from the cache that are in an invalid or a clean state.

2. 发明授权

US08984311B2 Method, apparatus, and system for energy efficiency and energy conservation including dynamic C0-state cache resizing 有权
标题翻译：包括动态C0状态缓存调整大小的节能和节能的方法，装置和系统
公开(公告)号：US08984311B2
公开(公告)日：2015-03-17
申请号：US13341657
申请日：2011-12-30
申请人： Jaideep Moses , Rameshkumar G. Illikkal , Ravishankar Iyer , Jared E. Bendt , Sadagopan Srinivasan , Andrew J. Herdrich , Ashish V. Choubal , Avinash N. Ananthakrishnan , Vijay S. R. Degalahal
发明人： Jaideep Moses , Rameshkumar G. Illikkal , Ravishankar Iyer , Jared E. Bendt , Sadagopan Srinivasan , Andrew J. Herdrich , Ashish V. Choubal , Avinash N. Ananthakrishnan , Vijay S. R. Degalahal
IPC分类号： G06F1/26 , G06F1/32
CPC分类号： G06F1/3275 , G06F1/3225 , G06F1/3287 , G06F12/0864 , G06F2212/1028 , G06F2212/601 , Y02D10/13 , Y02D10/14 , Y02D10/171
摘要： Embodiments of systems, apparatuses, and methods for energy-efficient operation of a device are described. In some embodiments, a cache performance indicator of a cache is monitored, and a set of one or more cache performance parameters based on the cache performance indicator is determined. The cache is dynamically resized to an optimal cache size based on a comparison of the cache performance parameters to their energy-efficient targets to reduce power consumption.
摘要翻译：描述了用于设备的能量效率操作的系统，装置和方法的实施例。在一些实施例中，监视高速缓存的高速缓存性能指示符，并且确定基于高速缓存性能指示符的一个或多个高速缓存性能参数的集合。基于缓存性能参数与其节能目标的比较来缓存高速缓存大小，以达到最佳高速缓存大小，从而降低功耗。

3. 发明申请

US20140095794A1 Apparatus and Method For Reducing The Flushing Time Of A Cache 有权
标题翻译：用于降低高速缓存冲洗时间的装置和方法
公开(公告)号：US20140095794A1
公开(公告)日：2014-04-03
申请号：US13631625
申请日：2012-09-28
申请人： Jaideep MOSES , Ravishankar IYER , Ramesh G. ILLIKKAL , Sadagopan SRINIVASAN
发明人： Jaideep MOSES , Ravishankar IYER , Ramesh G. ILLIKKAL , Sadagopan SRINIVASAN
IPC分类号： G06F12/08
CPC分类号： G06F12/08 , G06F12/0891
摘要： A processor is described having cache circuitry and logic circuitry. The logic circuitry is to manage the entry and removal of cache lines from the cache circuitry. The logic circuitry includes storage circuitry and control circuitry. The storage circuitry is to store information identifying a set of cache lines within the cache that are in a modified state. The control circuitry is coupled to the storage circuitry to receive the information from the storage circuitry, responsive to a signal to flush the cache, and determine addresses of the cache therefrom so that the set of cache lines are read from the cache so as to avoid reading cache lines from the cache that are in an invalid or a clean state.
摘要翻译：描述了具有高速缓存电路和逻辑电路的处理器。逻辑电路是管理高速缓存线路的高速缓存行的输入和移除。逻辑电路包括存储电路和控制电路。存储电路用于存储标识高速缓存中处于修改状态的一组高速缓存行的信息。控制电路耦合到存储电路，以响应于刷新高速缓存的信号从存储电路接收信息，并从其中确定高速缓存的地址，从而从高速缓存读取高速缓存行集合，以避免从缓存中读取处于无效或干净状态的缓存行。

4. 发明申请

US20080059707A1 Selective storage of data in levels of a cache memory 失效
标题翻译：在高速缓冲存储器的级别中选择性地存储数据
公开(公告)号：US20080059707A1
公开(公告)日：2008-03-06
申请号：US11513554
申请日：2006-08-31
申请人： Srihari Makineni , Jaideep Moses , Ravishankar Iyer , Ramesh Illikkal , Don Newell , Li Zhao
发明人： Srihari Makineni , Jaideep Moses , Ravishankar Iyer , Ramesh Illikkal , Don Newell , Li Zhao
IPC分类号： G06F12/00
CPC分类号： G06F12/0897 , G06F12/128
摘要： In one embodiment, the present invention includes a method for incrementing a counter value associated with a cache line if the cache line is inserted into a first level cache, and storing the cache line into a second level cache coupled to the first level cache or a third level cache coupled to the second level cache based on the counter value, after eviction from the first level cache. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于在高速缓存行插入到第一级高速缓存中时递增与高速缓存线相关联的计数器值的方法，并且将高速缓存行存储到耦合到第一级高速缓存的第二级高速缓存或在从第一级高速缓存驱逐之后，基于计数器值耦合到第二级高速缓存的第三级缓存。描述和要求保护其他实施例。

5. 发明授权

US07921276B2 Applying quality of service (QoS) to a translation lookaside buffer (TLB) 有权
标题翻译：将服务质量（QoS）应用于翻译后备缓冲区（TLB）
公开(公告)号：US07921276B2
公开(公告)日：2011-04-05
申请号：US11726316
申请日：2007-03-21
申请人： Ramesh Illikkal , Hari Kannan , Ravishankar Iyer , Donald Newell , Jaideep Moses , Li Zhao
发明人： Ramesh Illikkal , Hari Kannan , Ravishankar Iyer , Donald Newell , Jaideep Moses , Li Zhao
IPC分类号： G06F12/10
CPC分类号： G06F12/126
摘要： In one embodiment, the present invention includes a translation lookaside buffer (TLB) having storage locations each including a priority indicator field to store a priority level associated with an agent that requested storage of the data in the TLB, and an identifier field to store an identifier of the agent, where the TLB is apportioned according to a plurality of priority levels. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括具有存储位置的翻译后备缓冲器（TLB），每个存储位置包括优先级指示符字段以存储与请求TLB中的数据存储的代理相关联的优先级，以及存储代理商的标识符，其中TLB根据多个优先级分摊。描述和要求保护其他实施例。

6. 发明授权

US09473891B2 Mechanism for facilitating dynamic detection and communication of geo-locations for devices 有权
标题翻译：促进设备地理位置的动态检测和通信的机制
公开(公告)号：US09473891B2
公开(公告)日：2016-10-18
申请号：US14129958
申请日：2013-09-11
申请人： Robert A. Colby , Jaideep Moses , Mats Agerstam , Roy Ramon , Raguraman Barathalwar
发明人： Robert A. Colby , Jaideep Moses , Mats Agerstam , Roy Ramon , Raguraman Barathalwar
IPC分类号： H04W4/02 , H04W4/00
CPC分类号： H04W4/023 , H04W4/38 , H04W4/80
摘要： A mechanism is described for facilitating detection and communication of geo-locations for devices according to one embodiment. A method of embodiments, as described herein, includes tracking, at a first smart device, one or more devices including a second smart device, and first and second smart devices including a computing device, and establishing a first connection with the second smart device, establishing further comprising exchanging first location data between the first smart device and the second smart device, establishing further including communicating a first current location associated with the first smart device to the second smart device. The method may further include identifying a second current location associated with the second smart device. The second current location may be initially recorded and iteratively rewritten at a first local memory of the first smart device.
摘要翻译：描述了根据一个实施例的用于促进设备的地理位置的检测和通信的机制。如本文所述的实施例的方法包括在第一智能设备处跟踪包括第二智能设备的一个或多个设备以及包括计算设备的第一和第二智能设备以及建立与第二智能设备的第一连接，建立进一步包括在第一智能设备和第二智能设备之间交换第一位置数据，建立进一步包括将与第一智能设备相关联的第一当前位置传送到第二智能设备。该方法还可以包括识别与第二智能设备相关联的第二当前位置。可以在第一智能设备的第一本地存储器处初始地记录和迭代地重写第二当前位置。

7. 发明授权

US09360927B2 Power efficient processor architecture 有权
标题翻译：高效的处理器架构
公开(公告)号：US09360927B2
公开(公告)日：2016-06-07
申请号：US13992361
申请日：2011-09-06
申请人： Andrew J. Herdrich , Rameshkumar G. Illikkal , Ravishankar Iyer , Sadogopan Srinivasan , Jaideep Moses , Srihari Makineni
发明人： Andrew J. Herdrich , Rameshkumar G. Illikkal , Ravishankar Iyer , Sadogopan Srinivasan , Jaideep Moses , Srihari Makineni
IPC分类号： G06F1/32 , G06F9/50
CPC分类号： G06F1/3293 , G06F1/3206 , G06F1/3287 , G06F9/4418 , G06F9/5094 , G06F12/084 , G06F13/24 , G06F2212/1028 , G06F2212/60 , G06F2212/62 , H04W52/028 , H04W88/02 , Y02B70/30 , Y02B70/32 , Y02D10/122 , Y02D10/22 , Y02D70/00
摘要： In one embodiment, the present invention includes a method for receiving an interrupt from an accelerator, sending a resume signal directly to a small core responsive to the interrupt and providing a subset of an execution state of the large core to the first small core, and determining whether the small core can handle a request associated with the interrupt, and performing an operation corresponding to the request in the small core if the determination is in the affirmative, and otherwise providing the large core execution state and the resume signal to the large core. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于从加速器接收中断的方法，响应于该中断将恢复信号直接发送到小型核心，并向第一小型核心提供大型核心的执行状态的子集，以及确定小型核心是否可以处理与该中断有关的请求，如果该确定是肯定的，则执行与该小核心中的该请求相对应的操作，否则将大的核心执行状态和恢复信号提供给该大核心。描述和要求保护其他实施例。

8. 发明授权

US07895415B2 Cache sharing based thread control 有权
标题翻译：基于缓存共享的线程控制
公开(公告)号：US07895415B2
公开(公告)日：2011-02-22
申请号：US11705987
申请日：2007-02-14
申请人： Antonio Gonzalez , Josep M. Codina , Pedro Lopez , Fernando Latorre , Jose-Alejandro Pineiro , Enric Gibert , Jaume Abella , Jaideep Moses , Donald Newell , Ravishankar Iyer , Ramesh G. Illikkal , Srihari Makineni
发明人： Antonio Gonzalez , Josep M. Codina , Pedro Lopez , Fernando Latorre , Jose-Alejandro Pineiro , Enric Gibert , Jaume Abella , Jaideep Moses , Donald Newell , Ravishankar Iyer , Ramesh G. Illikkal , Srihari Makineni
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44 , G06F15/00
CPC分类号： G06F9/3851 , G06F9/3009 , G06F12/0842
摘要： Apparatus and computing systems associated with cache sharing based thread control are described. One embodiment includes a memory to store a thread control instruction and a processor to execute the thread control instruction. The processor is coupled to the memory. The processor includes a first unit to dynamically determine a cache sharing behavior between threads in a multi-threaded computing system and a second unit to dynamically control the composition of a set of threads in the multi-threaded computing system. The composition of the set of threads is based, at least in part, on thread affinity as exhibited by cache-sharing behavior. The thread control instruction controls the operation of the first unit and the second unit.
摘要翻译：描述与基于缓存共享的线程控制相关联的装置和计算系统。一个实施例包括存储线程控制指令的存储器和执行线程控制指令的处理器。处理器耦合到存储器。处理器包括第一单元，用于动态地确定多线程计算系统中的线程之间的高速缓存共享行为，以及第二单元，以动态地控制多线程计算系统中的一组线程的组合。该组线程的组合至少部分地基于缓存共享行为所表现的线程亲和性。线程控制指令控制第一单元和第二单元的操作。

9. 发明申请

US20090165004A1 Resource-aware application scheduling 审中-公开
标题翻译：资源感知应用程序调度
公开(公告)号：US20090165004A1
公开(公告)日：2009-06-25
申请号：US12004756
申请日：2007-12-21
申请人： Jaideep Moses , Don K. Newell , Ramesh Illikkal , Ravishankar Iyer , Srihari Makineni , Li Zhao , Scott Hahn , Tong N. Li , Padmashree Apparao
发明人： Jaideep Moses , Don K. Newell , Ramesh Illikkal , Ravishankar Iyer , Srihari Makineni , Li Zhao , Scott Hahn , Tong N. Li , Padmashree Apparao
IPC分类号： G06F9/46
CPC分类号： G06F9/505 , G06F2209/507 , G06F2209/508
摘要： In one embodiment, a method provides capturing resource monitoring information for a plurality of applications; accessing the resource monitoring information; and scheduling at least one of the plurality of applications on a selected processing core of a plurality of processing cores based, at least in part, on the resource monitoring information.
摘要翻译：在一个实施例中，一种方法提供捕获用于多个应用的资源监视信息; 访问资源监控信息; 以及至少部分地基于所述资源监视信息，在所述多个处理核心的所选择的处理核心上调度所述多个应用中的至少一个。

10. 发明申请

US20080244221A1 EXPOSING SYSTEM TOPOLOGY TO THE EXECUTION ENVIRONMENT 审中-公开
标题翻译：对执行环境的暴露系统拓扑
公开(公告)号：US20080244221A1
公开(公告)日：2008-10-02
申请号：US11694322
申请日：2007-03-30
申请人： Donald K. Newell , Jaideep Moses , Ravishankar Iyer , Rameshkumar G. Illikkal , Srihari Makineni
发明人： Donald K. Newell , Jaideep Moses , Ravishankar Iyer , Rameshkumar G. Illikkal , Srihari Makineni
IPC分类号： G06F15/00
CPC分类号： G06F15/16
摘要： Embodiments of apparatuses, methods, and systems for exposing system topology to an execution environment are disclosed. In one embodiment, an apparatus includes execution cores and resources on a single integrated circuit, and topology logic. The topology logic is to populate a data structure with information regarding a relationship between the execution cores and the resources.
摘要翻译：公开了将系统拓扑暴露给执行环境的装置，方法和系统的实施例。在一个实施例中，装置包括在单个集成电路上的执行核心和资源以及拓扑逻辑。拓扑逻辑是使用关于执行核心和资源之间的关系的信息来填充数据结构。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式