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1. 发明授权

US6154804A Multiprocessor communication using reduced addressing lines 失效
标题翻译：使用减少寻址行的多处理器通信
公开(公告)号：US6154804A
公开(公告)日：2000-11-28
申请号：US250232
申请日：1999-02-15
申请人： Javier F. Izquierdo , John A. Landry
发明人： Javier F. Izquierdo , John A. Landry
IPC分类号： G06F12/02 , G06F12/08 , G06F15/17 , G06F13/00
CPC分类号： G06F15/17 , G06F12/0284 , G06F12/0806
摘要： A method for communication between multiple processors using registers that are accessed by four register select lines which are translated from the original system address. The address translation is performed off of the main processor board to reduce loading effects on the local bus and reduces the pin count of processor board. A signal representing which of the processors is currently active is used as a pseudo address line for the purpose of the translation. The original addresses of the I/O registers may be either input/output or memory mapped.
摘要翻译：一种使用由原始系统地址翻译的四个寄存器选择线访问的寄存器的多个处理器之间进行通信的方法。地址转换是从主处理器板执行的，以减少对本地总线的负载影响，并减少处理器板的引脚数。代表处理器当前处于活动状态的信号被用作用于转换目的的伪地址线。 I / O寄存器的原始地址可以是输入/输出或存储器映射。

2. 发明授权

US5656961A High frequency clock signal distribution with high voltage output 失效
标题翻译：高频时钟信号分配具有高电压输出
公开(公告)号：US5656961A
公开(公告)日：1997-08-12
申请号：US135086
申请日：1993-10-12
申请人： Thanh Thien Tran , Clarence Y. Mar , Javier F. Izquierdo
发明人： Thanh Thien Tran , Clarence Y. Mar , Javier F. Izquierdo
IPC分类号： G06F1/10 , H03K19/018 , H03K12/00 , G06F1/04
CPC分类号： G06F1/10 , H03K19/01806
摘要： A clock signal is distributed over a circuit board and across a connector as a sine wave. A circuit located near the clocked circuitry converts the sine wave into a same frequency square wave for use by the clocked circuitry. The output stage of the converter circuitry provides a high output level to drive CMOS circuitry. The output transistor is pulled up to 5 volts, but the preceding transistors are pulled up to 6.3 volts so that the base to emitter drops are compensated.
摘要翻译：时钟信号分布在电路板上，并以连接器的形式分布在正弦波上。位于时钟电路附近的电路将正弦波转换成相同的频率方波，供时钟电路使用。转换器电路的输出级提供高输出电平来驱动CMOS电路。输出晶体管被上拉至5伏特，但是先前的晶体管被上拉至6.3伏，从而补偿基极到发射极的下降。

3. 发明授权

US5341494A Memory accessing system with an interface and memory selection unit utilizing write protect and strobe signals 失效
标题翻译：存储器访问系统，具有使用写保护和选通信号的接口和存储器选择单元
公开(公告)号：US5341494A
公开(公告)日：1994-08-23
申请号：US165514
申请日：1993-12-10
申请人： John S. Thayer , Dale J. Mayer , Javier F. Izquierdo , Paul R. Culley , John A. Landry
发明人： John S. Thayer , Dale J. Mayer , Javier F. Izquierdo , Paul R. Culley , John A. Landry
IPC分类号： G06F12/06
CPC分类号： G06F12/0653
摘要： A memory mapping and module enabling circuit for allowing logical 128 kbyte memory blocks to be defined for any location in any module connected to a memory system. A RAM is addressed by the system address lines defining 128 kbyte blocks, with the output data providing the row address strobe enable signals for a particular memory module and the address values necessary to place the 128 kbyte block within the module. Various other parameters such as write protect status and memory location are also provided by the RAM. Circuits and techniques for programming and reading the RAM are provided.
摘要翻译：存储器映射和模块使能电路，用于允许为连接到存储器系统的任何模块中的任何位置定义逻辑128K字节的存储器块。 RAM由定义128千字节块的系统地址线寻址，输出数据为特定存储器模块提供行地址选通使能信号，以及将128K字节块放置在模块内所需的地址值。各种其他参数，如写保护状态和存储器位置也由RAM提供。提供了用于编程和读取RAM的电路和技术。

4. 发明授权

US5281861A Sine wave clock distribution with high voltage output 失效
标题翻译：正弦波时钟分配具有高电压输出
公开(公告)号：US5281861A
公开(公告)日：1994-01-25
申请号：US855453
申请日：1992-03-19
申请人： Thanh T. Tran , Clarence Y. Mar , Javier F. Izquierdo
发明人： Thanh T. Tran , Clarence Y. Mar , Javier F. Izquierdo
IPC分类号： G06F1/10 , H03K19/018 , H03K5/00 , H03B19/00 , H03K5/13 , H03K7/00
CPC分类号： G06F1/10 , H03K19/01806
摘要： A clock signal is distributed over a circuit board and across a connector as a sine wave. A circuit located near the clocked circuitry converts the sine wave into a same frequency square wave for use by the clocked circuitry. The output stage of the converter circuitry provides a high output level to drive CMOS circuitry. The output transistor is pulled up to 5 volts, but the preceding transistors are pulled up to 6.3 volts so that the base to emitter drops are compensated.
摘要翻译：时钟信号分布在电路板上，并以连接器的形式分布在正弦波上。位于时钟电路附近的电路将正弦波转换成相同的频率方波，供时钟电路使用。转换器电路的输出级提供高输出电平来驱动CMOS电路。输出晶体管被上拉至5伏特，但是先前的晶体管被上拉至6.3伏，从而补偿基极到发射极的下降。

5. 发明授权

US5201055A Multiprocessing system includes interprocessor encoding and decoding logic used for communication between two cards through reduced addressing lines 失效
标题翻译：多协议系统包括用于通过减少寻址线路的两个卡之间进行通信的交织器编码和解码逻辑
公开(公告)号：US5201055A
公开(公告)日：1993-04-06
申请号：US431659
申请日：1989-11-03
申请人： Javier F. Izquierdo , John A. Landry
发明人： Javier F. Izquierdo , John A. Landry
IPC分类号： G06F12/02 , G06F12/08 , G06F15/17
CPC分类号： G06F15/17 , G06F12/0284 , G06F12/0806
摘要： A method for communication between multiple processors using registers that are accessed by four register select lines which are translated from the original system address. The address translation is performed off of the main processor board to reduce loading effects on the local bus and reduces the pin count of processor board. A signal representing which of the processors is currently active is used as a pseudo address line for the purpose of the translation. The original addresses of the I/O registers may be either input/output or memory mapped.

6. 发明授权

US5611078A Method and apparatus for independently resetting processors and cache controllers in multiple processor systems 失效
标题翻译：用于在多个处理器系统中独立地重置处理器和缓存控制器的方法和装置
公开(公告)号：US5611078A
公开(公告)日：1997-03-11
申请号：US480874
申请日：1995-06-07
申请人： David A. Miller , Kenneth A. Jansen , Paul R. Culley , Mark Taylor , Javier F. Izquierdo
发明人： David A. Miller , Kenneth A. Jansen , Paul R. Culley , Mark Taylor , Javier F. Izquierdo
IPC分类号： G06F1/24 , G06F12/08 , G06F15/177 , G06F13/00
CPC分类号： G06F12/0802 , G06F1/24 , G06F15/177
摘要： A method and system for independently resetting primary and secondary processors 20 and 120 respectively under program control in a multiprocessor, cache memory system. Processors 20 and 120 are reset without causing cache memory controllers 24 and 124 to reset.
摘要翻译：一种用于在多处理器，高速缓冲存储器系统中的程序控制下分别独立地重置主处理器20和第二处理器120的方法和系统。复位处理器20和120而不使高速缓冲存储器控制器24和124复位。

7. 发明授权

US09116676B2 Power distribution to computer system 有权
标题翻译：配电到电脑系统
公开(公告)号：US09116676B2
公开(公告)日：2015-08-25
申请号：US13320947
申请日：2009-06-23
申请人： Javier F. Izquierdo , Ronald D. Noblett
发明人： Javier F. Izquierdo , Ronald D. Noblett
IPC分类号： G06F1/26 , G06F1/32 , H02J1/08
CPC分类号： G06F1/26 , G06F1/3203 , H02J1/08
摘要： Power distribution to computer systems. At least some of the illustrative embodiments are systems including a power supply configured to convert an alternating current (AC) power signal to a direct current (DC) power signal (and the power supply comprising a first power port and a second power port, the second power port different than the first power port), a first computer system coupled to the first power port (the power supply configured to provide DC operational power to the first computer system through the first power port, and the first computer system the only computer system receiving operational power through the first power port), and a second computer system different than the first computer system (the power supply configured to provide DC operational power to the second computer system through the second power port, and the second computer system the only computer system receiving power from the second power port).
摘要翻译：配电到计算机系统。至少一些说明性实施例是系统，其包括被配置为将交流（AC）功率信号转换为直流（DC）功率信号的电源（以及包括第一电源端口和第二电源端口的电源，第二电源端口与第一电源端口不同），耦合到第一电源端口的第一计算机系统（被配置为通过第一电源端口向第一计算机系统提供DC操作电力的电源，以及第一计算机系统，唯一的计算机系统通过第一电源端口接收操作电力）和与第一计算机系统不同的第二计算机系统（被配置为通过第二电源端口向第二计算机系统提供DC操作电力的电源，以及仅第二计算机系统的唯一的计算机系统从第二电源端口接收电力）。

8. 发明授权

US5884054A Multiprocessor system including interprocessor encoding and decoding logic for communication between two cards through reduced addressing lines 失效
标题翻译：多处理器系统包括处理器编码和解码逻辑，用于通过减少寻址行在两个卡之间进行通信
公开(公告)号：US5884054A
公开(公告)日：1999-03-16
申请号：US001091
申请日：1993-01-06
申请人： Javier F. Izquierdo , John A. Landry
发明人： Javier F. Izquierdo , John A. Landry
IPC分类号： G06F12/02 , G06F12/08 , G06F15/17 , G06F13/00
CPC分类号： G06F15/17 , G06F12/0284 , G06F12/0806
摘要： A method for communication between multiple processors using registers that are accessed by four register select lines which are translated from the original system address. The address translation is performed off of the main processor board to reduce loading effects on the local bus and reduces the pin count of processor board. A signal representing which of the processors is currently active is used as a pseudo address line for the purpose of the translation. The original addresses of the I/O registers may be either input/output or memory mapped.
摘要翻译：一种使用由原始系统地址翻译的四个寄存器选择线访问的寄存器的多个处理器之间进行通信的方法。地址转换是从主处理器板执行的，以减少对本地总线的负载影响，并减少处理器板的引脚数。代表处理器当前处于活动状态的信号被用作用于转换目的的伪地址线。 I / O寄存器的原始地址可以是输入/输出或存储器映射。

9. 发明授权

US5870602A Multi-processor system with system wide reset and partial system reset capabilities 失效
标题翻译：具有系统复位和部分系统复位功能的多处理器系统
公开(公告)号：US5870602A
公开(公告)日：1999-02-09
申请号：US14369
申请日：1998-01-27
申请人： David A. Miller , Kenneth A. Jansen , Paul R. Culley , Mark Taylor , Javier F. Izquierdo
发明人： David A. Miller , Kenneth A. Jansen , Paul R. Culley , Mark Taylor , Javier F. Izquierdo
IPC分类号： G06F1/24 , G06F9/00
CPC分类号： G06F1/24
摘要： A multiprocessor system includes first and second processing units. Each of these processing units includes at least a processor and preferably also a cache memory, a cache memory controller and a numerical coprocessor. Each processing unit is reset in response to a system reset signal but only selected portions of the processing units are reset in response to a partial-reset signal. The system can also include a number other components such as video circuitry, a hard disk drive, bus interface circuitry, a speaker, a keyboard controller and a keyboard.
摘要翻译：多处理器系统包括第一和第二处理单元。这些处理单元中的每一个至少包括处理器，优选地还包括高速缓冲存储器，高速缓冲存储器控制器和数字协处理器。每个处理单元响应于系统复位信号被复位，但只响应于部分复位信号来复位处理单元的选定部分。该系统还可以包括许多其他组件，例如视频电路，硬盘驱动器，总线接口电路，扬声器，键盘控制器和键盘。

10. 发明申请

US20120084579A1 Power Distribution To Computer System 有权
标题翻译：配电到计算机系统
公开(公告)号：US20120084579A1
公开(公告)日：2012-04-05
申请号：US13320947
申请日：2009-06-23
申请人： Javier F. Izquierdo , Ronald D. Noblett
发明人： Javier F. Izquierdo , Ronald D. Noblett
IPC分类号： G06F1/26
CPC分类号： G06F1/26 , G06F1/3203 , H02J1/08
摘要： Power distribution to computer systems. At least some of the illustrative embodiments are systems including a power supply configured to convert an alternating current (AC) power signal to a direct current (DC) power signal (and the power supply comprising a first power port and a second power port, the second power port different than the first power port), a first computer system coupled to the first power port (the power supply configured to provide DC operational power to the first computer system through the first power port, and the first computer system the only computer system receiving operational power through the first power port), and a second computer system different than the first computer system (the second computer system coupled to the second power port, the power supply configured to provide DC operational power to the second computer system through the second power port, and the second computer system the only computer system receiving operational power from the second power port).
摘要翻译：配电到计算机系统。至少一些说明性实施例是系统，其包括被配置为将交流（AC）功率信号转换为直流（DC）功率信号的电源（以及包括第一电源端口和第二电源端口的电源，第二电源端口与第一电源端口不同），耦合到第一电源端口的第一计算机系统（被配置为通过第一电源端口向第一计算机系统提供DC操作电力的电源，以及第一计算机系统，唯一的计算机系统通过第一电源端口接收操作电力），以及与第一计算机系统不同的第二计算机系统（第二计算机系统耦合到第二电源端口，电源被配置为通过第二计算机系统向第二计算机系统提供DC操作电力第二电源端口和第二计算机系统，唯一的计算机系统从第二电源端口接收操作电源）。

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