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1. 发明授权

US08916930B2 Trenched power semiconductor device and fabrication method thereof 有权
标题翻译：沟槽功率半导体器件及其制造方法
公开(公告)号：US08916930B2
公开(公告)日：2014-12-23
申请号：US13223603
申请日：2011-09-01
申请人： Yuan-Shun Chang , Yi-Yun Tsai , Kao-Way Tu
发明人： Yuan-Shun Chang , Yi-Yun Tsai , Kao-Way Tu
IPC分类号： H01L29/78 , H01L21/336 , H01L29/66 , H01L29/417 , H01L29/40 , H01L29/06 , H01L21/74 , H01L29/423 , H01L29/08
CPC分类号： H01L29/7809 , H01L21/74 , H01L29/0623 , H01L29/0653 , H01L29/0878 , H01L29/0882 , H01L29/407 , H01L29/41766 , H01L29/42368 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7811 , H01L29/7812 , H01L29/7813
摘要： A trenched power semiconductor device on a lightly doped substrate is provided. The device has a base, a plurality of trenches including at least a gate trench, a plurality of first heavily doping regions, a body region, a source doped region, a contact window, a second heavily doped region, and a metal layer. The trenches are formed in the base. The first heavily doped regions are beneath the trenches respectively and spaced from the bottom of the respective trench with a lightly doped region. The body region encircles the trenches and is away from the first heavily doped region with a predetermined distance. The source doped region is in an upper portion of the body region. The contact window is adjacent to the edge of the base. The second heavily doped region is below the contact window filled by the metal layer for electrically connecting the second heavily doped region.
摘要翻译：提供了一种在轻掺杂衬底上的沟槽功率半导体器件。该器件具有基极，至少包括栅极沟槽，多个第一重掺杂区域，体区域，源极掺杂区域，接触窗口，第二重掺杂区域和金属层的多个沟槽。沟槽形成在基部。第一重掺杂区域分别在沟槽下方并且与具有轻掺杂区域的相应沟槽的底部间隔开。体区域包围沟槽并且以预定距离远离第一重掺杂区域。源极掺杂区域位于体区的上部。接触窗口与基座的边缘相邻。第二重掺杂区域在由用于电连接第二重掺杂区域的金属层填充的接触窗口的下方。

2. 发明授权

US08735249B2 Trenched power semiconductor device and fabrication method thereof 有权
标题翻译：沟槽功率半导体器件及其制造方法
公开(公告)号：US08735249B2
公开(公告)日：2014-05-27
申请号：US13115951
申请日：2011-05-25
申请人： Yi-Yun Tsai , Yuan-Shun Chang , Kao-Way Tu
发明人： Yi-Yun Tsai , Yuan-Shun Chang , Kao-Way Tu
IPC分类号： H01L21/326
CPC分类号： H01L29/7809 , H01L21/2253 , H01L21/2257 , H01L29/0623 , H01L29/0634 , H01L29/0878 , H01L29/0882 , H01L29/0886 , H01L29/407 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/66727 , H01L29/66734 , H01L29/7397 , H01L29/7811 , H01L29/7813
摘要： A trenched power semiconductor device on a lightly doped substrate is provided. Firstly, a plurality of trenches including at least a gate trench and a contact window are formed on the lightly doped substrate. Then, at least two trench-bottom heavily doped regions are formed at the bottoms of the trenches. These trench-bottom heavily doped regions are then expanded to connect with each other by using thermal diffusion process so as to form a conductive path. Afterward, the gate structure and the well are formed above the trench-bottom heavily doped regions, and then a conductive structure is formed in the contact window to electrically connect the trench-bottom heavily doped regions to an electrode.
摘要翻译：提供了一种在轻掺杂衬底上的沟槽功率半导体器件。首先，在轻掺杂衬底上形成至少包括栅极沟槽和接触窗口的多个沟槽。然后，在沟槽的底部形成至少两个沟底重掺杂区域。然后通过使用热扩散工艺将这些沟底重掺杂区域扩展以彼此连接，从而形成导电路径。之后，栅极结构和阱形成在沟槽底部重掺杂区域上方，然后在接触窗口中形成导电结构，以将沟槽底部重掺杂区域电连接到电极。

3. 发明授权

US08222689B2 High-voltage metal oxide semiconductor device and fabrication method thereof 有权
标题翻译：高压金属氧化物半导体器件及其制造方法
公开(公告)号：US08222689B2
公开(公告)日：2012-07-17
申请号：US12285179
申请日：2008-09-30
申请人： Kao-Way Tu
发明人： Kao-Way Tu
IPC分类号： H01L29/66
CPC分类号： H01L29/7802 , H01L29/0619 , H01L29/0623 , H01L29/0634 , H01L29/407 , H01L29/42376 , H01L29/66734 , H01L29/7808 , H01L29/7811 , H01L29/7813
摘要： A high-voltage metal oxide semiconductor device comprising a main body of a first conductivity type, a conductive structure, a first well of a second conductivity type, a source region of the first conductivity type, and a second well of the second conductivity type is provided. The conductive structure has a first portion and a second portion. The first portion is extended from an upper surface of the main body into the main body. The second portion is extended along the upper surface of the main body. The first well is located in the main body and below the second portion. The first well is kept away from the first portion with a predetermined distance. The source region is located in the first well. The second well is located in the main body and extends from a bottom of the first portion to a place close to a drain region.
摘要翻译：一种高电压金属氧化物半导体器件，包括第一导电类型的主体，导电结构，第二导电类型的第一阱，第一导电类型的源极区和第二导电类型的第二阱，提供。导电结构具有第一部分和第二部分。第一部分从主体的上表面延伸到主体。第二部分沿着主体的上表面延伸。第一口井位于主体中，并位于第二部分之下。第一个井以预定距离远离第一部分。源区位于第一井。第二井位于主体中并且从第一部分的底部延伸到靠近排水区的位置。

4. 发明申请

US20110057254A1 METAL-OXIDE-SEMICONDUCTOR CHIP AND FABRICATION METHOD THEREOF 有权
标题翻译：金属氧化物半导体芯片及其制造方法
公开(公告)号：US20110057254A1
公开(公告)日：2011-03-10
申请号：US12556715
申请日：2009-09-10
申请人： Kuo-Chang Tsen , Kao-Way Tu
发明人： Kuo-Chang Tsen , Kao-Way Tu
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L24/05 , H01L23/4824 , H01L24/03 , H01L24/06 , H01L24/16 , H01L29/0657 , H01L29/41766 , H01L29/66734 , H01L29/7809 , H01L29/7811 , H01L29/7813 , H01L2224/0401 , H01L2224/05599 , H01L2924/00014 , H01L2924/01005 , H01L2924/01033 , Y10S438/977
摘要： A metal-oxide-semiconductor chip having a semiconductor substrate, an epitaxial layer, at least a MOS cell, and a metal pattern layer is provided. The epitaxial layer is located on the semiconductor substrate and has an active region, a termination region, and a scribe line preserving region defined on an upper surface thereof. An etched sidewall of the epitaxial layer is located in the scribe line preserving region. The boundary portion of the upper surface of the semiconductor substrate is thus exposed. The MOS cell is located in the active region. The metal pattern layer is located on the epitaxial layer and has a gate pad coupled to the gate of the MOS cell, a source pad coupled to the source of the MOS cell, and a drain pattern, which is partly located on the upper surface of the semiconductor substrate.
摘要翻译：提供了具有半导体衬底，外延层，至少MOS单元和金属图案层的金属氧化物半导体芯片。外延层位于半导体衬底上，并具有限定在其上表面上的有源区，端接区和划线保留区。外延层的蚀刻侧壁位于划线保留区域中。因此，半导体衬底的上表面的边界部分露出。 MOS单元位于活动区域。金属图案层位于外延层上，并且具有耦合到MOS单元的栅极的栅极焊盘，耦合到MOS单元的源极的源极焊盘和部分位于MOS单元的上表面上的漏极图案半导体衬底。

5. 发明授权

US07838343B2 Semiconductor structure and fabrication method thereof 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US07838343B2
公开(公告)日：2010-11-23
申请号：US12403660
申请日：2009-03-13
申请人： Kao-Way Tu , Cheng-Hui Tung
发明人： Kao-Way Tu , Cheng-Hui Tung
IPC分类号： H01L21/332
CPC分类号： H01L27/088 , H01L29/0619 , H01L29/42372 , H01L29/66719 , H01L29/66727 , H01L29/7811
摘要： A semiconductor fabrication process according to the present invention defines an auxiliary structure with a plurality of spaces with a predetermined line-width in the oxide layer to prevent the conductive material in the spaces from being removed by etching or defined an auxiliary structure to rise the conductive structure so as to have the conductive structure being exposed by chemical mechanical polishing. Thus, the transmitting circuit can be defined without requiring an additional mask. Hence, the semiconductor fabrication process can reduce the number of required masks to lower the cost.
摘要翻译：根据本发明的半导体制造方法限定了在氧化物层中具有预定线宽的多个空间的辅助结构，以防止通过蚀刻或限定辅助结构来使空间中的导电材料被去除以使导电结构，使得导电结构通过化学机械抛光曝光。因此，可以限定发射电路而不需要额外的掩模。因此，半导体制造过程可以减少所需的掩模的数量以降低成本。

6. 发明申请

US20100171171A1 Trench mosfet device with low gate charge and the manfacturing method thereof 有权
标题翻译：具有低栅极电荷的沟槽mosfet器件及其制造方法
公开(公告)号：US20100171171A1
公开(公告)日：2010-07-08
申请号：US12453281
申请日：2009-05-06
申请人： Hsiu-Wen Hsu , Chun We Ni , Kao- Way Tu
发明人： Hsiu-Wen Hsu , Chun We Ni , Kao- Way Tu
IPC分类号： H01L29/78 , H01L21/28
CPC分类号： H01L29/7813 , H01L21/2815 , H01L29/407 , H01L29/42376 , H01L29/4933 , H01L29/66734
摘要： A method for manufacturing trench MOSFET device with low gate charge includes the steps of providing a substrate of first conductivity type; forming an epitaxial layer of first conductivity type on the substrate; forming a body region of second conductivity type in the epitaxial layer, the body region extends downwards from the surface of the epitaxial layer; forming a plurality of trenches in the epitaxial layer, the body region having the trenches formed therethrough; forming a first insulating layer on the body region and on an inner surface of each trench; forming a ploy-silicon spacer on the first insulating layer on an inner side-wall of each trench; filling a dielectric structure in the lower portion of each trench; and filling a ploy-silicon structure on top of the dielectric structure in each trench. Through the trench MOSFET device, the gate capacitance and resistance thereof are reduced so the performance is increased.
摘要翻译：具有低栅极电荷的沟槽MOSFET器件的制造方法包括提供第一导电类型的衬底的步骤; 在衬底上形成第一导电类型的外延层; 在所述外延层中形成第二导电类型的体区，所述体区从所述外延层的表面向下延伸; 在所述外延层中形成多个沟槽，所述主体区域具有穿过其形成的沟槽; 在所述主体区域和每个沟槽的内表面上形成第一绝缘层; 在每个沟槽的内侧壁上的第一绝缘层上形成合金硅衬垫; 在每个沟槽的下部填充电介质结构; 并在每个沟槽中的电介质结构的顶部上填充硅 - 硅结构。通过沟槽MOSFET器件，栅极电容和电阻降低，从而性能提高。

7. 发明申请

US20100025762A1 SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US20100025762A1
公开(公告)日：2010-02-04
申请号：US12403660
申请日：2009-03-13
申请人： Kao-Way Tu , Cheng-Hui Tung
发明人： Kao-Way Tu , Cheng-Hui Tung
IPC分类号： H01L29/78 , H01L29/06 , H01L21/336
CPC分类号： H01L27/088 , H01L29/0619 , H01L29/42372 , H01L29/66719 , H01L29/66727 , H01L29/7811
摘要： A semiconductor fabrication process according to the present invention defines an auxiliary structure with a plurality of spaces with a predetermined line-width in the oxide layer to prevent the conductive material in the spaces from being removed by etching or defined an auxiliary structure to rise the conductive structure so as to have the conductive structure being exposed by chemical mechanical polishing. Thus, the transmitting circuit can be defined without requiring an additional mask. Hence, the semiconductor fabrication process can reduce the number of required masks to lower the cost.
摘要翻译：根据本发明的半导体制造方法限定了在氧化物层中具有预定线宽的多个空间的辅助结构，以防止通过蚀刻或限定辅助结构来使空间中的导电材料被去除以使导电结构，使得导电结构通过化学机械抛光曝光。因此，可以限定发射电路而不需要额外的掩模。因此，半导体制造过程可以减少所需的掩模的数量以降低成本。

8. 发明申请

US20090085105A1 TRENCH MOSFET AND METHOD OF MANUFACTURE UTILIZING TWO MASKS 失效
标题翻译： TRENCH MOSFET和使用两个掩模的制造方法
公开(公告)号：US20090085105A1
公开(公告)日：2009-04-02
申请号：US11866365
申请日：2007-10-02
申请人： Shih Tzung Su , Jun Zeng , Poi Sun , Kao Way Tu , Tai Chiang Chen , Long Lv , Xin Wang
发明人： Shih Tzung Su , Jun Zeng , Poi Sun , Kao Way Tu , Tai Chiang Chen , Long Lv , Xin Wang
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L29/0661 , H01L29/407 , H01L29/41766 , H01L29/4236 , H01L29/42372 , H01L29/4238 , H01L29/456 , H01L29/4925 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7811
摘要： A method for manufacturing a trench MOSFET semiconductor device comprises: providing a heavily doped N+ silicon substrate; forming an N type epitaxial layer; forming a thick SiO2 layer; creating P body and source area formations by ion implantation without any masks; utilizing a first mask to define openings for a trench gate and a termination; thermally growing a gate oxide layer followed by formation of a thick poly-Silicon refill layer without a mask to define a gate bus area; forming sidewall spacers; forming P+ areas; removing the sidewall spacers; depositing tungsten to fill contacts and vias; depositing a first thin barrier metal layer; depositing a first thick metal layer; utilizing a second metal mask to open a gate bus area; forming second sidewall spacers; depositing a second thin barrier metal layer; depositing a second thick metal layer; and planarizing at least the second thick metal layer and the second thin metal layer to isolate the source metal portions from gate metal portions, whereby the trench MOSFET semiconductor device is manufactured utilizing only first and second masks.
摘要翻译：一种用于制造沟槽MOSFET半导体器件的方法包括：提供重掺杂的N +硅衬底; 形成N型外延层; 形成厚的SiO 2层; 通过离子注入创建P体和源区形成，而不需要任何掩模; 利用第一掩模来限定沟槽栅极和终端的开口; 热生长栅极氧化层，随后形成厚度不含掩模的多晶硅替代层，以限定栅极总线面积; 形成侧壁间隔物; 形成P +区域; 去除侧壁间隔物; 沉积钨以填充触点和通孔; 沉积第一薄的阻挡金属层; 沉积第一厚金属层; 利用第二金属掩模打开闸总线区域; 形成第二侧壁间隔物; 沉积第二薄的阻挡金属层; 沉积第二厚金属层; 并且至少平面化第二厚金属层和第二薄金属层以将源极金属部分与栅极金属部分隔离，由此仅利用第一和第二掩模制造沟槽MOSFET半导体器件。

9. 发明授权

US08399921B2 Metal oxide semiconductor (MOS) structure and manufacturing method thereof 有权
标题翻译：金属氧化物半导体（MOS）结构及其制造方法
公开(公告)号：US08399921B2
公开(公告)日：2013-03-19
申请号：US12567194
申请日：2009-09-25
申请人： Kao-Way Tu
发明人： Kao-Way Tu
IPC分类号： H01L29/78
CPC分类号： H01L29/7811 , H01L29/0634 , H01L29/0696 , H01L29/41766 , H01L29/4236 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7813
摘要： The manufacturing method includes the steps of: providing a semiconductor base of a first conduction type; forming a first epitaxial layer with a plurality of epitaxial pillars of therein on a first surface of the semiconductor base, wherein the epitaxial pillars have a conduction type opposite to the first epitaxial layer; forming a plurality of first shallow trenches and a plurality of second shallow trenches alternately on the epitaxial pillars and the first epitaxial layer, wherein the first shallow trench has a width greater than the width of the second shallow trench and the first shallow trench is extended downward to the epitaxial pillar; and forming a plurality of gate regions in the first shallow trenches respectively; forming a plurality of source regions on both sides of the first shallow trench; and forming a source metal conducting wire to connect the source regions.
摘要翻译：该制造方法包括以下步骤：提供第一导电类型的半导体基底; 在所述半导体基底的第一表面上形成具有多个外延柱的第一外延层，其中所述外延柱具有与所述第一外延层相反的导电类型; 在所述外延柱和所述第一外延层上交替地形成多个第一浅沟槽和多个第二浅沟槽，其中所述第一浅沟槽的宽度大于所述第二浅沟槽的宽度，并且所述第一浅沟槽向下延伸到外延柱; 以及分别在所述第一浅沟槽中形成多个栅极区域; 在所述第一浅沟槽的两侧形成多个源极区域; 以及形成源极金属导线以连接源极区域。

10. 发明申请

US20120040503A1 FABRICATION METHOD OF INTEGRATING POWER TRANSISTOR AND SCHOTTKY DIODE ON A MONOLITHIC SUBSTRATE 审中-公开
标题翻译：在单片基板上集成功率晶体管和肖特基二极管的制造方法
公开(公告)号：US20120040503A1
公开(公告)日：2012-02-16
申请号：US12854280
申请日：2010-08-11
申请人： KAO-WAY TU
发明人： KAO-WAY TU
IPC分类号： H01L21/8234
CPC分类号： H01L29/7813 , H01L27/0629 , H01L29/0619 , H01L29/407 , H01L29/41766 , H01L29/66143 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/872 , H01L29/8725
摘要： A fabrication method of integrating a power transistor and a schottky diode on a monolithic substrate is provided. Firstly, a substrate of a first conductive type is provided. Then, at least a polysilicon gate and a second polysilicon structure are formed on the substrate. At least a portion of the second polysilicon structure is located on an upper surface of the substrate. Thereafter, a body of a second conductive type and a source region of the first conductive type are formed between the polysilicon gate and the second polysilicon structure. Then, an interlayer dielectric film is formed on the polysilicon gate to define a source contact window, but the second polysilicon structure is still exposed. Afterward, a portion of the second polysilicon structure is removed to form a schottky contact window to expose the substrate.
摘要翻译：提供了将功率晶体管和肖特基二极管集成在单片基板上的制造方法。首先，提供第一导电类型的衬底。然后，在基板上形成至少多晶硅栅极和第二多晶硅结构。第二多晶硅结构的至少一部分位于衬底的上表面上。此后，在多晶硅栅极和第二多晶硅结构之间形成第二导电类型的主体和第一导电类型的源极区域。然后，在多晶硅栅极上形成层间电介质膜以限定源极接触窗口，但第二多晶硅结构仍然暴露。之后，去除第二多晶硅结构的一部分以形成肖特基接触窗以暴露衬底。

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