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1. 发明申请

US20090085105A1 TRENCH MOSFET AND METHOD OF MANUFACTURE UTILIZING TWO MASKS 失效
标题翻译： TRENCH MOSFET和使用两个掩模的制造方法
公开(公告)号：US20090085105A1
公开(公告)日：2009-04-02
申请号：US11866365
申请日：2007-10-02
申请人： Shih Tzung Su , Jun Zeng , Poi Sun , Kao Way Tu , Tai Chiang Chen , Long Lv , Xin Wang
发明人： Shih Tzung Su , Jun Zeng , Poi Sun , Kao Way Tu , Tai Chiang Chen , Long Lv , Xin Wang
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L29/0661 , H01L29/407 , H01L29/41766 , H01L29/4236 , H01L29/42372 , H01L29/4238 , H01L29/456 , H01L29/4925 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7811
摘要： A method for manufacturing a trench MOSFET semiconductor device comprises: providing a heavily doped N+ silicon substrate; forming an N type epitaxial layer; forming a thick SiO2 layer; creating P body and source area formations by ion implantation without any masks; utilizing a first mask to define openings for a trench gate and a termination; thermally growing a gate oxide layer followed by formation of a thick poly-Silicon refill layer without a mask to define a gate bus area; forming sidewall spacers; forming P+ areas; removing the sidewall spacers; depositing tungsten to fill contacts and vias; depositing a first thin barrier metal layer; depositing a first thick metal layer; utilizing a second metal mask to open a gate bus area; forming second sidewall spacers; depositing a second thin barrier metal layer; depositing a second thick metal layer; and planarizing at least the second thick metal layer and the second thin metal layer to isolate the source metal portions from gate metal portions, whereby the trench MOSFET semiconductor device is manufactured utilizing only first and second masks.
摘要翻译：一种用于制造沟槽MOSFET半导体器件的方法包括：提供重掺杂的N +硅衬底; 形成N型外延层; 形成厚的SiO 2层; 通过离子注入创建P体和源区形成，而不需要任何掩模; 利用第一掩模来限定沟槽栅极和终端的开口; 热生长栅极氧化层，随后形成厚度不含掩模的多晶硅替代层，以限定栅极总线面积; 形成侧壁间隔物; 形成P +区域; 去除侧壁间隔物; 沉积钨以填充触点和通孔; 沉积第一薄的阻挡金属层; 沉积第一厚金属层; 利用第二金属掩模打开闸总线区域; 形成第二侧壁间隔物; 沉积第二薄的阻挡金属层; 沉积第二厚金属层; 并且至少平面化第二厚金属层和第二薄金属层以将源极金属部分与栅极金属部分隔离，由此仅利用第一和第二掩模制造沟槽MOSFET半导体器件。

2. 发明申请

US20090085099A1 TRENCH MOSFET AND METHOD OF MANUFACTURE UTILIZING THREE MASKS 审中-公开
标题翻译： TRENCH MOSFET及其制造方法利用三个掩模
公开(公告)号：US20090085099A1
公开(公告)日：2009-04-02
申请号：US11866353
申请日：2007-10-02
申请人： Shih Tzung Su , Jun Zeng , Poi Sun , Kao Way Tu , Tai Chiang Chen , Long Lv , Xin Wang
发明人： Shih Tzung Su , Jun Zeng , Poi Sun , Kao Way Tu , Tai Chiang Chen , Long Lv , Xin Wang
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7811 , H01L29/0661 , H01L29/407 , H01L29/41766 , H01L29/4236 , H01L29/456 , H01L29/4925 , H01L29/66727 , H01L29/66734 , H01L29/7813
摘要： In accordance with the invention a vertical power trench MOSFET semiconductor device comprises P+ body and N+ source diffusions shorted together to prevent second breakdown caused by a parasitic bipolar transistor. The device is manufactured in accordance with a process comprising the steps of: providing a heavily doped N+ silicon substrate; utilizing a first, trench, mask to define a plurality of openings comprising a trench gate and a termination; creating P+ body and N+ source area formations by ion implantation without any masks; utilizing a second, contact, mask to define a gate bus area; and utilizing a third metal mask to separate source metal and gate bus metal and remove metal from a portion of the termination, whereby only three masks are utilized to form the semiconductor device.
摘要翻译：根据本发明，垂直功率沟槽MOSFET半导体器件包括P +体和N +源极扩散在一起短路以防止由寄生双极晶体管引起的第二次击穿。该装置根据包括以下步骤的方法制造：提供重掺杂的N +硅衬底; 利用第一沟槽掩模来限定包括沟槽栅极和终端的多个开口; 通过没有任何掩模的离子注入产生P +体和N +源区形成; 利用第二接触掩模来定义一个门总线区域; 并且利用第三金属掩模来分离源极金属和栅极总线金属并从终端的一部分去除金属，由此仅使用三个掩模来形成半导体器件。

3. 发明授权

US07799642B2 Trench MOSFET and method of manufacture utilizing two masks 失效
标题翻译：沟槽MOSFET和利用两个掩模的制造方法
公开(公告)号：US07799642B2
公开(公告)日：2010-09-21
申请号：US11866365
申请日：2007-10-02
申请人： Shih Tzung Su , Jun Zeng , Poi Sun , Kao Way Tu , Tai Chiang Chen , Long Lv , Xin Wang
发明人： Shih Tzung Su , Jun Zeng , Poi Sun , Kao Way Tu , Tai Chiang Chen , Long Lv , Xin Wang
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/0661 , H01L29/407 , H01L29/41766 , H01L29/4236 , H01L29/42372 , H01L29/4238 , H01L29/456 , H01L29/4925 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7811
摘要： A method for manufacturing a trench MOSFET semiconductor device comprises: providing a heavily doped N+ silicon substrate; forming an N type epitaxial layer; forming a thick SiO2 layer; creating P body and source area formations by ion implantation without any masks; utilizing a first mask to define openings for a trench gate and a termination; thermally growing a gate oxide layer followed by formation of a thick poly-Silicon refill layer without a mask to define a gate bus area; forming sidewall spacers; forming P+ areas; removing the sidewall spacers; depositing tungsten to fill contacts and vias; depositing a first thin barrier metal layer; depositing a first thick metal layer; utilizing a second metal mask to open a gate bus area; forming second sidewall spacers; depositing a second thin barrier metal layer; depositing a second thick metal layer; and planarizing at least the second thick metal layer and the second thin metal layer to isolate the source metal portions from gate metal portions, whereby the trench MOSFET semiconductor device is manufactured utilizing only first and second masks.
摘要翻译：一种用于制造沟槽MOSFET半导体器件的方法包括：提供重掺杂的N +硅衬底; 形成N型外延层; 形成厚的SiO 2层; 通过离子注入创建P体和源区形成，而不需要任何掩模; 利用第一掩模来限定沟槽栅极和终端的开口; 热生长栅极氧化层，随后形成厚度不含掩模的多晶硅替代层，以限定栅极总线面积; 形成侧壁间隔物; 形成P +区域; 去除侧壁间隔物; 沉积钨以填充触点和通孔; 沉积第一薄的阻挡金属层; 沉积第一厚金属层; 利用第二金属掩模打开闸总线区域; 形成第二侧壁间隔物; 沉积第二薄的阻挡金属层; 沉积第二厚金属层; 并且至少平面化第二厚金属层和第二薄金属层以将源极金属部分与栅极金属部分隔离，由此仅利用第一和第二掩模制造沟槽MOSFET半导体器件。

4. 发明授权

US07687352B2 Trench MOSFET and method of manufacture utilizing four masks 失效
标题翻译：沟槽MOSFET和利用四个掩模的制造方法
公开(公告)号：US07687352B2
公开(公告)日：2010-03-30
申请号：US11866350
申请日：2007-10-02
申请人： Shih Tzung Su , Jun Zeng , Poi Sun , Kao Way Tu , Tai Chiang Chen , Long Lv , Xin Wang
发明人： Shih Tzung Su , Jun Zeng , Poi Sun , Kao Way Tu , Tai Chiang Chen , Long Lv , Xin Wang
IPC分类号： H01L21/336
CPC分类号： H01L29/7811 , H01L29/0661 , H01L29/407 , H01L29/4236 , H01L29/456 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7813
摘要： In accordance with the invention, a trench MOSFET semiconductor device is manufactured in accordance with a process comprising the steps of: providing a heavily doped N+ silicon substrate; utilizing a first mask to define openings for the trench gate and termination; utilizing a second mask as a source mask with openings determining the size and shape of a diffused source junction depth; utilizing a third mask as a contact mask to define contact hole openings; and utilizing a fourth mask as a metal mask, whereby only the first, second, third and fourth masks are utilized in the manufacture of the trench MOSFET semiconductor device.
摘要翻译：根据本发明，根据包括以下步骤的方法制造沟槽MOSFET半导体器件：提供重掺杂的N +硅衬底; 利用第一掩模来限定沟槽栅极和终端的开口; 利用第二掩模作为源掩模，其具有确定扩散源结深度的大小和形状的开口; 利用第三掩模作为接触掩模来限定接触孔开口; 并且利用第四掩模作为金属掩模，由此在制造沟槽MOSFET半导体器件中仅利用第一，第二，第三和第四掩模。

5. 发明申请

US20090085074A1 TRENCH MOSFET AND METHOD OF MANUFACTURE UTILIZING FOUR MASKS 失效
标题翻译： TRENCH MOSFET和使用四个掩模的制造方法
公开(公告)号：US20090085074A1
公开(公告)日：2009-04-02
申请号：US11866350
申请日：2007-10-02
申请人： Shih Tzung Su , Jun Zeng , Poi Sun , Kao Way Tu , Tai Chiang Chen , Long Lv , Xin Wang
发明人： Shih Tzung Su , Jun Zeng , Poi Sun , Kao Way Tu , Tai Chiang Chen , Long Lv , Xin Wang
IPC分类号： H01L29/00 , H01L21/425
CPC分类号： H01L29/7811 , H01L29/0661 , H01L29/407 , H01L29/4236 , H01L29/456 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7813
摘要： In accordance with the invention, a trench MOSFET semiconductor device is manufactured in accordance with a process comprising the steps of: providing a heavily doped N+ silicon substrate; utilizing a first mask to define openings for the trench gate and termination; utilizing a second mask as a source mask with openings determining the size and shape of a diffused source junction depth; utilizing a third mask as a contact mask to define contact hole openings; and utilizing a fourth mask as a metal mask, whereby only the first, second, third and fourth masks are utilized in the manufacture of the trench MOSFET semiconductor device.
摘要翻译：根据本发明，根据包括以下步骤的方法制造沟槽MOSFET半导体器件：提供重掺杂的N +硅衬底; 利用第一掩模来限定沟槽栅极和终端的开口; 利用第二掩模作为源掩模，其具有确定扩散源结深度的尺寸和形状的开口; 利用第三掩模作为接触掩模来限定接触孔开口; 并且利用第四掩模作为金属掩模，由此在制造沟槽MOSFET半导体器件中仅利用第一，第二，第三和第四掩模。

6. 发明授权

US07759238B2 Method for fabricating semiconductor device capable of adjusting the thickness of gate oxide layer 有权
标题翻译：制造半导体器件的方法，该半导体器件能够调节栅极氧化物层的厚度
公开(公告)号：US07759238B2
公开(公告)日：2010-07-20
申请号：US12187370
申请日：2008-08-06
申请人： Tai Chiang Chen , Xin Wang
发明人： Tai Chiang Chen , Xin Wang
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L21/31662 , H01L21/02233 , H01L21/28035 , H01L21/28167 , H01L21/31658 , H01L29/51 , Y10S438/981
摘要： The present invention provides a method for fabricating semiconductor device, which is capable of adjusting a gate oxide layer thickness, including: providing a semiconductor substrate; growing a first oxide layer on a surface of the semiconductor substrate; patterning the first oxide layer to expose the first oxide layer corresponding to a gate to be formed; removing the exposed first oxide layer; immersing the substrate into deionized water to grow a second oxide layer; forming a polysilicon layer on the surfaces of the first oxide layer and the second oxide layer; and etching the polysilicon layer to form a gate. The method for fabricating semiconductor device according to the present invention, which is capable of adjusting the thickness of gate oxide layer, can control the thickness of gate oxide layer precisely to satisfy the requirement for different threshold voltages.
摘要翻译：本发明提供一种能够调整栅极氧化层厚度的半导体器件的制造方法，包括：提供半导体衬底; 在半导体衬底的表面上生长第一氧化物层; 图案化第一氧化物层以暴露与要形成的栅极对应的第一氧化物层; 去除暴露的第一氧化物层; 将基底浸入去离子水中以生长第二氧化物层; 在所述第一氧化物层和所述第二氧化物层的表面上形成多晶硅层; 并蚀刻多晶硅层以形成栅极。根据本发明的半导体器件的制造方法，其能够调整栅氧化层的厚度，能够精确地控制栅氧化层的厚度，以满足不同阈值电压的要求。

7. 发明申请

US20090042379A1 Method for Fabricating Semiconductor Device Capable of Adjusting the Thickness of Gate Oxide Layer 有权
标题翻译：制造能够调节栅氧化层厚度的半导体器件的方法
公开(公告)号：US20090042379A1
公开(公告)日：2009-02-12
申请号：US12187370
申请日：2008-08-06
申请人： Tai Chiang Chen , Xin Wang
发明人： Tai Chiang Chen , Xin Wang
IPC分类号： H01L21/3205 , H01L21/469
CPC分类号： H01L21/31662 , H01L21/02233 , H01L21/28035 , H01L21/28167 , H01L21/31658 , H01L29/51 , Y10S438/981
摘要： The present invention provides a method for fabricating semiconductor device, which is capable of adjusting a gate oxide layer thickness, including: providing a semiconductor substrate; growing a first oxide layer on a surface of the semiconductor substrate; patterning the first oxide layer to expose the first oxide layer corresponding to a gate to be formed; removing the exposed first oxide layer; immersing the substrate into deionized water to grow a second oxide layer; forming a polysilicon layer on the surfaces of the first oxide layer and the second oxide layer; and etching the polysilicon layer to form a gate. The method for fabricating semiconductor device according to the present invention, which is capable of adjusting the thickness of gate oxide layer, can control the thickness of gate oxide layer precisely to satisfy the requirement for different threshold voltages.
摘要翻译：本发明提供一种能够调整栅极氧化层厚度的半导体器件的制造方法，包括：提供半导体衬底; 在半导体衬底的表面上生长第一氧化物层; 图案化第一氧化物层以暴露与要形成的栅极对应的第一氧化物层; 去除暴露的第一氧化物层; 将基底浸入去离子水中以生长第二氧化物层; 在所述第一氧化物层和所述第二氧化物层的表面上形成多晶硅层; 并蚀刻多晶硅层以形成栅极。根据本发明的半导体器件的制造方法，其能够调整栅氧化层的厚度，能够精确地控制栅氧化层的厚度，以满足不同阈值电压的要求。

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