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1. 发明授权

US08692305B2 Semiconductor devices and structures including at least partially formed container capacitors 有权
标题翻译：包括至少部分形成的容器电容器的半导体器件和结构
公开(公告)号：US08692305B2
公开(公告)日：2014-04-08
申请号：US13286702
申请日：2011-11-01
申请人： Brett Busch , Kevin R. Shea , Thomas A. Figura
发明人： Brett Busch , Kevin R. Shea , Thomas A. Figura
IPC分类号： H01L27/108 , H01L29/94
CPC分类号： H01L27/10852 , H01L28/90
摘要： Semiconductor device structures include an at least partially formed container capacitor having a generally cylindrical first conductive member with at least one inner sidewall surface, a lattice material at least partially laterally surrounding an upper end portion of the first conductive member, an anchor material, and at least one aperture extending through the lattice material between the at least partially formed container capacitor and an adjacent at least partially formed container capacitor. Other structures include an at least partially formed container capacitor, a lattice material, and an anchor material disposed over a surface of the lattice material and at least a portion of an end surface of the first conductive member and forming a chemical barrier over at least a portion of an interface between the lattice material and the upper end portion of the first conductive member.
摘要翻译：半导体器件结构包括至少部分形成的容器电容器，其具有大致圆柱形的第一导电构件，其具有至少一个内侧壁表面，格栅材料至少部分横向围绕第一导电构件的上端部分，锚固材料和在所述至少部分形成的容器电容器和相邻的至少部分形成的容器电容器之间延伸穿过所述晶格材料的至少一个孔。其他结构包括至少部分形成的容器电容器，格子材料和布置在晶格材料的表面上的锚定材料和第一导电构件的端表面的至少一部分，并且在至少一个晶格材料和第一导电构件的上端部分之间的界面的一部分。

2. 发明授权

US08058126B2 Semiconductor devices and structures including at least partially formed container capacitors and methods of forming the same 有权
标题翻译：包括至少部分形成的容器电容器的半导体器件和结构体及其形成方法
公开(公告)号：US08058126B2
公开(公告)日：2011-11-15
申请号：US12365519
申请日：2009-02-04
申请人： Brett Busch , Kevin R. Shea , Thomas A. Figura
发明人： Brett Busch , Kevin R. Shea , Thomas A. Figura
IPC分类号： H01L21/8242
CPC分类号： H01L27/10852 , H01L28/90
摘要： Methods of forming semiconductor devices that include one or more container capacitors include anchoring an end of a conductive member to a surrounding lattice material using an anchor material, which may be a dielectric. The anchor material may extend over at least a portion of an end surface of the conductive member, at least a portion of the lattice material, and an interface between the conductive member and the lattice material. In some embodiments, the anchor material may be formed without significantly covering an inner sidewall surface of the conductive member. Furthermore, in some embodiments, a barrier material may be provided over at least a portion of the anchor material and over at least a portion of an inner sidewall surface of the conductive member. Novel semiconductor devices and structures are fabricated using such methods.
摘要翻译：形成包括一个或多个容器电容器的半导体器件的方法包括使用锚定材料（其可以是电介质）将导电构件的端部锚定到周围的栅格材料。锚固材料可以在导电构件的端表面的至少一部分，晶格材料的至少一部分以及导电构件和晶格材料之间的界面上延伸。在一些实施例中，可以形成锚固材料而不显着地覆盖导电构件的内侧壁表面。此外，在一些实施例中，阻挡材料可以设置在锚定材料的至少一部分上并且在导电构件的内侧壁表面的至少一部分上方。使用这种方法制造新的半导体器件和结构。

3. 发明申请

US20110183507A1 Peripheral Gate Stacks and Recessed Array Gates 有权
标题翻译：外围门堆叠和嵌入式阵列门
公开(公告)号：US20110183507A1
公开(公告)日：2011-07-28
申请号：US13083782
申请日：2011-04-11
申请人： Thomas A. Figura , Gordon A. Haller
发明人： Thomas A. Figura , Gordon A. Haller
IPC分类号： H01L21/28
CPC分类号： H01L21/823456 , H01L21/82345 , H01L27/10852 , H01L27/10876 , H01L27/10897
摘要： Methods are provided for simultaneously processing transistors in two different regions of an integrated circuit. Planar transistors are provided in a logic region while recessed access devices (RADs) are provided in an array region for a memory device. During gate stack patterning in the periphery, word lines are recessed within the trenches for the array RADs. Side wall spacer formation in the periphery simultaneously provides an insulating cap layer burying the word lines within the trenches of the array.
摘要翻译：提供了用于在集成电路的两个不同区域中同时处理晶体管的方法。在逻辑区域中提供平面晶体管，而在用于存储器件的阵列区域中提供凹入式存取设备（RAD）。在周边的栅堆栈图案化期间，字线凹入用于阵列RAD的沟槽内。在外围的侧壁间隔物形成同时提供了一个绝缘盖层，掩埋了阵列的沟槽内的字线。

4. 发明授权

US07977236B2 Method of forming a transistor gate of a recessed access device, method of forming a recessed transistor gate and a non-recessed transistor gate, and method of fabricating an integrated circuit 有权
标题翻译：形成凹陷式存取器件的晶体管栅极的方法，形成凹陷晶体管栅极和非凹槽晶体管栅极的方法以及制造集成电路的方法
公开(公告)号：US07977236B2
公开(公告)日：2011-07-12
申请号：US12476364
申请日：2009-06-02
申请人： Hasan Nejad , Thomas A. Figura , Gordon A. Haller , Ravi Iyer , John Mark Meldrim , Justin Harnish
发明人： Hasan Nejad , Thomas A. Figura , Gordon A. Haller , Ravi Iyer , John Mark Meldrim , Justin Harnish
IPC分类号： H01L21/4763
CPC分类号： H01L21/823835 , H01L21/28097 , H01L21/823418 , H01L21/823443 , H01L21/823814 , H01L27/10852 , H01L27/10876 , H01L27/10897 , H01L29/4975 , H01L29/66621 , H01L2924/0002 , H01L2924/00
摘要： Methods and structures are provided for full silicidation of recessed silicon. Silicon is provided within a trench. A mixture of metals is provided over the silicon in which one of the metals diffuses more readily in silicon than silicon does in the metal, and another of the metals diffuses less readily in silicon than silicon does in the metal. An exemplary mixture includes 80% nickel and 20% cobalt. The silicon within the trench is allowed to fully silicide without void formation, despite a relatively high aspect ratio for the trench. Among other devices, recessed access devices (RADs) can be formed by the method for memory arrays.
摘要翻译：为嵌入硅完全硅化提供了方法和结构。在沟槽内提供硅。在硅上提供了一种金属混合物，其中一种金属在硅中比硅中更容易扩散到金属中，而另一种金属在硅中比在金属中的硅更容易扩散。示例性的混合物包括80％的镍和20％的钴。尽管沟槽的纵横比相对较高，但沟槽内的硅可以完全无硅化物形成。在其他设备中，可以通过用于存储器阵列的方法形成凹陷接入设备（RAD）。

5. 发明授权

US07939409B2 Peripheral gate stacks and recessed array gates 有权
标题翻译：外围栅极堆叠和凹陷阵列栅极
公开(公告)号：US07939409B2
公开(公告)日：2011-05-10
申请号：US12177296
申请日：2008-07-22
申请人： Thomas A. Figura , Gordon A. Haller
发明人： Thomas A. Figura , Gordon A. Haller
IPC分类号： H01L21/336
CPC分类号： H01L21/823456 , H01L21/82345 , H01L27/10852 , H01L27/10876 , H01L27/10897
摘要： Methods are provided for simultaneously processing transistors in two different regions of an integrated circuit. Planar transistors are provided in a logic region while recessed access devices (RADs) are provided in an array region for a memory device. During gate stack patterning in the periphery, word lines are recessed within the trenches for the array RADs. Side wall spacer formation in the periphery simultaneously provides an insulating cap layer burying the word lines within the trenches of the array.
摘要翻译：提供了用于在集成电路的两个不同区域中同时处理晶体管的方法。在逻辑区域中提供平面晶体管，而在用于存储器件的阵列区域中提供凹入式存取设备（RAD）。在周边的栅堆栈图案化期间，字线凹入用于阵列RAD的沟槽内。在外围的侧壁间隔物形成同时提供了一个绝缘盖层，掩埋了阵列的沟槽内的字线。

6. 发明授权

US07709343B2 Use of a plasma source to form a layer during the formation of a semiconductor device 失效
标题翻译：在形成半导体器件期间使用等离子体源形成层
公开(公告)号：US07709343B2
公开(公告)日：2010-05-04
申请号：US12235351
申请日：2008-09-22
申请人： Thomas A. Figura , Kevin G. Donohoe , Thomas Dunbar
发明人： Thomas A. Figura , Kevin G. Donohoe , Thomas Dunbar
IPC分类号： H01L21/20 , H01L21/302
CPC分类号： H01L21/312 , H01L21/02129 , H01L21/32139 , H01L21/76865 , H01L28/40 , H01L28/60
摘要： A method used to form a semiconductor device having a capacitor comprises placing a semiconductor wafer assembly into a chamber of a plasma source, the wafer assembly comprising a layer of insulation having at least one contact therein and a surface, and further comprising a conductive layer over the surface and in the contact. Next, in the chamber, a layer of etch resistant material is formed within the contact over the conductive layer, the etch resistant material not forming over the surface.
摘要翻译：用于形成具有电容器的半导体器件的方法包括将半导体晶片组件放置在等离子体源的腔室中，所述晶片组件包括其中具有至少一个触点的绝缘层和表面，并且还包括导电层表面和接触。接下来，在腔室中，在导电层上的接触件内形成一层耐蚀刻材料，该耐蚀刻材料不会在该表面上形成。

7. 发明授权

US07683413B2 Double sided container capacitor for a semiconductor device 有权
标题翻译：用于半导体器件的双面容器电容器
公开(公告)号：US07683413B2
公开(公告)日：2010-03-23
申请号：US11517045
申请日：2006-09-07
申请人： Thomas M. Graettinger , Marsela Pontoh , Thomas A. Figura
发明人： Thomas M. Graettinger , Marsela Pontoh , Thomas A. Figura
IPC分类号： H01L27/108
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/91
摘要： A method for forming a double sided container capacitor comprises forming a first capacitor top plate layer within a recess in a dielectric layer, then forming a first cell dielectric on the first top plate layer. Next, first and second bottom plate layers are formed on the first cell dielectric layer, and a second cell dielectric layer is formed on the second bottom plate layers. Finally, a second top plate layer is formed on the second cell dielectric layer, and the first and second top plate layers are electrically connected using a conductive plug or conductive spacer. An inventive structure formed using the inventive method is also described.
摘要翻译：一种用于形成双面容器电容器的方法包括在电介质层的凹槽内形成第一电容器顶板层，然后在第一顶板层上形成第一单元电介质。接下来，在第一单元电介质层上形成第一和第二底板层，在第二底板层上形成第二单元电介质层。最后，在第二单元电介质层上形成第二顶板层，并且使用导电插塞或导电间隔件将第一和第二顶板层电连接。还描述了使用本发明方法形成的本发明的结构。

8. 发明授权

US07429535B2 Use of a plasma source to form a layer during the formation of a semiconductor device 失效
标题翻译：在形成半导体器件期间使用等离子体源形成层
公开(公告)号：US07429535B2
公开(公告)日：2008-09-30
申请号：US11651158
申请日：2007-01-09
申请人： Thomas A. Figura , Kevin G. Donohoe , Thomas Dunbar
发明人： Thomas A. Figura , Kevin G. Donohoe , Thomas Dunbar
IPC分类号： H01L21/302 , H01L21/311
CPC分类号： H01L21/312 , H01L21/02129 , H01L21/32139 , H01L21/76865 , H01L28/40 , H01L28/60
摘要： A method used to form a semiconductor device having a capacitor comprises placing a semiconductor wafer assembly into a chamber of a plasma source, the wafer assembly comprising a layer of insulation having at least one contact therein and a surface, and further comprising a conductive layer over the surface and in the contact. Next, in the chamber, a layer of etch resistant material is formed within the contact over the conductive layer, the etch resistant material not forming over the surface.
摘要翻译：用于形成具有电容器的半导体器件的方法包括将半导体晶片组件放置在等离子体源的腔室中，所述晶片组件包括其中具有至少一个触点的绝缘层和表面，并且还包括导电层表面和接触。接下来，在腔室中，在导电层上的接触件内形成一层耐蚀刻材料，该耐蚀刻材料不会在该表面上形成。

9. 发明授权

US07105403B2 Double sided container capacitor for a semiconductor device and method for forming same 有权
标题翻译：用于半导体器件的双面容器电容器及其形成方法
公开(公告)号：US07105403B2
公开(公告)日：2006-09-12
申请号：US10628994
申请日：2003-07-28
申请人： Thomas M. Graettinger , Marsela Pontoh , Thomas A. Figura
发明人： Thomas M. Graettinger , Marsela Pontoh , Thomas A. Figura
IPC分类号： H01L21/8242
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/91
摘要： A method for forming a double sided container capacitor comprises forming a first capacitor top plate layer within a recess in a dielectric layer, then forming a first cell dielectric on the first top plate layer. Next, first and second bottom plate layers are formed on the first cell dielectric layer, and a second cell dielectric layer is formed on the second bottom plate layers. Finally, a second top plate layer is formed on the second cell dielectric layer, and the first and second top plate layers are electrically connected using a conductive plug or conductive spacer. An inventive structure formed using the inventive method is also described.
摘要翻译：一种用于形成双面容器电容器的方法包括在电介质层的凹槽内形成第一电容器顶板层，然后在第一顶板层上形成第一单元电介质。接下来，在第一单元电介质层上形成第一和第二底板层，在第二底板层上形成第二单元电介质层。最后，在第二单元电介质层上形成第二顶板层，并且使用导电插塞或导电间隔件将第一和第二顶板层电连接。还描述了使用本发明方法形成的本发明的结构。

10. 发明授权

US06838714B2 Low leakage diodes, including photodiodes 有权
标题翻译：低漏电二极管，包括光电二极管
公开(公告)号：US06838714B2
公开(公告)日：2005-01-04
申请号：US09780390
申请日：2001-02-12
申请人： Howard E. Rhodes , Werner Juengling , Thomas A. Figura , Steven D. Cummings
发明人： Howard E. Rhodes , Werner Juengling , Thomas A. Figura , Steven D. Cummings
IPC分类号： H01L27/146 , H01L27/148 , H01L29/861 , H01L31/062
CPC分类号： H01L27/14687 , H01L27/14609 , H01L27/14806 , H01L29/8611
摘要： A photodiode for use in an imager having an improved charge leakage. The photodiode has a doped region that is spaced away from the field isolation to minimize charge leakage. A second embodiment of invention provides a second implant to improve charge leakage to the substrate. The photodiodes according to the invention provide improve charge leakage, improved reactions to dark current and an improved signal to noise ratio. Also disclosed are processes for forming the photodiode.
摘要翻译：用于具有改善的电荷泄漏的成像器中的光电二极管。光电二极管具有与场隔离间隔开的掺杂区域，以最小化电荷泄漏。本发明的第二实施例提供了一种第二种植入物，用于改善对衬底的电荷泄漏。根据本发明的光电二极管提供改善电荷泄漏，改善对暗电流的反应和改善的信噪比。还公开了用于形成光电二极管的工艺。

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