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1. 发明授权

US08735302B2 High productivity combinatorial oxide terracing and PVD/ALD metal deposition combined with lithography for gate work function extraction 有权
标题翻译：高生产率组合氧化物梯度和PVD / ALD金属沉积结合光刻用于栅极功能提取
公开(公告)号：US08735302B2
公开(公告)日：2014-05-27
申请号：US13480023
申请日：2012-05-24
申请人： Amol Joshi , John Foster , Zhendong Hong , Olov Karlsson , Bei Li , Usha Raghuram
发明人： Amol Joshi , John Foster , Zhendong Hong , Olov Karlsson , Bei Li , Usha Raghuram
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L29/66181 , G01N27/002 , H01L22/14 , H01L22/20
摘要： Metal gate high-k capacitor structures with lithography patterning are used to extract gate work function using a combinatorial workflow. Oxide terracing, together with high productivity combinatorial process flow for metal deposition can provide optimum high-k gate dielectric and metal gate solutions for high performance logic transistors. The high productivity combinatorial technique can provide an evaluation of effective work function for given high-k dielectric metal gate stacks for PMOS and NMOS transistors, which is critical in identifying and selecting the right materials.
摘要翻译：使用光刻图案化的金属栅极高k电容器结构使用组合工作流程提取门功函数。氧化物梯田，以及用于金属沉积的高生产率组合工艺流程可为高性能逻辑晶体管提供最佳的高k栅介质和金属栅极解决方案。高生产率组合技术可以为PMOS和NMOS晶体管的给定高k介质金属栅极叠层提供有效的工作函数的评估，这对于识别和选择正确的材料至关重要。

2. 发明授权

US08854067B2 Circular transmission line methods compatible with combinatorial processing of semiconductors 有权
标题翻译：圆形传输线方法兼容半导体的组合处理
公开(公告)号：US08854067B2
公开(公告)日：2014-10-07
申请号：US13594292
申请日：2012-08-24
申请人： Amol Joshi , Charlene Chen , John Foster , Zhendong Hong , Olov Karlsson , Bei Li , Dipankar Pramanik , Usha Raghuram , Mark Victor Raymond , Jingang Su , Bin Yang
发明人： Amol Joshi , Charlene Chen , John Foster , Zhendong Hong , Olov Karlsson , Bei Li , Dipankar Pramanik , Usha Raghuram , Mark Victor Raymond , Jingang Su , Bin Yang
IPC分类号： G01R27/08 , G01R31/28
CPC分类号： G01R27/08 , G01R31/2831 , H01L22/14 , H01L22/20
摘要： Methods and structures are described for determining contact resistivities and Schottky barrier heights for conductors deposited on semiconductor wafers that can be combined with combinatorial processing, allowing thereby numerous processing conditions and materials to be tested concurrently. Methods for using multi-ring as well as single-ring CTLM structures to cancel parasitic resistance are also described, as well as structures and processes for inline monitoring of properties.
摘要翻译：描述了用于确定沉积在可与组合处理组合的半导体晶片上的导体的接触电阻率和肖特基势垒高度的方法和结构，从而允许同时测试许多处理条件和材料。还描述了使用多环以及单环CTLM结构来消除寄生电阻的方法，以及用于在线监测性质的结构和方法。

3. 发明申请

US20130316472A1 HIGH PRODUCTIVITY COMBINATORIAL OXIDE TERRACING AND PVD/ALD METAL DEPOSITION COMBINED WITH LITHOGRAPHY FOR GATE WORK FUNCTION EXTRACTION 有权
标题翻译：高生产率组合氧化物触媒和PVD / ALD金属沉积与门式工作功能提取相结合
公开(公告)号：US20130316472A1
公开(公告)日：2013-11-28
申请号：US13480023
申请日：2012-05-24
申请人： Amol Joshi , John Foster , Zhendong Hong , Olov Karlsson , Bei Li , Usha Raghuram
发明人： Amol Joshi , John Foster , Zhendong Hong , Olov Karlsson , Bei Li , Usha Raghuram
IPC分类号： H01L21/66
CPC分类号： H01L29/66181 , G01N27/002 , H01L22/14 , H01L22/20
摘要： Metal gate high-k capacitor structures with lithography patterning are used to extract gate work function using a combinatorial workflow. Oxide terracing, together with high productivity combinatorial process flow for metal deposition can provide optimum high-k gate dielectric and metal gate solutions for high performance logic transistors. The high productivity combinatorial technique can provide an evaluation of effective work function for given high-k dielectric metal gate stacks for PMOS and NMOS transistors, which is critical in identifying and selecting the right materials.
摘要翻译：使用光刻图案化的金属栅极高k电容器结构使用组合工作流程提取门功函数。氧化物梯田，以及用于金属沉积的高生产率组合工艺流程可为高性能逻辑晶体管提供最佳的高k栅介质和金属栅极解决方案。高生产率组合技术可以为PMOS和NMOS晶体管的给定高k介质金属栅极叠层提供有效的工作函数的评估，这对于识别和选择正确的材料至关重要。

4. 发明授权

US08920618B2 Combinatorial processing using high deposition rate sputtering 有权
标题翻译：使用高沉积速率溅射的组合加工
公开(公告)号：US08920618B2
公开(公告)日：2014-12-30
申请号：US13339648
申请日：2011-12-29
申请人： Hong Sheng Yang , Zhendong Hong , Chi-I Lang
发明人： Hong Sheng Yang , Zhendong Hong , Chi-I Lang
IPC分类号： C23C14/54
CPC分类号： C23C14/044 , C23C14/3464
摘要： Apparatuses and methods for high-deposition-rate sputtering for depositing layers onto a substrate are disclosed. The apparatuses generally comprise a process chamber; one or more sputtering sources disposed within the process chamber, wherein each sputtering source comprises a sputtering target; a substrate support disposed within the process chamber; a shield positioned between the sputtering sources and the substrate, the shield comprising an aperture positioned under each sputtering source; and a transport system connected to the substrate support capable of positioning the substrate such that one of a plurality of site-isolated regions on the substrate can be exposed to sputtered material through the aperture positioned under each of the sputtering sources; wherein the spacing between the sputtering target and the substrate is less than 100 mm. The apparatus enables high deposition rate sputtering onto site-isolated regions on the substrate.
摘要翻译：公开了用于将沉积层沉积到基底上的高沉积速率溅射的装置和方法。设备通常包括处理室; 设置在处理室内的一个或多个溅射源，其中每个溅射源包括溅射靶; 设置在所述处理室内的衬底支撑件; 位于所述溅射源和所述衬底之间的屏蔽罩，所述屏蔽件包括位于每个溅射源下方的孔; 以及连接到所述基板支撑件的输送系统，其能够定位所述基板，使得所述基板上的多个位置隔离区域中的一个可以通过位于每个所述溅射源下方的所述孔暴露于溅射材料; 其中溅射靶和衬底之间的间距小于100mm。该装置能够在衬底上的位置分离区域上实现高沉积速率溅射。

5. 发明申请

US20140055152A1 CIRCULAR TRANSMISSION LINE METHODS COMPATIBLE WITH COMBINATORIAL PROCESSING OF SEMICONDUCTORS 有权
标题翻译：圆形传输线方法与半导体的组合处理兼容
公开(公告)号：US20140055152A1
公开(公告)日：2014-02-27
申请号：US13594292
申请日：2012-08-24
申请人： Amol Joshi , Charlene Chen , John Foster , Zhendong Hong , Olov Karlsson , Bei Li , Dipankar Pramanik , Usha Raghuram , Mark Victor Raymond , Jingang Su , Bin Yang
发明人： Amol Joshi , Charlene Chen , John Foster , Zhendong Hong , Olov Karlsson , Bei Li , Dipankar Pramanik , Usha Raghuram , Mark Victor Raymond , Jingang Su , Bin Yang
IPC分类号： G01R27/08
CPC分类号： G01R27/08 , G01R31/2831 , H01L22/14 , H01L22/20
摘要： Methods and structures are described for determining contact resistivities and Schottky barrier heights for conductors deposited on semiconductor wafers that can be combined with combinatorial processing, allowing thereby numerous processing conditions and materials to be tested concurrently. Methods for using multi-ring as well as single-ring CTLM structures to cancel parasitic resistance are also described, as well as structures and processes for inline monitoring of properties.
摘要翻译：描述了用于确定沉积在可与组合处理组合的半导体晶片上的导体的接触电阻率和肖特基势垒高度的方法和结构，从而允许同时测试许多处理条件和材料。还描述了使用多环以及单环CTLM结构来消除寄生电阻的方法，以及用于在线监测性质的结构和方法。

6. 发明申请

US20130167773A1 Combinatorial Processing Using High Deposition Rate Sputtering 有权
标题翻译：使用高沉积速率溅射的组合处理
公开(公告)号：US20130167773A1
公开(公告)日：2013-07-04
申请号：US13339648
申请日：2011-12-29
申请人： Hong Sheng Yang , Zhendong Hong , Chi-I Lang
发明人： Hong Sheng Yang , Zhendong Hong , Chi-I Lang
IPC分类号： C23C14/34
CPC分类号： C23C14/044 , C23C14/3464
摘要： Apparatuses and methods for high-deposition-rate sputtering for depositing layers onto a substrate are disclosed. The apparatuses generally comprise a process chamber; one or more sputtering sources disposed within the process chamber, wherein each sputtering source comprises a sputtering target; a substrate support disposed within the process chamber; a shield positioned between the sputtering sources and the substrate, the shield comprising an aperture positioned under each sputtering source; and a transport system connected to the substrate support capable of positioning the substrate such that one of a plurality of site-isolated regions on the substrate can be exposed to sputtered material through the aperture positioned under each of the sputtering sources; wherein the spacing between the sputtering target and the substrate is less than 100 mm. The apparatus enables high deposition rate sputtering onto site-isolated regions on the substrate.
摘要翻译：公开了用于将沉积层沉积到基底上的高沉积速率溅射的装置和方法。设备通常包括处理室; 设置在处理室内的一个或多个溅射源，其中每个溅射源包括溅射靶; 设置在所述处理室内的衬底支撑件; 位于所述溅射源和所述衬底之间的屏蔽罩，所述屏蔽件包括位于每个溅射源下方的孔; 以及连接到所述基板支撑件的输送系统，其能够定位所述基板，使得所述基板上的多个位置隔离区域中的一个可以通过位于每个所述溅射源下方的所述孔暴露于溅射材料; 其中溅射靶和衬底之间的间距小于100mm。该装置能够在衬底上的位置分离区域上实现高沉积速率溅射。

7. 发明申请

US20130130414A1 HIGH PRODUCTIVITY COMBINATORIAL WORKFLOW FOR PHOTORESIST STRIP APPLICATIONS 失效
标题翻译：高效生产力组合工作流程用于光栅条纹应用
公开(公告)号：US20130130414A1
公开(公告)日：2013-05-23
申请号：US13298524
申请日：2011-11-17
申请人： Bei Li , Sean Barstow , Anh Duong , Zhendong Hong , Ashley Lacey
发明人： Bei Li , Sean Barstow , Anh Duong , Zhendong Hong , Ashley Lacey
IPC分类号： H01L21/66
CPC分类号： H01L22/14 , G03F7/422 , H01L22/20
摘要： Electrical testing of metal oxide semiconductor (MOS) high-k capacitor structures is used to evaluate photoresist strip or cleaning chemicals using a combinatorial workflow. The electrical testing can be able to identify the damages on the high-k dielectrics, permitting a selection of photoresist strip chemicals to optimize the process conditions in the fabrication of semiconductor devices. The high productivity combinatorial technique can provide a compatibility evaluation of photoresist strip chemicals with high-k devices.
摘要翻译：金属氧化物半导体（MOS）高k电容器结构的电气测试用于使用组合工作流程来评估光致抗蚀剂条或清洁化学品。电气测试能够识别高k电介质上的损伤，允许选择光致抗蚀剂胶带化学品来优化半导体器件制造过程中的工艺条件。高生产率组合技术可以提供具有高k器件的光致抗蚀剂剥离化学品的兼容性评估。

8. 发明授权

US08882917B1 Substrate processing including correction for deposition location 有权
标题翻译：基板处理包括对沉积位置的校正
公开(公告)号：US08882917B1
公开(公告)日：2014-11-11
申请号：US12651172
申请日：2009-12-31
申请人： Jeremy Cheng , Ho Yin Owen Fong , Dan Wang , Zhendong Hong , Indranil De
发明人： Jeremy Cheng , Ho Yin Owen Fong , Dan Wang , Zhendong Hong , Indranil De
IPC分类号： C23C16/00 , C23C14/54
CPC分类号： G05B19/402 , B01J19/0046 , B01J2219/00326 , B01J2219/0043 , B01J2219/00443 , B01J2219/00536 , B01J2219/00612 , B01J2219/00689 , B01J2219/00693 , B01J2219/00695 , C23C14/042 , C23C14/505 , C23C14/54 , G05B2219/45031
摘要： Substrate processing including correction for deposition location is described, including a combinatorial processing chamber that incorporates the correction. The combinatorial processing chamber can be used to process multiple regions of a substrate using different processing parameters on different regions. For example, one region can have one material deposited on it and another region can have a different material deposited on it, although other combinations and variations are possible. The combinatorial processing chamber uses a rotating and revolving substrate pedestal to be able to deposit on all locations or positions on a substrate. The combinatorial processing chamber uses a correction factor that accounts for variations in alignment and/or configuration of the processing chamber so that the actual location of deposition of a region is approximately the same as a desired location of deposition.
摘要翻译：描述包括用于沉积位置的校正的衬底处理，包括结合了校正的组合处理室。组合处理室可用于在不同区域上使用不同的处理参数处理衬底的多个区域。例如，一个区域可以具有沉积在其上的一个材料，而另一个区域可以具有沉积在其上的不同材料，尽管其它组合和变化是可能的。组合处理室使用旋转和旋转的基板基座能够沉积在基板上的所有位置或位置上。组合处理室使用考虑处理室的对准和/或配置变化的校正因子，使得区域的实际沉积位置与期望的沉积位置大致相同。

9. 发明授权

US08846443B2 Atomic layer deposition of metal oxides for memory applications 有权
标题翻译：用于记忆应用的金属氧化物的原子层沉积
公开(公告)号：US08846443B2
公开(公告)日：2014-09-30
申请号：US13198837
申请日：2011-08-05
申请人： Zhendong Hong , Hieu Pham , Randall Higuchi , Vidyut Gopal , Imran Hashim , Tim Minvielle , Takeshi Yamaguchi
发明人： Zhendong Hong , Hieu Pham , Randall Higuchi , Vidyut Gopal , Imran Hashim , Tim Minvielle , Takeshi Yamaguchi
IPC分类号： H01L21/00 , H01L21/8222 , H01L45/00 , H01L27/24
CPC分类号： H01L45/146 , H01L27/2463 , H01L45/04 , H01L45/08 , H01L45/1233 , H01L45/1616
摘要： Embodiments of the invention generally relate to nonvolatile memory devices and methods for manufacturing such memory devices. The methods for forming improved memory devices, such as a ReRAM cells, provide optimized, atomic layer deposition (ALD) processes for forming a metal oxide film stack which contains at least one hard metal oxide film (e.g., metal is completely oxidized or substantially oxidized) and at least one soft metal oxide film (e.g., metal is less oxidized than hard metal oxide). The soft metal oxide film is less electrically resistive than the hard metal oxide film since the soft metal oxide film is less oxidized or more metallic than the hard metal oxide film. In one example, the hard metal oxide film is formed by an ALD process utilizing ozone as the oxidizing agent while the soft metal oxide film is formed by another ALD process utilizing water vapor as the oxidizing agent.
摘要翻译：本发明的实施例一般涉及用于制造这种存储器件的非易失性存储器件和方法。用于形成改进的存储器件（例如ReRAM单元）的方法提供优化的原子层沉积（ALD）工艺，用于形成金属氧化物膜堆叠，其包含至少一个硬金属氧化物膜（例如，金属被完全氧化或基本上被氧化）和至少一种软金属氧化物膜（例如，金属比硬金属氧化物氧化较少）。由于软金属氧化物膜比硬金属氧化物膜氧化得更少或更金属，所以软金属氧化物膜的电阻小于硬金属氧化物膜。在一个实例中，通过利用臭氧作为氧化剂的ALD工艺形成硬质金属氧化物膜，而通过利用水蒸汽作为氧化剂的另一ALD工艺形成软金属氧化物膜。

10. 发明授权

US08664014B2 High productivity combinatorial workflow for photoresist strip applications 失效
标题翻译：用于光刻胶剥离应用的高生产率组合工作流程
公开(公告)号：US08664014B2
公开(公告)日：2014-03-04
申请号：US13298524
申请日：2011-11-17
申请人： Bei Li , Sean Barstow , Anh Duong , Zhendong Hong , Ashley Lacey
发明人： Bei Li , Sean Barstow , Anh Duong , Zhendong Hong , Ashley Lacey
IPC分类号： G01R31/26 , H01L21/66
CPC分类号： H01L22/14 , G03F7/422 , H01L22/20
摘要： Electrical testing of metal oxide semiconductor (MOS) high-k capacitor structures is used to evaluate photoresist strip or cleaning chemicals using a combinatorial workflow. The electrical testing can be able to identify the damages on the high-k dielectrics, permitting a selection of photoresist strip chemicals to optimize the process conditions in the fabrication of semiconductor devices. The high productivity combinatorial technique can provide a compatibility evaluation of photoresist strip chemicals with high-k devices.
摘要翻译：金属氧化物半导体（MOS）高k电容器结构的电气测试用于使用组合工作流程来评估光致抗蚀剂条或清洁化学品。电气测试能够识别高k电介质上的损伤，允许选择光致抗蚀剂胶带化学品来优化半导体器件制造过程中的工艺条件。高生产率组合技术可以提供具有高k器件的光致抗蚀剂剥离化学品的兼容性评估。

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