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1. 发明授权

US06489655B2 Integrated circuit with dynamic threshold voltage 有权
标题翻译：具有动态阈值电压的集成电路
公开(公告)号：US06489655B2
公开(公告)日：2002-12-03
申请号：US09782540
申请日：2001-02-12
申请人： Brian S. Doyle , Brian Roberds , Rafael Rios
发明人： Brian S. Doyle , Brian Roberds , Rafael Rios
IPC分类号： H01L2701
CPC分类号： H01L29/78621 , H01L29/78606 , H01L29/78696
摘要： An integrated circuit and method for making it are described. The integrated circuit includes a first insulating layer formed on a substrate and a body strap of a first conductivity type that is formed on the first insulating layer. A second insulating layer is formed on the first insulating layer adjacent to the body strap and a film is formed on the second insulating layer. The integrated circuit also includes a gate electrode formed on the film. A plurality of doped regions of a second conductivity type are formed within the film that extend from the surface of the film to the surface of the second insulating layer. The doped regions have junctions that are each spaced from the body strap by at least about 500 angstroms.
摘要翻译：对集成电路及其制作方法进行说明。集成电路包括形成在基板上的第一绝缘层和形成在第一绝缘层上的第一导电类型的主体带。在与体带相邻的第一绝缘层上形成第二绝缘层，并且在第二绝缘层上形成膜。集成电路还包括形成在膜上的栅电极。在薄膜内形成多个第二导电类型的掺杂区，从薄膜的表面延伸到第二绝缘层的表面。掺杂区域具有与体带相隔至少约500埃的交点。

2. 发明授权

US06261878B1 Integrated circuit with dynamic threshold voltage 有权
标题翻译：具有动态阈值电压的集成电路
公开(公告)号：US06261878B1
公开(公告)日：2001-07-17
申请号：US09337174
申请日：1999-06-21
申请人： Brian S. Doyle , Brian Roberds , Rafael Rios
发明人： Brian S. Doyle , Brian Roberds , Rafael Rios
IPC分类号： H01L2100
CPC分类号： H01L29/78621 , H01L29/78606 , H01L29/78696
摘要： An integrated circuit and method for making it are described. The integrated circuit includes a first insulating layer formed on a substrate and a body strap of a first conductivity type that is formed on the first insulating layer. A second insulating layer is formed on the first insulating layer adjacent to the body strap and a film is formed on the second insulating layer. The integrated circuit also includes a gate electrode formed on the film. A plurality of doped regions of a second conductivity type are formed within the film that extend from the surface of the film to the surface of the second insulating layer. The doped regions have junctions that are each spaced from the body strap by at least about 500 angstroms.
摘要翻译：对集成电路及其制作方法进行说明。集成电路包括形成在基板上的第一绝缘层和形成在第一绝缘层上的第一导电类型的主体带。在与体带相邻的第一绝缘层上形成第二绝缘层，并且在第二绝缘层上形成膜。集成电路还包括形成在膜上的栅电极。在薄膜内形成多个第二导电类型的掺杂区，从薄膜的表面延伸到第二绝缘层的表面。掺杂区域具有与体带相隔至少约500埃的交点。

3. 发明授权

US06656822B2 Method for reduced capacitance interconnect system using gaseous implants into the ILD 失效
标题翻译：使用气体植入物进入ILD的电容互连系统的方法
公开(公告)号：US06656822B2
公开(公告)日：2003-12-02
申请号：US09344918
申请日：1999-06-28
申请人： Brian S. Doyle , Brian Roberds , Sandy S. Lee , Quat Vu
发明人： Brian S. Doyle , Brian Roberds , Sandy S. Lee , Quat Vu
IPC分类号： H01L21265
CPC分类号： H01L23/5329 , H01L21/31155 , H01L21/7682 , H01L21/76825 , H01L23/5222 , H01L2221/1047 , H01L2924/0002 , H01L2924/00
摘要： A method of decreasing the dielectric constant of a dielectric layer. First, a dielectric layer is formed on a first conductive layer. A substance is then implanted into the dielectric layer.
摘要翻译：降低介电层的介电常数的方法。首先，在第一导电层上形成电介质层。然后将物质注入电介质层。

4. 发明授权

US06952040B2 Transistor structure and method of fabrication 失效
标题翻译：晶体管结构及其制造方法
公开(公告)号：US06952040B2
公开(公告)日：2005-10-04
申请号：US09895697
申请日：2001-06-29
申请人： Robert S. Chau , Jack Kavalieros , Anand Murthy , Brian Roberds , Brian S. Doyle
发明人： Robert S. Chau , Jack Kavalieros , Anand Murthy , Brian Roberds , Brian S. Doyle
IPC分类号： H01L21/3205 , H01L21/336 , H01L29/49 , H01L29/76 , H01L29/786 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L29/66772 , H01L29/41783 , H01L29/4908 , H01L29/495 , H01L29/4966 , H01L29/4975 , H01L29/665 , H01L29/66628 , H01L29/78654 , Y10S977/70 , Y10S977/721 , Y10S977/936
摘要： A novel transistor structure and its method of fabrication. According to the present invention, the transistor includes an intrinsic silicon body having a first surface. A gate dielectric is formed on the first surface of the intrinsic silicon body. A gate electrode is formed on the gate dielectric wherein the gate electrode comprises a mid-gap work function film on the gate dielectric. A pair of source/drain regions are formed on opposite sides of the intrinsic silicon body.
摘要翻译：一种新颖的晶体管结构及其制造方法。根据本发明，晶体管包括具有第一表面的本征硅体。在本征硅体的第一表面上形成栅极电介质。栅极电极形成在栅极电介质上，其中栅电极在栅极电介质上包括中间间隙功函数膜。一对源极/漏极区域形成在本征硅体的相对侧上。

5. 发明授权

US06281532B1 Technique to obtain increased channel mobilities in NMOS transistors by gate electrode engineering 有权
标题翻译：通过栅极电极工程获得NMOS晶体管中增加的沟道迁移率的技术
公开(公告)号：US06281532B1
公开(公告)日：2001-08-28
申请号：US09340954
申请日：1999-06-28
申请人： Brian S. Doyle , Brian Roberds , Jin Lee
发明人： Brian S. Doyle , Brian Roberds , Jin Lee
IPC分类号： H01L2976
CPC分类号： H01L29/7845 , H01L21/26506 , H01L21/28026 , H01L29/0649 , H01L29/0653 , H01L29/7842
摘要： A method of modifying the mobility of a transistor. First, a transistor having a gate is formed. A substance is then implanted in the gate. The transistor is annealed such that the implanted substance forms at least one void in the transistor's gate.
摘要翻译：修改晶体管的迁移率的方法。首先，形成具有栅极的晶体管。然后将物质植入门。晶体管退火，使得注入的物质在晶体管的栅极中形成至少一个空隙。

6. 发明授权

US06815310B2 Technique to obtain high mobility channels in MOS transistors by forming a strain layer on an underside of a channel 有权
标题翻译：通过在通道的下侧形成应变层来获得MOS晶体管中的高迁移率通道的技术
公开(公告)号：US06815310B2
公开(公告)日：2004-11-09
申请号：US10366771
申请日：2003-02-14
申请人： Brian Roberds , Brian S. Doyle
发明人： Brian Roberds , Brian S. Doyle
IPC分类号： H01L2176
CPC分类号： H01L29/66916 , H01L29/1054 , H01L29/66636 , H01L29/7842 , H01L29/802
摘要： A method for forming a strain layer on an underside of a channel in an MOS transistor in order to produce a mechanical stress in the channel, increasing a mobility of carriers in the channel and an apparatus produced from such a method.

7. 发明授权

US06563152B2 Technique to obtain high mobility channels in MOS transistors by forming a strain layer on an underside of a channel 有权
公开(公告)号：US06563152B2
公开(公告)日：2003-05-13
申请号：US09752333
申请日：2000-12-29
申请人： Brian Roberds , Brian S. Doyle
发明人： Brian Roberds , Brian S. Doyle
IPC分类号： H01L2976
CPC分类号： H01L29/66916 , H01L29/1054 , H01L29/66636 , H01L29/7842 , H01L29/802
摘要： A method for forming a strain layer on an underside of a channel in an MOS transistor in order to produce a mechanical stress in the channel, increasing a mobility of carriers in the channel and an apparatus produced from such a method.

8. 发明授权

US06362082B1 Methodology for control of short channel effects in MOS transistors 有权
公开(公告)号：US06362082B1
公开(公告)日：2002-03-26
申请号：US09342030
申请日：1999-06-28
申请人： Brian S. Doyle , Brian Roberds
发明人： Brian S. Doyle , Brian Roberds
IPC分类号： H01L21265
CPC分类号： H01L29/0649 , H01L21/26506 , H01L21/26533 , H01L29/0653 , H01L29/7842
摘要： A method of improving short channel effects in a transistor. First, a substance is implanted in a substrate. The substrate is then annealed such that the implanted substance forms at least one void in the substrate. Then, a transistor having a source, a drain, and a channel region is formed on the substrate, wherein the at least one void is in the channel region of the transistor.

9. 发明授权

US06740913B2 MOS transistor using mechanical stress to control short channel effects 有权
标题翻译： MOS晶体管采用机械应力来控制短沟道效应
公开(公告)号：US06740913B2
公开(公告)日：2004-05-25
申请号：US10045376
申请日：2001-11-09
申请人： Brian S. Doyle , Brian Roberds
发明人： Brian S. Doyle , Brian Roberds
IPC分类号： H01L2976
CPC分类号： H01L29/0649 , H01L21/26506 , H01L21/26533 , H01L29/0653 , H01L29/7842
摘要： A transistor using mechanical stress to alter carrier mobility. Voids are formed in one or more of the source, drain, channel or gate regions to introduce tensile or compressive stress to improve short channel effects.
摘要翻译：使用机械应力来改变载流子迁移率的晶体管。在源极，漏极，沟道或栅极区域中的一个或多个中形成空穴以引入拉伸或压缩应力以改善短沟道效应。

10. 发明授权

US06653700B2 Transistor structure and method of fabrication 有权
标题翻译：晶体管结构及其制造方法
公开(公告)号：US06653700B2
公开(公告)日：2003-11-25
申请号：US10191118
申请日：2002-07-08
申请人： Robert S. Chau , Jack Kavalieros , Anand Murthy , Brian Roberds , Brian S. Doyle
发明人： Robert S. Chau , Jack Kavalieros , Anand Murthy , Brian Roberds , Brian S. Doyle
IPC分类号： H01L2976
CPC分类号： H01L29/66772 , H01L29/41783 , H01L29/4908 , H01L29/495 , H01L29/4966 , H01L29/4975 , H01L29/665 , H01L29/66628 , H01L29/78654 , Y10S977/70 , Y10S977/721 , Y10S977/936
摘要： A novel transistor structure and its method of fabrication. According to the present invention, the transistor includes an intrinsic silicon body having a first surface. A gate dielectric is formed on the first surface of the intrinsic silicon body. A gate electrode is formed on the gate dielectric wherein the gate electrode comprises a mid-gap work function film on the gate dielectric. A pair of source/drain regions are formed on opposite sides of the intrinsic silicon body.
摘要翻译：一种新颖的晶体管结构及其制造方法。根据本发明，晶体管包括具有第一表面的本征硅体。在本征硅体的第一表面上形成栅极电介质。栅极电极形成在栅极电介质上，其中栅电极在栅极电介质上包括中间间隙功函数膜。一对源极/漏极区域形成在本征硅体的相对侧上。

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