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1. 发明授权

US06489655B2 Integrated circuit with dynamic threshold voltage 有权
标题翻译：具有动态阈值电压的集成电路
公开(公告)号：US06489655B2
公开(公告)日：2002-12-03
申请号：US09782540
申请日：2001-02-12
申请人： Brian S. Doyle , Brian Roberds , Rafael Rios
发明人： Brian S. Doyle , Brian Roberds , Rafael Rios
IPC分类号： H01L2701
CPC分类号： H01L29/78621 , H01L29/78606 , H01L29/78696
摘要： An integrated circuit and method for making it are described. The integrated circuit includes a first insulating layer formed on a substrate and a body strap of a first conductivity type that is formed on the first insulating layer. A second insulating layer is formed on the first insulating layer adjacent to the body strap and a film is formed on the second insulating layer. The integrated circuit also includes a gate electrode formed on the film. A plurality of doped regions of a second conductivity type are formed within the film that extend from the surface of the film to the surface of the second insulating layer. The doped regions have junctions that are each spaced from the body strap by at least about 500 angstroms.
摘要翻译：对集成电路及其制作方法进行说明。集成电路包括形成在基板上的第一绝缘层和形成在第一绝缘层上的第一导电类型的主体带。在与体带相邻的第一绝缘层上形成第二绝缘层，并且在第二绝缘层上形成膜。集成电路还包括形成在膜上的栅电极。在薄膜内形成多个第二导电类型的掺杂区，从薄膜的表面延伸到第二绝缘层的表面。掺杂区域具有与体带相隔至少约500埃的交点。

2. 发明授权

US06261878B1 Integrated circuit with dynamic threshold voltage 有权
标题翻译：具有动态阈值电压的集成电路
公开(公告)号：US06261878B1
公开(公告)日：2001-07-17
申请号：US09337174
申请日：1999-06-21
申请人： Brian S. Doyle , Brian Roberds , Rafael Rios
发明人： Brian S. Doyle , Brian Roberds , Rafael Rios
IPC分类号： H01L2100
CPC分类号： H01L29/78621 , H01L29/78606 , H01L29/78696
摘要： An integrated circuit and method for making it are described. The integrated circuit includes a first insulating layer formed on a substrate and a body strap of a first conductivity type that is formed on the first insulating layer. A second insulating layer is formed on the first insulating layer adjacent to the body strap and a film is formed on the second insulating layer. The integrated circuit also includes a gate electrode formed on the film. A plurality of doped regions of a second conductivity type are formed within the film that extend from the surface of the film to the surface of the second insulating layer. The doped regions have junctions that are each spaced from the body strap by at least about 500 angstroms.
摘要翻译：对集成电路及其制作方法进行说明。集成电路包括形成在基板上的第一绝缘层和形成在第一绝缘层上的第一导电类型的主体带。在与体带相邻的第一绝缘层上形成第二绝缘层，并且在第二绝缘层上形成膜。集成电路还包括形成在膜上的栅电极。在薄膜内形成多个第二导电类型的掺杂区，从薄膜的表面延伸到第二绝缘层的表面。掺杂区域具有与体带相隔至少约500埃的交点。

3. 发明授权

US07456476B2 Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication 有权
标题翻译：非平面半导体器件部分或完全缠绕在栅极电极和制造方法
公开(公告)号：US07456476B2
公开(公告)日：2008-11-25
申请号：US10607769
申请日：2003-06-27
申请人： Scott A. Hareland , Robert S. Chau , Brian S. Doyle , Rafael Rios , Tom Linton , Suman Datta
发明人： Scott A. Hareland , Robert S. Chau , Brian S. Doyle , Rafael Rios , Tom Linton , Suman Datta
IPC分类号： H01L29/786
CPC分类号： H01L29/785 , H01L29/42384 , H01L29/42392 , H01L29/66545 , H01L29/66772 , H01L29/66795
摘要： A nonplanar semiconductor device and its method of fabrication is described. The nonplanar semiconductor device includes a semiconductor body having a top surface opposite a bottom surface formed above an insulating substrate wherein the semiconductor body has a pair laterally opposite sidewalls. A gate dielectric is formed on the top surface of the semiconductor body on the laterally opposite sidewalls of the semiconductor body and on at least a portion of the bottom surface of semiconductor body. A gate electrode is formed on the gate dielectric, on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of semiconductor body and beneath the gate dielectric on the bottom surface of the semiconductor body. A pair source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.
摘要翻译：描述了非平面半导体器件及其制造方法。非平面半导体器件包括半导体本体，该半导体本体具有与形成在绝缘基板上方的底表面相对的顶表面，其中半导体本体具有一对横向相对的侧壁。在半导体本体的横向相对的侧壁和半导体本体的底表面的至少一部分上的半导体本体的顶表面上形成栅极电介质。栅极电极形成在半导体本体的顶表面上并与半导体本体的横向相对的侧壁上的栅电介质相邻并位于半导体本体的底表面上的栅电介质之下的栅电介质上。在栅电极的相对侧的半导体本体中形成一对源/漏区。

4. 发明申请

US20080237719A1 Multi-gate structure and method of doping same 审中-公开
标题翻译：多栅极结构及掺杂方法
公开(公告)号：US20080237719A1
公开(公告)日：2008-10-02
申请号：US11729198
申请日：2007-03-28
申请人： Brian S. Doyle , Suman Datta , Jack T. Kavalieros , Rafael Rios
发明人： Brian S. Doyle , Suman Datta , Jack T. Kavalieros , Rafael Rios
IPC分类号： H01L27/12 , H01L21/8238
CPC分类号： H01L29/785 , H01L29/66795 , H01L29/66803
摘要： A multi-gate structure includes a substrate (110, 210, 410), an electrically insulating layer (120, 220, 420) over the substrate, and a first semiconducting fin (130, 230, 430) above the electrically insulating layer. The first semiconducting fin includes a top region (131, 231, 431), a first side region (132, 232, 432), and a second side region (133, 233, 433). The top region, the first side region, and the second side region have doping concentrations that are substantially equal to each other. The multi-gate structure may be made by depositing a solid source material (510) over the semiconducting fin, and by annealing the multi-gate structure such that dopants from the solid source material diffuse into the semiconducting fin and uniformly dope the top region and the first and second side regions.
摘要翻译：多栅极结构包括衬底（110,210,410），在衬底上方的电绝缘层（120,220,420）以及在电绝缘层上方的第一半导电翅片（130,230,430）。第一半导体鳍片包括顶部区域（131,231,431），第一侧面区域（132,232,432）和第二侧面区域（133,233,433）。顶部区域，第一侧面区域和第二侧面区域具有彼此基本相等的掺杂浓度。多栅极结构可以通过在半导体鳍上沉积固体源材料（510）并且通过退火多栅极结构使得来自固体源材料的掺杂剂扩散到半导体翅片中并且均匀地掺杂顶部区域和第一和第二侧区域。

5. 发明授权

US06960517B2 N-gate transistor 失效
标题翻译： N栅晶体管
公开(公告)号：US06960517B2
公开(公告)日：2005-11-01
申请号：US10610835
申请日：2003-06-30
申请人： Rafael Rios , Brian S. Doyle , Thomas D. Linton, Jr. , Jack Kavalieros
发明人： Rafael Rios , Brian S. Doyle , Thomas D. Linton, Jr. , Jack Kavalieros
IPC分类号： H01L21/336 , H01L29/786 , H01L21/3205
CPC分类号： H01L29/7853 , H01L29/66795
摘要： A n-gate transistor, and method of forming such, including source/drain regions connected by a channel region and a gate electrode coupled to the channel region. The channel region has many angled edges protruding into the gate electrode. The many angled edges are to act as electrically conducting channel conduits between source/drain regions.
摘要翻译：一种n型栅极晶体管及其形成方法，包括由沟道区域连接的源极/漏极区域和耦合到沟道区域的栅电极。通道区域具有突出到栅电极中的许多成角度的边缘。许多成角度的边缘用作在源极/漏极区域之间的导电沟道导管。

6. 发明授权

US08273626B2 Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication 有权
标题翻译：非平面半导体器件部分或完全缠绕在栅极电极和制造方法
公开(公告)号：US08273626B2
公开(公告)日：2012-09-25
申请号：US12893753
申请日：2010-09-29
申请人： Scott A. Hareland , Robert S. Chau , Brian S. Doyle , Rafael Rios , Tom Linton , Suman Datta
发明人： Scott A. Hareland , Robert S. Chau , Brian S. Doyle , Rafael Rios , Tom Linton , Suman Datta
IPC分类号： H01L21/84
CPC分类号： H01L29/785 , H01L29/42384 , H01L29/42392 , H01L29/66545 , H01L29/66772 , H01L29/66795
摘要： A nonplanar semiconductor device and its method of fabrication is described. The nonplanar semiconductor device includes a semiconductor body having a top surface opposite a bottom surface formed above an insulating substrate wherein the semiconductor body has a pair laterally opposite sidewalls. A gate dielectric is formed on the top surface of the semiconductor body on the laterally opposite sidewalls of the semiconductor body and on at least a portion of the bottom surface of semiconductor body. A gate electrode is formed on the gate dielectric, on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of semiconductor body and beneath the gate dielectric on the bottom surface of the semiconductor body. A pair source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.
摘要翻译：描述了非平面半导体器件及其制造方法。非平面半导体器件包括半导体本体，该半导体本体具有与形成在绝缘基板上方的底表面相对的顶表面，其中半导体本体具有一对横向相对的侧壁。在半导体本体的横向相对的侧壁和半导体本体的底表面的至少一部分上的半导体本体的顶表面上形成栅极电介质。栅极电极形成在半导体本体的顶表面上并与半导体本体的横向相对的侧壁上的栅电介质相邻并位于半导体本体的底表面上的栅电介质之下的栅电介质上。在栅电极的相对侧的半导体本体中形成一对源/漏区。

7. 发明授权

US07820513B2 Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication 有权
标题翻译：非平面半导体器件部分或完全缠绕在栅极电极和制造方法
公开(公告)号：US07820513B2
公开(公告)日：2010-10-26
申请号：US12259464
申请日：2008-10-28
申请人： Scott A. Hareland , Robert S. Chau , Brian S. Doyle , Rafael Rios , Tom Linton , Suman Datta
发明人： Scott A. Hareland , Robert S. Chau , Brian S. Doyle , Rafael Rios , Tom Linton , Suman Datta
IPC分类号： H01L21/84
CPC分类号： H01L29/785 , H01L29/42384 , H01L29/42392 , H01L29/66545 , H01L29/66772 , H01L29/66795
摘要： A nonplanar semiconductor device and its method of fabrication is described. The nonplanar semiconductor device includes a semiconductor body having a top surface opposite a bottom surface formed above an insulating substrate wherein the semiconductor body has a pair laterally opposite sidewalls. A gate dielectric is formed on the top surface of the semiconductor body on the laterally opposite sidewalls of the semiconductor body and on at least a portion of the bottom surface of semiconductor body. A gate electrode is formed on the gate dielectric, on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of semiconductor body and beneath the gate dielectric on the bottom surface of the semiconductor body. A pair source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.
摘要翻译：描述了非平面半导体器件及其制造方法。非平面半导体器件包括半导体本体，该半导体本体具有与形成在绝缘基板上方的底表面相对的顶表面，其中半导体本体具有一对横向相对的侧壁。在半导体本体的横向相对的侧壁和半导体本体的底表面的至少一部分上的半导体本体的顶表面上形成栅极电介质。栅极电极形成在半导体本体的顶表面上并与半导体本体的横向相对的侧壁上的栅电介质相邻并位于半导体本体的底表面上的栅电介质之下的栅电介质上。在栅电极的相对侧的半导体本体中形成一对源/漏区。

8. 发明授权

US06740913B2 MOS transistor using mechanical stress to control short channel effects 有权
标题翻译： MOS晶体管采用机械应力来控制短沟道效应
公开(公告)号：US06740913B2
公开(公告)日：2004-05-25
申请号：US10045376
申请日：2001-11-09
申请人： Brian S. Doyle , Brian Roberds
发明人： Brian S. Doyle , Brian Roberds
IPC分类号： H01L2976
CPC分类号： H01L29/0649 , H01L21/26506 , H01L21/26533 , H01L29/0653 , H01L29/7842
摘要： A transistor using mechanical stress to alter carrier mobility. Voids are formed in one or more of the source, drain, channel or gate regions to introduce tensile or compressive stress to improve short channel effects.
摘要翻译：使用机械应力来改变载流子迁移率的晶体管。在源极，漏极，沟道或栅极区域中的一个或多个中形成空穴以引入拉伸或压缩应力以改善短沟道效应。

9. 发明授权

US06653700B2 Transistor structure and method of fabrication 有权
标题翻译：晶体管结构及其制造方法
公开(公告)号：US06653700B2
公开(公告)日：2003-11-25
申请号：US10191118
申请日：2002-07-08
申请人： Robert S. Chau , Jack Kavalieros , Anand Murthy , Brian Roberds , Brian S. Doyle
发明人： Robert S. Chau , Jack Kavalieros , Anand Murthy , Brian Roberds , Brian S. Doyle
IPC分类号： H01L2976
CPC分类号： H01L29/66772 , H01L29/41783 , H01L29/4908 , H01L29/495 , H01L29/4966 , H01L29/4975 , H01L29/665 , H01L29/66628 , H01L29/78654 , Y10S977/70 , Y10S977/721 , Y10S977/936
摘要： A novel transistor structure and its method of fabrication. According to the present invention, the transistor includes an intrinsic silicon body having a first surface. A gate dielectric is formed on the first surface of the intrinsic silicon body. A gate electrode is formed on the gate dielectric wherein the gate electrode comprises a mid-gap work function film on the gate dielectric. A pair of source/drain regions are formed on opposite sides of the intrinsic silicon body.
摘要翻译：一种新颖的晶体管结构及其制造方法。根据本发明，晶体管包括具有第一表面的本征硅体。在本征硅体的第一表面上形成栅极电介质。栅极电极形成在栅极电介质上，其中栅电极在栅极电介质上包括中间间隙功函数膜。一对源极/漏极区域形成在本征硅体的相对侧上。

10. 发明授权

US06228694B1 Method of increasing the mobility of MOS transistors by use of localized stress regions 有权
标题翻译：通过使用局部应力区域增加MOS晶体管的迁移率的方法
公开(公告)号：US06228694B1
公开(公告)日：2001-05-08
申请号：US09340583
申请日：1999-06-28
申请人： Brian S. Doyle , Brian Roberds , Jin Lee
发明人： Brian S. Doyle , Brian Roberds , Jin Lee
IPC分类号： H01L218238
CPC分类号： H01L21/26506 , H01L21/823412 , H01L21/823418 , H01L29/0649 , H01L29/0653 , H01L29/32 , H01L29/7842
摘要： A method of modifying the mobility of a transistor. First, a substance is implanted into a substrate. The substrate is then annealed such that the implanted substance forms at least one void in the substrate. Then, a transistor is formed on the substrate.
摘要翻译：修改晶体管的迁移率的方法。首先，将物质植入基材中。然后将衬底退火，使得注入的物质在衬底中形成至少一个空隙。然后，在基板上形成晶体管。

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