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1. 发明申请

US20140262707A1 NANOWIRE-BASED MECHANICAL SWITCHING DEVICE 有权
标题翻译：基于纳米级的机械开关装置
公开(公告)号：US20140262707A1
公开(公告)日：2014-09-18
申请号：US13996507
申请日：2013-03-14
申请人： Chytra Pawashe , Kevin Lin , Anurag Chaudhry , Raseong Kim , Seiyon Kim , Kelin Kuhn , Sasikanth Manipatruni , Rafael Rios , Ian A. Young
发明人： Chytra Pawashe , Kevin Lin , Anurag Chaudhry , Raseong Kim , Seiyon Kim , Kelin Kuhn , Sasikanth Manipatruni , Rafael Rios , Ian A. Young
IPC分类号： H01H59/00
CPC分类号： H01L29/84 , B82Y10/00 , H01H1/0094 , H01H9/0271 , H01H59/0009 , H01L29/045 , H01L29/0673 , H01L29/161
摘要： Nanowire-based mechanical switching devices are described. For example, a nanowire relay includes a nanowire disposed in a void disposed above a substrate. The nanowire has an anchored portion and a suspended portion. A first gate electrode is disposed adjacent the void, and is spaced apart from the nanowire. A first conductive region is disposed adjacent the first gate electrode and adjacent the void, and is spaced apart from the nanowire.
摘要翻译：描述了基于纳米线的机械开关装置。例如，纳米线继电器包括布置在衬底上方的空隙中的纳米线。纳米线具有锚固部分和悬挂部分。第一栅电极邻近空隙设置，并与纳米线隔开。第一导电区域邻近第一栅电极设置并邻近空隙，并与纳米线隔开。

2. 发明申请

US20160329438A1 NANOWIRE-BASED MECHANICAL SWITCHING DEVICE 有权
标题翻译：基于纳米级的机械开关装置
公开(公告)号：US20160329438A1
公开(公告)日：2016-11-10
申请号：US15151381
申请日：2016-05-10
申请人： Chytra Pawashe , Kevin Lin , Anurag Chaudhry , Raseong Kim , Seiyon Kim , Kelin Kuhn , Sasikanth Manipatruni , Rafael Rios , Ian A. Young
发明人： Chytra Pawashe , Kevin Lin , Anurag Chaudhry , Raseong Kim , Seiyon Kim , Kelin Kuhn , Sasikanth Manipatruni , Rafael Rios , Ian A. Young
IPC分类号： H01L29/84 , H01H59/00 , H01L29/161 , H01L29/06 , H01L29/04
CPC分类号： H01L29/84 , B82Y10/00 , H01H1/0094 , H01H9/0271 , H01H59/0009 , H01L29/045 , H01L29/0673 , H01L29/161
摘要： Nanowire-based mechanical switching devices are described. For example, a nanowire relay includes a nanowire disposed in a void disposed above a substrate. The nanowire has an anchored portion and a suspended portion. A first gate electrode is disposed adjacent the void, and is spaced apart from the nanowire. A first conductive region is disposed adjacent the first gate electrode and adjacent the void, and is spaced apart from the nanowire.
摘要翻译：描述了基于纳米线的机械开关装置。例如，纳米线继电器包括布置在衬底上方的空隙中的纳米线。纳米线具有锚固部分和悬挂部分。第一栅电极邻近空隙设置，并与纳米线隔开。第一导电区域邻近第一栅电极设置并邻近空隙，并与纳米线隔开。

3. 发明授权

US09362074B2 Nanowire-based mechanical switching device 有权
标题翻译：基于纳米线的机械开关装置
公开(公告)号：US09362074B2
公开(公告)日：2016-06-07
申请号：US13996507
申请日：2013-03-14
申请人： Chytra Pawashe , Kevin Lin , Anurag Chaudhry , Raseong Kim , Seiyon Kim , Kelin Kuhn , Sasikanth Manipatruni , Rafael Rios , Ian A. Young
发明人： Chytra Pawashe , Kevin Lin , Anurag Chaudhry , Raseong Kim , Seiyon Kim , Kelin Kuhn , Sasikanth Manipatruni , Rafael Rios , Ian A. Young
IPC分类号： H01H51/22 , H01H59/00 , B82Y10/00 , H01H1/00 , H01H9/02
CPC分类号： H01L29/84 , B82Y10/00 , H01H1/0094 , H01H9/0271 , H01H59/0009 , H01L29/045 , H01L29/0673 , H01L29/161
摘要： Nanowire-based mechanical switching devices are described. For example, a nanowire relay includes a nanowire disposed in a void disposed above a substrate. The nanowire has an anchored portion and a suspended portion. A first gate electrode is disposed adjacent the void, and is spaced apart from the nanowire. A first conductive region is disposed adjacent the first gate electrode and adjacent the void, and is spaced apart from the nanowire.
摘要翻译：描述了基于纳米线的机械开关装置。例如，纳米线继电器包括布置在衬底上方的空隙中的纳米线。纳米线具有锚固部分和悬挂部分。第一栅电极邻近空隙设置，并与纳米线隔开。第一导电区域邻近第一栅电极设置并邻近空隙，并与纳米线隔开。

4. 发明申请

US20140264253A1 LEAKAGE REDUCTION STRUCTURES FOR NANOWIRE TRANSISTORS 有权
标题翻译：纳米晶体管的漏电减少结构
公开(公告)号：US20140264253A1
公开(公告)日：2014-09-18
申请号：US13996845
申请日：2013-03-14
申请人： Seiyon Kim , Kelin Kuhn , Rafael Rios , Mark Armstrong
发明人： Seiyon Kim , Kelin Kuhn , Rafael Rios , Mark Armstrong
IPC分类号： H01L29/06 , H01L29/66 , H01L29/786 , H01L21/266 , H01L29/10 , H01L21/265
CPC分类号： H01L29/0673 , H01L29/16 , H01L29/42392 , H01L29/66439 , H01L29/775 , H01L29/785 , H01L29/78696
摘要： A nanowire device of the present description may include a highly doped underlayer formed between at least one nanowire transistor and the microelectronic substrate on which the nanowire transistors are formed, wherein the highly doped underlayer may reduce or substantially eliminate leakage and high gate capacitance which can occur at a bottom portion of a gate structure of the nanowire transistors. As the formation of the highly doped underlayer may result in gate inducted drain leakage at an interface between source structures and drain structures of the nanowire transistors, a thin layer of undoped or low doped material may be formed between the highly doped underlayer and the nanowire transistors.
摘要翻译：本描述的纳米线器件可以包括形成在至少一个纳米线晶体管和其上形成纳米线晶体管的微电子衬底之间的高度掺杂的底层，其中高度掺杂的底层可以减少或基本上消除可能发生的泄漏和高栅极电容在纳米线晶体管的栅极结构的底部。由于高掺杂底层的形成可能导致在纳米线晶体管的源极结构和漏极结构之间的界面处的栅极感应漏极泄漏，可以在高掺杂底层和纳米线晶体管之间形成未掺杂或低掺杂材料的薄层。

5. 发明申请

US20140264280A1 NANOWIRE TRANSISTOR WITH UNDERLAYER ETCH STOPS 有权
标题翻译：具有下层蚀刻层的纳米晶体管
公开(公告)号：US20140264280A1
公开(公告)日：2014-09-18
申请号：US13996848
申请日：2013-03-15
申请人： Seiyon Kim , Daniel Aubertine , Kelin Kuhn , Anand Murthy
发明人： Seiyon Kim , Daniel Aubertine , Kelin Kuhn , Anand Murthy
IPC分类号： H01L29/06 , H01L29/66 , H01L29/775 , H01L29/78
CPC分类号： H01L29/66795 , H01L29/0673 , H01L29/1037 , H01L29/42392 , H01L29/66439 , H01L29/66545 , H01L29/6656 , H01L29/6681 , H01L29/66818 , H01L29/775 , H01L29/785 , H01L29/78696
摘要： A nanowire device of the present description may be produced with the incorporation of at least one underlayer etch stop formed during the fabrication of at least one nanowire transistor in order to assist in protecting source structures and/or drain structures from damage that may result from fabrication processes. The underlayer etch stop may prevent damage to the source structures andor drain the structures, when the material used in the fabrication of the source structures andor the drain structures is susceptible to being etched by the processes used in the removal of the sacrificial materials, i.e. low selectively to the source structure and/or the drain structure materials, such that potential shorting between the transistor gate electrodes and contacts formed for the source structures andor the drain structures may be prevented.
摘要翻译：本描述的纳米线器件可以通过结合在制造至少一个纳米线晶体管期间形成的至少一个底层蚀刻停止来产生，以便有助于保护源结构和/或漏极结构免受可能由制造产生的损伤过程。当用于制造源结构的材料和漏极结构易于被用于去除牺牲材料的工艺被蚀刻时，底层蚀刻停止件可以防止对源结构的损坏和排出结构，即低选择性地连接到源极结构和/或漏极结构材料，使得可以防止晶体管栅电极和为源结构形成的触点之间的电位短路以及漏极结构。

6. 发明授权

US09064944B2 Nanowire transistor with underlayer etch stops 有权
标题翻译：具有底层蚀刻的纳米线晶体管停止
公开(公告)号：US09064944B2
公开(公告)日：2015-06-23
申请号：US13996848
申请日：2013-03-15
申请人： Seiyon Kim , Daniel Aubertine , Kelin Kuhn , Anand Murthy
发明人： Seiyon Kim , Daniel Aubertine , Kelin Kuhn , Anand Murthy
IPC分类号： H01L29/06 , H01L29/775 , H01L29/78 , H01L29/66
CPC分类号： H01L29/66795 , H01L29/0673 , H01L29/1037 , H01L29/42392 , H01L29/66439 , H01L29/66545 , H01L29/6656 , H01L29/6681 , H01L29/66818 , H01L29/775 , H01L29/785 , H01L29/78696
摘要： A nanowire device of the present description may be produced with the incorporation of at least one underlayer etch stop formed during the fabrication of at least one nanowire transistor in order to assist in protecting source structures and/or drain structures from damage that may result from fabrication processes. The underlayer etch stop may prevent damage to the source structures and/or drain the structures, when the material used in the fabrication of the source structures and/or the drain structures is susceptible to being etched by the processes used in the removal of the sacrificial materials, i.e. low selectively to the source structure and/or the drain structure materials, such that potential shorting between the transistor gate electrodes and contacts formed for the source structures and/or the drain structures may be prevented.
摘要翻译：本描述的纳米线器件可以通过结合在制造至少一个纳米线晶体管期间形成的至少一个底层蚀刻停止来产生，以便有助于保护源结构和/或漏极结构免受可能由制造产生的损伤过程。当在源结构和/或漏极结构的制造中使用的材料易于被用于去除牺牲物的过程被蚀刻时，底层蚀刻停止件可以防止对源结构的损坏和/或排出结构材料，即选择性地低至源极结构和/或漏极结构材料，使得可以防止晶体管栅电极和为源极结构和/或漏极结构形成的触点之间的电位短路。

7. 发明申请

US20080036005A1 CMOS FABRICATION PROCESS UTILIZING SPECIAL TRANSISTOR ORIENTATION 有权
标题翻译： CMOS制造工艺利用特殊晶体管方向
公开(公告)号：US20080036005A1
公开(公告)日：2008-02-14
申请号：US11874129
申请日：2007-10-17
申请人： Mark Armstrong , Gerhard Schrom , Sunit Tyagi , Paul Packan , Kelin Kuhn , Scott Thompson
发明人： Mark Armstrong , Gerhard Schrom , Sunit Tyagi , Paul Packan , Kelin Kuhn , Scott Thompson
IPC分类号： H01L29/76
CPC分类号： H01L27/1446 , H01L21/823807 , H01L21/823878 , H01L27/0922 , H01L29/045 , H01L29/7843 , H01L29/7846
摘要： Complementary metal oxide semiconductor transistors are formed on a silicon substrate. The substrate has a {100} crystallographic orientation. The transistors are formed on the substrate so that current flows in the channels of the transistors are parallel to the direction. Additionally, longitudinal tensile stress is applied to the channels.
摘要翻译：互补金属氧化物半导体晶体管形成在硅衬底上。基板具有{100}晶体取向。晶体管形成在衬底上，使得电流在晶体管的沟道中流动平行于<100>方向。此外，纵向拉伸应力施加到通道。

8. 发明申请

US20120305990A1 METHODS AND APPARATUS TO REDUCE LAYOUT BASED STRAIN VARIATIONS IN NON-PLANAR TRANSISTOR STRUCTURES 有权
标题翻译：减少非平面晶体管结构中基于布局的应变变化的方法和装置
公开(公告)号：US20120305990A1
公开(公告)日：2012-12-06
申请号：US13588416
申请日：2012-08-17
申请人： Stephen M Cea , Martin D. Giles , Kelin Kuhn , Jack T. Kavalieros , Markus Kuhn
发明人： Stephen M Cea , Martin D. Giles , Kelin Kuhn , Jack T. Kavalieros , Markus Kuhn
IPC分类号： H01L29/78 , H01L21/265
CPC分类号： H01L29/785 , H01L21/76224 , H01L29/66795 , H01L29/7842
摘要： The present disclosure relates to the field of fabricating microelectronic devices. In at least one embodiment, the present disclosure relates to forming isolation structures in strained semiconductor bodies of non-planar transistors while maintaining strain in the semiconductor bodies.
摘要翻译：本公开涉及制造微电子器件的领域。在至少一个实施例中，本公开涉及在保持半导体本体中的应变的同时在非平面晶体管的应变半导体本体中形成隔离结构。

9. 发明申请

US20070236850A1 Power switches having positive-channel high dielectric constant insulated gate field effect transistors 有权
标题翻译：具有正通道高介电常数绝缘栅场效应晶体管的电源开关
公开(公告)号：US20070236850A1
公开(公告)日：2007-10-11
申请号：US11394810
申请日：2006-03-31
申请人： Kelin Kuhn , Richard Hose , Edward Burton , Rajesh Kumar
发明人： Kelin Kuhn , Richard Hose , Edward Burton , Rajesh Kumar
IPC分类号： H02H3/22
CPC分类号： H01L27/088
摘要： Power switch units for microelectronic devices are disclosed. In one aspect, a microelectronic device may include a functional circuit, and a power switch unit to switch power to the functional circuit on and off. The power switch unit may include a large number of transistors coupled together. The transistors may include predominantly positive-channel, insulated gate field effect transistors, which have a gate dielectric that includes a high dielectric constant material. Power switch units having such transistors may tend to have low power consumption. In an aspect, an overdrive voltage may be applied to the gates of such transistors to further reduce power consumption. Methods of overdriving such transistors and systems including such power switch units are also disclosed.
摘要翻译：公开了用于微电子器件的功率开关单元。一方面，微电子器件可以包括功能电路，以及电源开关单元，用于将功率电路接通和断开。电源开关单元可以包括耦合在一起的大量晶体管。晶体管可以包括主要为正沟道绝缘栅场效应晶体管，其具有包括高介电常数材料的栅极电介质。具有这种晶体管的功率开关单元倾向于具有低功耗。在一方面，可以将过驱动电压施加到这种晶体管的栅极，以进一步降低功耗。还公开了过载驱动这种晶体管和包括这种功率开关单元的系统的方法。

10. 发明申请

US20110147847A1 Methods and apparatus to reduce layout based strain variations in non-planar transistor structures 有权
标题翻译：减少非平面晶体管结构中基于布局的应变变化的方法和装置
公开(公告)号：US20110147847A1
公开(公告)日：2011-06-23
申请号：US12653971
申请日：2009-12-21
申请人： Stephen M. Cea , Martin D. Giles , Kelin Kuhn , Jack T. Kavalieros , Markus Kuhn
发明人： Stephen M. Cea , Martin D. Giles , Kelin Kuhn , Jack T. Kavalieros , Markus Kuhn
IPC分类号： H01L29/78 , H01L21/762
CPC分类号： H01L29/785 , H01L21/76224 , H01L29/66795 , H01L29/7842
摘要： The present disclosure relates to the field of fabricating microelectronic devices. In at least one embodiment, the present disclosure relates to forming isolation structures in strained semiconductor bodies of non-planar transistors while maintaining strain in the semiconductor bodies.
摘要翻译：本公开涉及制造微电子器件的领域。在至少一个实施例中，本公开涉及在保持半导体本体中的应变的同时在非平面晶体管的应变半导体本体中形成隔离结构。

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