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1. 发明申请

US20190103156A1 FULL-RAIL DIGITAL READ COMPUTE-IN-MEMORY CIRCUIT 审中-公开
公开(公告)号：US20190103156A1
公开(公告)日：2019-04-04
申请号：US16146932
申请日：2018-09-28
申请人： Huseyin Ekin SUMBUL , Gregory K. CHEN , Raghavan KUMAR , Phil Ekin KNAG , Abhishek SHARMA , Sasikanth MANIPATRUNI , Amrita MATHURIYA , Ram A. KRISHNAMURTHY , Ian A. YOUNG
发明人： Huseyin Ekin SUMBUL , Gregory K. CHEN , Raghavan KUMAR , Phil Ekin KNAG , Abhishek SHARMA , Sasikanth MANIPATRUNI , Amrita MATHURIYA , Ram A. KRISHNAMURTHY , Ian A. YOUNG
IPC分类号： G11C11/419
CPC分类号： G11C11/419 , G11C7/1006 , G11C7/12 , G11C11/412 , G11C11/418 , G11C27/024
摘要： A full-rail digital-read CIM circuit enables a weighted read operation on a single row of a memory array. A weighted read operation captures a value of a weight stored in the single memory array row without having to rely on weighted row-access. Rather, using full-rail access and a weighted sampling capacitance network, the CIM circuit enables the weighted read operation even under process variation, noise and mismatch.

2. 发明授权

US09583602B2 Tunneling field effect transistors (TFETs) for CMOS architectures and approaches to fabricating N-type and P-type TFETs 有权
标题翻译：用于CMOS架构的隧道场效应晶体管（TFET）和制造N型和P型TFET的方法
公开(公告)号：US09583602B2
公开(公告)日：2017-02-28
申请号：US15209552
申请日：2016-07-13
申请人： Roza Kotlyar , Stephen M. Cea , Gilbert Dewey , Benjamin Chu-Kung , Uygar E. Avci , Rafael Rios , Anurag Chaudhry , Thomas D. Linton, Jr. , Ian A. Young , Kelin J. Kuhn
发明人： Roza Kotlyar , Stephen M. Cea , Gilbert Dewey , Benjamin Chu-Kung , Uygar E. Avci , Rafael Rios , Anurag Chaudhry , Thomas D. Linton, Jr. , Ian A. Young , Kelin J. Kuhn
IPC分类号： H01L29/66 , H01L29/78 , H01L29/739 , H01L29/16 , H01L29/161 , H01L29/06 , H01L29/24 , H01L29/267 , H01L27/092 , H01L29/04 , H01L29/10 , H01L29/165 , H01L29/20 , H01L29/423 , H01L29/786
CPC分类号： H01L29/66977 , H01L27/092 , H01L29/045 , H01L29/0676 , H01L29/068 , H01L29/1054 , H01L29/16 , H01L29/161 , H01L29/165 , H01L29/20 , H01L29/24 , H01L29/267 , H01L29/42392 , H01L29/7391 , H01L29/7842 , H01L29/785 , H01L29/78603 , H01L29/78642 , H01L29/78684 , H01L29/78696
摘要： Tunneling field effect transistors (TFETs) for CMOS architectures and approaches to fabricating N-type and P-type TFETs are described. For example, a tunneling field effect transistor (TFET) includes a homojunction active region disposed above a substrate. The homojunction active region includes a relaxed Ge or GeSn body having an undoped channel region therein. The homojunction active region also includes doped source and drain regions disposed in the relaxed Ge or GeSn body, on either side of the channel region. The TFET also includes a gate stack disposed on the channel region, between the source and drain regions. The gate stack includes a gate dielectric portion and gate electrode portion.
摘要翻译：描述了用于CMOS架构的隧道场效应晶体管（TFET）和制造N型和P型TFET的方法。例如，隧道场效应晶体管（TFET）包括设置在衬底上方的均质有源区。同质结有源区包括其中具有未掺杂沟道区的松弛Ge或GeSn体。同质结有源区还包括设置在放大的Ge或GeSn体中，在沟道区两侧的掺杂源极和漏极区。 TFET还包括设置在沟道区域之间的源极和漏极区域之间的栅极堆叠。栅极堆叠包括栅极电介质部分和栅极电极部分。

3. 发明授权

US09526285B2 Flexible computing fabric 有权
标题翻译：灵活计算架构
公开(公告)号：US09526285B2
公开(公告)日：2016-12-27
申请号：US13717909
申请日：2012-12-18
申请人： Aleksandar Aleksov , Ravindranath V. Mahajan , Sairam Agraharam , Ian A. Young , John C. Johnson , Debendra Mallik , John S. Guzek
发明人： Aleksandar Aleksov , Ravindranath V. Mahajan , Sairam Agraharam , Ian A. Young , John C. Johnson , Debendra Mallik , John S. Guzek
IPC分类号： H05K1/02 , H05K3/30 , A41D31/00 , H05K1/03 , H05K1/18 , H05K3/32 , H05K3/34
CPC分类号： A41D31/00 , H05K1/0274 , H05K1/038 , H05K1/188 , H05K3/323 , H05K3/3436 , Y10T29/4913
摘要： A flexible computing fabric and a method of forming thereof. The flexible computing fabric includes an electronic substrate including one or more channels and including at least two ends. At least one computational element is mounted on the electronic substrate between the two ends and at least one functional element is mounted on the electronic substrate between the two ends. The channels form an interconnect between the elements. In addition, the electronic substrate is flexible and exhibits a flexural modulus in the range of 0.1 GPa to 30 GPa.
摘要翻译：一种灵活的计算结构及其形成方法。柔性计算结构包括包括一个或多个通道并且包括至少两个端部的电子基板。至少一个计算元件安装在两端之间的电子基板上，并且至少一个功能元件安装在两端之间的电子基板上。通道形成元件之间的互连。此外，电子基板是柔性的并且具有在0.1GPa至30GPa范围内的挠曲模量。

4. 发明申请

US20160329438A1 NANOWIRE-BASED MECHANICAL SWITCHING DEVICE 有权
标题翻译：基于纳米级的机械开关装置
公开(公告)号：US20160329438A1
公开(公告)日：2016-11-10
申请号：US15151381
申请日：2016-05-10
申请人： Chytra Pawashe , Kevin Lin , Anurag Chaudhry , Raseong Kim , Seiyon Kim , Kelin Kuhn , Sasikanth Manipatruni , Rafael Rios , Ian A. Young
发明人： Chytra Pawashe , Kevin Lin , Anurag Chaudhry , Raseong Kim , Seiyon Kim , Kelin Kuhn , Sasikanth Manipatruni , Rafael Rios , Ian A. Young
IPC分类号： H01L29/84 , H01H59/00 , H01L29/161 , H01L29/06 , H01L29/04
CPC分类号： H01L29/84 , B82Y10/00 , H01H1/0094 , H01H9/0271 , H01H59/0009 , H01L29/045 , H01L29/0673 , H01L29/161
摘要： Nanowire-based mechanical switching devices are described. For example, a nanowire relay includes a nanowire disposed in a void disposed above a substrate. The nanowire has an anchored portion and a suspended portion. A first gate electrode is disposed adjacent the void, and is spaced apart from the nanowire. A first conductive region is disposed adjacent the first gate electrode and adjacent the void, and is spaced apart from the nanowire.
摘要翻译：描述了基于纳米线的机械开关装置。例如，纳米线继电器包括布置在衬底上方的空隙中的纳米线。纳米线具有锚固部分和悬挂部分。第一栅电极邻近空隙设置，并与纳米线隔开。第一导电区域邻近第一栅电极设置并邻近空隙，并与纳米线隔开。

5. 发明申请

US20160322480A1 TUNNELING FIELD EFFECT TRANSISTORS (TFETS) FOR CMOS ARCHITECTURES AND APPROACHES TO FABRICATING N-TYPE AND P-TYPE TFETS 审中-公开
公开(公告)号：US20160322480A1
公开(公告)日：2016-11-03
申请号：US15209552
申请日：2016-07-13
申请人： Roza Kotlyar , Stephen M. Cea , Gilbert Dewey , Benjamin Chu-Kung , Uygar E. Avci , Rafael Rios , Anurag Chaudhry , Thomas D. Linton, JR. , Ian A. Young , Kelin J. Kuhn
发明人： Roza Kotlyar , Stephen M. Cea , Gilbert Dewey , Benjamin Chu-Kung , Uygar E. Avci , Rafael Rios , Anurag Chaudhry , Thomas D. Linton, JR. , Ian A. Young , Kelin J. Kuhn
IPC分类号： H01L29/66 , H01L29/06 , H01L29/165 , H01L27/092 , H01L29/161 , H01L29/10 , H01L29/20 , H01L29/04 , H01L29/786 , H01L29/423
CPC分类号： H01L29/66977 , H01L27/092 , H01L29/045 , H01L29/0676 , H01L29/068 , H01L29/1054 , H01L29/16 , H01L29/161 , H01L29/165 , H01L29/20 , H01L29/24 , H01L29/267 , H01L29/42392 , H01L29/7391 , H01L29/7842 , H01L29/785 , H01L29/78603 , H01L29/78642 , H01L29/78684 , H01L29/78696
摘要： Tunneling field effect transistors (TFETs) for CMOS architectures and approaches to fabricating N-type and P-type TFETs are described. For example, a tunneling field effect transistor (TFET) includes a homojunction active region disposed above a substrate. The homojunction active region includes a relaxed Ge or GeSn body having an undoped channel region therein. The homojunction active region also includes doped source and drain regions disposed in the relaxed Ge or GeSn body, on either side of the channel region. The TFET also includes a gate stack disposed on the channel region, between the source and drain regions. The gate stack includes a gate dielectric portion and gate electrode portion.

6. 发明申请

US20160300612A1 HYBRID MEMORY AND MTJ BASED MRAM BIT-CELL AND ARRAY 审中-公开
标题翻译：混合存储器和基于MTJ的MRAM位单元和阵列
公开(公告)号：US20160300612A1
公开(公告)日：2016-10-13
申请号：US15036761
申请日：2013-12-24
申请人： Sasikanth MANIPATRUNI , Ian A. YOUNG , INTEL CORPORATION
发明人： Sasikanth MANIPATRUNI , Ian A. YOUNG
IPC分类号： G11C14/00 , G11C11/16 , H01L27/108 , H01L43/08 , H01L43/10 , H01L43/12 , G11C13/00 , H01L27/22
CPC分类号： G11C14/0036 , B82Y10/00 , G11C11/161 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C13/0004 , G11C13/0011 , G11C13/0069 , G11C14/0018 , G11C14/0045 , H01L27/10832 , H01L27/1087 , H01L27/228 , H01L43/08 , H01L43/10 , H01L43/12 , H04L9/0897
摘要： Described is an apparatus for a hybrid eDRAM and MRAM memory cell comprising: a capacitor having a first terminal and a second terminal; a first transistor having a gate terminal coupled to a first word line (WL), a source/drain terminal coupled to bit line (BL), and drain/source terminal coupled to the first terminal of the capacitor; a resistive memory element having a first terminal and a second terminal, the first terminal of the resistive memory element device coupled to the first terminal of the capacitor; and a second transistor having a gate terminal coupled to a second WL, a source/drain terminal coupled to source line (SL), and drain/source terminal coupled to the second terminal of the resistive memory element device.
摘要翻译：描述了一种用于混合eDRAM和MRAM存储单元的装置，包括：具有第一端子和第二端子的电容器; 第一晶体管，其具有耦合到第一字线（WL）的栅极端子，耦合到位线（BL）的源极/漏极端子以及耦合到所述电容器的所述第一端子的漏极/源极端子; 具有第一端子和第二端子的电阻性存储元件，所述电阻式存储元件器件的所述第一端子耦合到所述电容器的第一端子; 以及第二晶体管，其具有耦合到第二WL的栅极端子，耦合到源极线（SL）的源极/漏极端子以及耦合到所述电阻性存储器件器件的所述第二端子的漏极/源极端子。

7. 发明申请

US20160182023A1 APPARATUSES, METHODS, AND SYSTEMS FOR DENSE CIRCUITRY USING TUNNEL FIELD EFFECT TRANSISTORS 有权
标题翻译：使用隧道场效应晶体管的DENSE电路的装置，方法和系统
公开(公告)号：US20160182023A1
公开(公告)日：2016-06-23
申请号：US14575962
申请日：2014-12-18
申请人： Daniel H. Morris , Uygar E. Avci , Rafael Rios , Ian A. Young
发明人： Daniel H. Morris , Uygar E. Avci , Rafael Rios , Ian A. Young
IPC分类号： H03K3/356 , G11C11/419
CPC分类号： G11C11/419 , G11C5/145 , G11C11/412 , H01L27/1104 , H03K3/356104
摘要： Embodiments include apparatuses, methods, and systems for a circuit to shift a voltage level. The circuit may include a first inverter that includes a first transistor coupled to pass a low voltage signal and a second inverter coupled to receive the low voltage signal. The circuit may further include a second transistor coupled to receive the low voltage signal from the second inverter to serve as a feedback device and produce a high voltage signal. In embodiments, the first transistor conducts asymmetrically to prevent crossover of the high voltage signal into the low voltage domain. A low voltage memory array is also described. In embodiments, the circuit to shift a voltage level may assist communication between a logic component including the low voltage memory array of a low voltage domain and a logic component of a high voltage domain. Additional embodiments may also be described.
摘要翻译：实施例包括用于移位电压电平的电路的装置，方法和系统。电路可以包括第一反相器，其包括耦合以传递低电压信号的第一晶体管和耦合以接收低电压信号的第二反相器。电路还可以包括第二晶体管，其被耦合以从第二反相器接收低电压信号，以用作反馈装置并产生高电压信号。在实施例中，第一晶体管不对称地导通，以防止高电压信号到低电压域的交叉。还描述了低电压存储器阵列。在实施例中，用于移位电压电平的电路可以有助于包括低电压域的低电压存储器阵列和高电压域的逻辑分量的逻辑组件之间的通信。还可以描述另外的实施例。

8. 发明申请

US20150341036A1 HIGH SPEED PRECESSIONALLY SWITCHED MAGNETIC LOGIC 审中-公开
标题翻译：高速预切换磁性逻辑
公开(公告)号：US20150341036A1
公开(公告)日：2015-11-26
申请号：US14813934
申请日：2015-07-30
申请人： Sasikanth Manipatruni , Dmitri E. Nikonov , Ian A. Young
发明人： Sasikanth Manipatruni , Dmitri E. Nikonov , Ian A. Young
IPC分类号： H03K19/16 , H03K17/80
CPC分类号： H03K19/16 , G11C11/16 , G11C11/161 , H01F10/3268 , H03K17/80
摘要： High speed precessionally switched magnetic logic devices and architectures are described. In a first example, a magnetic logic device includes an input electrode having a first nanomagnet and an output electrode having a second nanomagnet. The spins of the second nanomagnet are non-collinear with the spins of the first nanomagnet. A channel region and corresponding ground electrode are disposed between the input and output electrodes. In a second example, a magnetic logic device includes an input electrode having an in-plane nanomagnet and an output electrode having a perpendicular magnetic anisotropy (PMA) magnet. A channel region and corresponding ground electrode are disposed between the input and output electrodes.
摘要翻译：描述了高速开关磁逻辑器件和架构。在第一示例中，磁逻辑器件包括具有第一纳米磁体的输入电极和具有第二纳米磁体的输出电极。第二纳米磁体的自旋与第一纳米磁体的自旋不共线。沟道区域和对应的接地电极设置在输入和输出电极之间。在第二示例中，磁逻辑器件包括具有面内纳米磁体的输入电极和具有垂直磁各向异性（PMA）磁体的输出电极。沟道区域和对应的接地电极设置在输入和输出电极之间。

9. 发明授权

US09136848B2 High speed precessionally switched magnetic logic 有权
公开(公告)号：US09136848B2
公开(公告)日：2015-09-15
申请号：US14659349
申请日：2015-03-16
申请人： Sasikanth Manipatruni , Dmitri E. Nikonov , Ian A. Young
发明人： Sasikanth Manipatruni , Dmitri E. Nikonov , Ian A. Young
IPC分类号： H03K19/16 , H03K17/80
CPC分类号： H03K19/16 , G11C11/16 , G11C11/161 , H01F10/3268 , H03K17/80
摘要： High speed precessionally switched magnetic logic devices and architectures are described. In a first example, a magnetic logic device includes an input electrode having a first nanomagnet and an output electrode having a second nanomagnet. The spins of the second nanomagnet are non-collinear with the spins of the first nanomagnet. A channel region and corresponding ground electrode are disposed between the input and output electrodes. In a second example, a magnetic logic device includes an input electrode having an in-plane nanomagnet and an output electrode having a perpendicular magnetic anisotropy (PMA) magnet. A channel region and corresponding ground electrode are disposed between the input and output electrodes.

10. 发明申请

US20140269034A1 INTEGRATED CAPACITOR BASED POWER DISTRIBUTION 有权
标题翻译：基于集成电容器的功率分配
公开(公告)号：US20140269034A1
公开(公告)日：2014-09-18
申请号：US13976053
申请日：2013-03-15
申请人： Sasikanth Manipatruni , Dmitri E. Nikonov , Ian A. Young
发明人： Sasikanth Manipatruni , Dmitri E. Nikonov , Ian A. Young
IPC分类号： G11C11/16
CPC分类号： G11C11/1697 , G11C5/14 , G11C11/16
摘要： An embodiment provides power (having low voltage, high current, and high current density) to ultra low voltage non-CMOS based devices using a distributed capacitor that is integrated onto the same chip as the non-CMOS devices. For example, an embodiment provides a spin logic gate adjacent dielectric material and first and second plates of a capacitor. The capacitor discharges low voltage/high current to the spin logic gate using a step down switched mode power supply that charges numerous capacitors during one clock cycle (using a switching element configured in a first orientation) and discharges power from the capacitors during the opposite clock cycle (using the switching element configured in a second orientation). The capacitors discharge the current out of plane and to the spin logic devices without having to traverse long power dissipating interconnect paths. Other embodiments are described herein.
摘要翻译：实施例使用集成到与非CMOS器件相同的芯片上的分布式电容器向超低压非CMOS器件提供功率（具有低电压，高电流和高电流密度）。例如，实施例提供了一个自旋逻辑门，邻近电介质材料和电容器的第一和第二平板。电容器使用降压开关模式电源将低电压/高电流放电到自旋逻辑门，该降压开关模式电源在一个时钟周期（使用以第一方向配置的开关元件）充电多个电容器，并在相对时钟内从电容器放电循环（使用以第二方向配置的开关元件）。电容器将电流从平面外转移到自旋逻辑器件，而不必横穿长的功率耗散互连路径。本文描述了其它实施例。

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