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1. 发明授权

US07309406B2 Method and apparatus for plating and polishing semiconductor substrate 有权
标题翻译：电镀和抛光半导体衬底的方法和装置
公开(公告)号：US07309406B2
公开(公告)日：2007-12-18
申请号：US10946703
申请日：2004-09-21
申请人： Homayoun Talieh , Cyprian Emeka Uzoh
发明人： Homayoun Talieh , Cyprian Emeka Uzoh
IPC分类号： C25F3/30
CPC分类号： B24B37/16 , C25D5/06 , C25D5/22 , C25D7/123 , C25D17/001 , C25D17/14 , C25F7/00 , H01L21/3212
摘要： The present invention provides a method and apparatus that plates/deposits a conductive material on a semiconductor substrate and then polishes the same substrate. This is achieved by providing multiple chambers in a single apparatus, where one chamber can be used for plating/depositing the conductive material and another chamber can be used for polishing the semiconductor substrate. The plating/depositing process can be performed using brush plating or electro chemical mechanical deposition and the polishing process can be performed using electropolishing or chemical mechanical polishing. The present invention further provides a method and apparatus for intermittently applying the conductive material to the semiconductor substrate and also intermittently polishing the substrate when such conductive material is not being applied to the substrate. Furthermore, the present invention provides a method and apparatus that plates/deposits and/or polishes a conductive material and improves the electrolyte mass transfer properties on a substrate using a novel anode assembly.
摘要翻译：本发明提供一种在半导体衬底上沉积/沉积导电材料然后抛光相同衬底的方法和装置。这通过在单个设备中提供多个室来实现，其中一个室可以用于电镀/沉积导电材料，并且另一个室可以用于抛光半导体衬底。电镀/沉积工艺可以使用刷镀或电化学机械沉积进行，并且可以使用电抛光或化学机械抛光进行抛光工艺。本发明还提供了一种用于将导电材料间歇地施加到半导体衬底的方法和装置，并且当这种导电材料未被施加到衬底时也间歇地抛光衬底。此外，本发明提供了一种使用新型阳极组件对导电材料进行平板/沉积和/或抛光并改善基板上的电解质传质性质的方法和装置。

2. 发明授权

US06630059B1 Workpeice proximity plating apparatus 失效
标题翻译：工件接近电镀设备
公开(公告)号：US06630059B1
公开(公告)日：2003-10-07
申请号：US09483095
申请日：2000-01-14
申请人： Cyprian Emeka Uzoh , Homayoun Talieh , Bulent Basol , Douglas W. Young
发明人： Cyprian Emeka Uzoh , Homayoun Talieh , Bulent Basol , Douglas W. Young
IPC分类号： C25D1700
CPC分类号： B24B37/20 , B24B37/046 , B24B37/24 , B24B37/26 , C25D5/06 , C25D17/001 , C25D17/14 , C25F7/00 , H01L21/2885 , H01L21/76877
摘要： The present invention relates to methods and apparatus for plating a conductive material on a semiconductor substrate by rotating pad or blade type objects in close proximity to the substrate, thereby eliminating/reducing dishing and voids. This is achieved by providing pad or blade type objects mounted on cylindrical anodes or rollers and applying the conductive material to the substrate using the electrolyte solution disposed on or through the pads, or on the blades. In one embodiment of the invention, the pad or blade type objects are mounted on the cylindrical anodes and rotated about a first axis while the workpiece may be stationary or rotate about a second axis, and metal from the electrolyte solution is deposited on the workpiece when a potential difference is applied between the workpiece and the anode. In another embodiment of the present invention, the plating apparatus includes an anode plate spaced apart from the cathode workpiece. Upon application of power to the anode plate and the cathode workpiece, the electrolyte solution disposed in the plating apparatus is used to deposit the conductive material on the workpiece surface using cylindrical rollers having the pad or blade type objects.
摘要翻译：本发明涉及通过旋转靠近基板的垫片或刀片型物体来在半导体衬底上镀覆导电材料的方法和装置，从而消除/减少凹陷和空隙。这通过提供安装在圆柱形阳极或辊子上的垫片或刀片型物体，并使用设置在垫片上或穿过垫片上的电解质溶液将导电材料施加到衬底来实现。在本发明的一个实施例中，衬垫或刀片型物体安装在圆柱形阳极上并围绕第一轴线旋转，同时工件可以是静止的或围绕第二轴线旋转，并且来自电解质溶液的金属沉积在工件上，在工件和阳极之间施加电位差。在本发明的另一实施例中，电镀装置包括与阴极工件间隔开的阳极板。在向阳极板和阴极工件施加电力时，使用设置在电镀装置中的电解液将导电材料沉积在工件表面上，使用具有焊盘或刀片型物体的圆柱形辊。

3. 发明授权

US06355153B1 Chip interconnect and packaging deposition methods and structures 有权
标题翻译：芯片互连和封装沉积方法和结构
公开(公告)号：US06355153B1
公开(公告)日：2002-03-12
申请号：US09398258
申请日：1999-09-17
申请人： Cyprian Emeka Uzoh , Homayoun Talieh , Bulent Basol
发明人： Cyprian Emeka Uzoh , Homayoun Talieh , Bulent Basol
IPC分类号： C25D500
CPC分类号： C25D5/00 , C23C18/1608 , C23C18/165 , C23C18/1651 , C23C18/1653 , C23C18/1696 , C23C18/1848 , C23C18/31 , C25D5/02 , C25D5/10 , C25D5/22 , C25D5/34 , H01L21/2885 , H01L21/7684 , H01L21/76843 , H01L21/76855 , H01L21/76865 , H01L21/76871 , H01L21/76874 , H01L21/76876 , H01L21/76879 , H01L21/76885 , H01L24/11 , H01L2221/1089 , H01L2224/13099 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01016 , H01L2924/01019 , H01L2924/01021 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01041 , H01L2924/01042 , H01L2924/01044 , H01L2924/01045 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/01057 , H01L2924/0106 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/14 , H01L2924/3011
摘要： The present invention relates to a method for fabricating high performance chip interconnects and packages by providing methods for depositing a conductive material in cavities of a substrate in a more efficient and time saving manner. This is accomplished by selectively removing portions of a seed layer from a top surface of a substrate and then depositing a conductive material in the cavities of the substrate, where portions of the seed layer remains in the cavities. Another method includes forming an oxide layer on the top surface of the substrate such that the conductive material can be deposited in the cavities without the material being formed on the top surface of the substrate. The present invention also discloses methods for forming multi-level interconnects and the corresponding structures.
摘要翻译：本发明涉及一种制造高性能芯片互连和封装的方法，该方法通过提供以更高效和省时的方式在衬底的空腔中沉积导电材料的方法。这是通过从衬底的顶表面选择性地去除种子层的部分，然后在衬底的空腔中沉积导电材料，其中种子层的部分保留在空腔中。另一种方法包括在衬底的顶表面上形成氧化物层，使得导电材料可以沉积在空腔中，而不会在衬底的顶表面上形成材料。本发明还公开了用于形成多级互连的方法和相应的结构。

4. 发明授权

US07572354B2 Electrochemical processing of conductive surface 有权
标题翻译：导电表面的电化学处理
公开(公告)号：US07572354B2
公开(公告)日：2009-08-11
申请号：US11445594
申请日：2006-06-01
申请人： Cyprian Emeka Uzoh , Homayoun Talieh , Bulent Basol , Douglas W. Young
发明人： Cyprian Emeka Uzoh , Homayoun Talieh , Bulent Basol , Douglas W. Young
IPC分类号： C25B9/00 , C25D7/00
CPC分类号： B24B37/20 , B24B37/046 , B24B37/24 , B24B37/26 , C25D5/06 , C25D17/001 , C25D17/14 , C25F7/00 , H01L21/2885 , H01L21/76877
摘要： The present invention relates to methods and apparatus for plating a conductive material on a semiconductor substrate by rotating pad or blade type objects in close proximity to the substrate, thereby eliminating/reducing dishing and voids. This is achieved by providing pad or blade type objects mounted on cylindrical anodes or rollers and applying the conductive material to the substrate using the electrolyte solution disposed on or through the pads, or on the blades. In one embodiment of the invention, the pad or blade type objects are mounted on the cylindrical anodes and rotated about a first axis while the workpiece may be stationary or rotate about a second axis, and metal from the electrolyte solution is deposited on the workpiece when a potential difference is applied between the workpiece and the anode. In another embodiment of the present invention, the plating apparatus includes an anode plate spaced apart from the cathode workpiece. Upon application of power to the anode plate and the cathode workpiece, the electrolyte solution disposed in the plating apparatus is used to deposit the conductive material on the workpiece surface using cylindrical rollers having the pad or blade type objects.
摘要翻译：本发明涉及通过旋转靠近基板的垫片或刀片型物体来在半导体衬底上镀覆导电材料的方法和装置，从而消除/减少凹陷和空隙。这通过提供安装在圆柱形阳极或辊子上的垫片或刀片型物体，并使用设置在垫片上或穿过垫片上的电解质溶液将导电材料施加到衬底来实现。在本发明的一个实施例中，衬垫或刀片型物体安装在圆柱形阳极上并围绕第一轴线旋转，同时工件可以是静止的或围绕第二轴线旋转，并且来自电解质溶液的金属沉积在工件上，在工件和阳极之间施加电位差。在本发明的另一实施例中，电镀装置包括与阴极工件间隔开的阳极板。在向阳极板和阴极工件施加电力时，使用设置在电镀装置中的电解液将导电材料沉积在工件表面上，使用具有焊盘或刀片型物体的圆柱形辊。

5. 发明授权

US06905588B2 Packaging deposition methods 失效
标题翻译：包装沉积方法
公开(公告)号：US06905588B2
公开(公告)日：2005-06-14
申请号：US09905335
申请日：2001-07-13
申请人： Cyprian Emeka Uzoh , Homayoun Talieh , Bulent Basol
发明人： Cyprian Emeka Uzoh , Homayoun Talieh , Bulent Basol
IPC分类号： C25D3/02 , C23C28/00 , C25D5/10 , C25D7/12 , H01L21/288 , H01L21/304 , H01L21/60 , H01L21/768 , C25D5/00 , B23H3/00
CPC分类号： C25D5/00 , C23C18/1608 , C23C18/165 , C23C18/1651 , C23C18/1653 , C23C18/1696 , C23C18/1848 , C23C18/31 , C25D5/02 , C25D5/10 , C25D5/22 , C25D5/34 , H01L21/2885 , H01L21/7684 , H01L21/76843 , H01L21/76855 , H01L21/76865 , H01L21/76871 , H01L21/76874 , H01L21/76876 , H01L21/76879 , H01L21/76885 , H01L24/11 , H01L2221/1089 , H01L2224/13099 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01016 , H01L2924/01019 , H01L2924/01021 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01041 , H01L2924/01042 , H01L2924/01044 , H01L2924/01045 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/01057 , H01L2924/0106 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/14 , H01L2924/3011
摘要： The present invention relates to a method for fabricating high performance chip interconnects and packages by providing methods for depositing a conductive material in cavities of a substrate in a more efficient and time saving manner. This is accomplished by selectively removing portions of a seed layer from a top surface of a substrate and then depositing a conductive material in the cavities of the substrate, where portions of the seed layer remains in the cavities. Another method includes forming an oxide layer on the top surface of the substrate such that the conductive material can be deposited in the cavities without the material being formed on the top surface of the substrate. The present invention also discloses methods for forming multi-level interconnects and the corresponding structures.
摘要翻译：本发明涉及一种制造高性能芯片互连和封装的方法，该方法通过提供以更高效和省时的方式在衬底的空腔中沉积导电材料的方法。这是通过从衬底的顶表面选择性地去除种子层的部分，然后在衬底的空腔中沉积导电材料，其中种子层的部分保留在空腔中。另一种方法包括在衬底的顶表面上形成氧化物层，使得导电材料可以沉积在空腔中，而不会在衬底的顶表面上形成材料。本发明还公开了用于形成多级互连的方法和相应的结构。

6. 发明授权

US06797132B2 Apparatus for plating and polishing a semiconductor workpiece 失效
标题翻译：用于电镀和抛光半导体工件的装置
公开(公告)号：US06797132B2
公开(公告)日：2004-09-28
申请号：US09941360
申请日：2001-08-28
申请人： Homayoun Talieh , Cyprian Emeka Uzoh
发明人： Homayoun Talieh , Cyprian Emeka Uzoh
IPC分类号： C25D1700
CPC分类号： B24B37/16 , C25D5/06 , C25D5/22 , C25D7/123 , C25D17/001 , C25D17/14 , C25F7/00 , H01L21/3212
摘要： The present invention provides a method and apparatus that plates/deposits a conductive material on a semiconductor substrate and then polishes the same substrate. This is achieved by providing multiple chambers in a single apparatus, where one chamber can be used for plating/depositing the conductive material and another chamber can be used for polishing the semiconductor substrate. The plating/depositing process can be performed using brush plating or electro chemical mechanical deposition and the polishing process can be performed using electropolishing or chemical mechanical polishing. The present invention further provides a method and apparatus for intermittently applying the conductive material to the semiconductor substrate and also intermittently polishing the substrate when such conductive material is not being applied to the substrate. Furthermore, the present invention provides a method and apparatus that plates/deposits and/or polishes a conductive material and improves the electrolyte mass transfer properties on a substrate using a novel anode assembly.
摘要翻译：本发明提供一种在半导体衬底上沉积/沉积导电材料然后抛光相同衬底的方法和装置。这通过在单个设备中提供多个室来实现，其中一个室可以用于电镀/沉积导电材料，并且另一个室可以用于抛光半导体衬底。电镀/沉积工艺可以使用刷镀或电化学机械沉积进行，并且可以使用电抛光或化学机械抛光进行抛光工艺。本发明还提供了一种用于将导电材料间歇地施加到半导体衬底的方法和装置，并且当这种导电材料未被施加到衬底时也间歇地抛光衬底。此外，本发明提供了一种使用新型阳极组件对导电材料进行平板/沉积和/或抛光并改善基板上的电解质传质性质的方法和装置。

7. 发明授权

US06328872B1 Method and apparatus for plating and polishing a semiconductor substrate 有权
标题翻译：电镀和抛光半导体衬底的方法和装置
公开(公告)号：US06328872B1
公开(公告)日：2001-12-11
申请号：US09285621
申请日：1999-04-03
申请人： Homayoun Talieh , Cyprian Emeka Uzoh
发明人： Homayoun Talieh , Cyprian Emeka Uzoh
IPC分类号： C25D1700
CPC分类号： B24B37/16 , C25D5/06 , C25D5/22 , C25D7/123 , C25D17/001 , C25D17/14 , C25F7/00 , H01L21/3212
摘要： The present invention provides a method and apparatus that plates/deposits a conductive material on a semiconductor substrate and then polishes the same substrate. This is achieved by providing multiple chambers in a single apparatus, where one chamber can be used for plating/depositing the conductive material and another chamber can be used for polishing the semiconductor substrate. The plating/depositing process can be performed using brush plating or electro chemical mechanical deposition and the polishing process can be performed using electropolishing or chemical mechanical polishing. The present invention further provides a method and apparatus for intermittently applying the conductive material to the semiconductor substrate and also intermittently polishing the substrate when such conductive material is not being applied to the substrate. Furthermore, the present invention provides a method and apparatus that plates/deposits and/or polishes a conductive material and improves the electrolyte mass transfer properties on a substrate using a novel anode assembly.
摘要翻译：本发明提供一种在半导体衬底上沉积/沉积导电材料然后抛光相同衬底的方法和装置。这通过在单个设备中提供多个室来实现，其中一个室可以用于电镀/沉积导电材料，并且另一个室可以用于抛光半导体衬底。电镀/沉积工艺可以使用刷镀或电化学机械沉积进行，并且可以使用电抛光或化学机械抛光进行抛光工艺。本发明还提供了一种用于将导电材料间歇地施加到半导体衬底的方法和装置，并且当这种导电材料未被施加到衬底时也间歇地抛光衬底。此外，本发明提供了一种使用新型阳极组件对导电材料进行平板/沉积和/或抛光并改善基板上的电解质传质性质的方法和装置。

8. 发明授权

US07147766B2 Chip interconnect and packaging deposition methods and structures 有权
公开(公告)号：US07147766B2
公开(公告)日：2006-12-12
申请号：US10407892
申请日：2003-04-04
申请人： Cyprian Emeka Uzoh , Homayoun Talieh , Bulent Basol
发明人： Cyprian Emeka Uzoh , Homayoun Talieh , Bulent Basol
IPC分类号： C25D5/02 , C25D5/48 , C25D5/52
CPC分类号： C25D5/00 , C23C18/1608 , C23C18/165 , C23C18/1651 , C23C18/1653 , C23C18/1696 , C23C18/1848 , C23C18/31 , C25D5/02 , C25D5/10 , C25D5/22 , C25D5/34 , H01L21/2885 , H01L21/7684 , H01L21/76843 , H01L21/76855 , H01L21/76865 , H01L21/76871 , H01L21/76874 , H01L21/76876 , H01L21/76879 , H01L21/76885 , H01L24/11 , H01L2221/1089 , H01L2224/13099 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01016 , H01L2924/01019 , H01L2924/01021 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01041 , H01L2924/01042 , H01L2924/01044 , H01L2924/01045 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/01057 , H01L2924/0106 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/14 , H01L2924/3011
摘要： The present invention relates to a method for fabricating high performance chip interconnects and packages by providing methods for depositing a conductive material in cavities of a substrate in a more efficient and time saving manner. This is accomplished by selectively removing portions of a seed layer from a top surface of a substrate and then depositing a conductive material in the cavities of the substrate, where portions of the seed layer remains in the cavities. Another method includes forming an oxide layer on the top surface of the substrate such that the conductive material can be deposited in the cavities without the material being formed on the top surface of the substrate. The present invention also discloses methods for forming multi-level interconnects and the corresponding structures.

9. 发明授权

US06837979B2 Method and apparatus for depositing and controlling the texture of a thin film 失效
标题翻译：用于沉积和控制薄膜纹理的方法和装置
公开(公告)号：US06837979B2
公开(公告)日：2005-01-04
申请号：US10165673
申请日：2002-06-06
申请人： Cyprian Emeka Uzoh , Homayoun Talieh
发明人： Cyprian Emeka Uzoh , Homayoun Talieh
IPC分类号： B24B37/04 , B24B37/20 , B24B37/22 , B24B37/24 , B24B37/26 , C25D5/00 , C25D5/02 , C25D5/06 , C25D5/22 , C25D7/12 , C25D17/14 , C25F7/00 , H01L21/00 , H01L21/288 , H01L21/321 , H01L21/768 , H01L23/532 , C23C14/34 , C23C16/00 , H01L21/44 , C25C5/52
CPC分类号： H01L23/53238 , B24B37/042 , B24B37/20 , B24B37/22 , B24B37/24 , B24B37/26 , C25D5/00 , C25D5/02 , C25D5/06 , C25D5/22 , C25D5/50 , C25D7/123 , C25D17/14 , C25D21/02 , C25F7/00 , H01L21/2885 , H01L21/3212 , H01L21/6715 , H01L21/76838 , H01L21/76877 , H01L2924/0002 , H01L2924/09701 , H01L2924/00
摘要： The present invention provides a method and apparatus for plating a conductive material to a substrate and also modifying the physical properties of a conductive film while the substrate is being plated. The present invention further provides a method and apparatus that plates a conductive material on a workpiece surface in a “proximity” plating manner while a pad type material or other fixed feature is making contact with the workpiece surface in a “cold worked” manner. In this manner, energy stored in the cold worked regions of the plated layer is used to accelerate and enhance micro-structural recovery and growth. Thus, large grain size is obtained in the plated material at a lower annealing temperature and a shorter annealing time.
摘要翻译：本发明提供了一种用于将导电材料镀覆到基底上的方法和装置，并且还改善了在衬底被电镀时导电膜的物理性质。本发明还提供了一种方法和装置，其以“接近”电镀方式在工件表面上平板化导电材料，同时衬垫型材料或其它固定特征以“冷加工”方式与工件表面接触。以这种方式，存储在镀层的冷加工区域中的能量用于加速和增强微结构回收和生长。因此，在较低的退火温度和较短的退火时间下，在镀覆材料中获得大的晶粒尺寸。

10. 发明授权

US06692588B1 Method and apparatus for simultaneously cleaning and annealing a workpiece 失效
标题翻译：同时清洁和退火工件的方法和装置
公开(公告)号：US06692588B1
公开(公告)日：2004-02-17
申请号：US09351868
申请日：1999-07-12
申请人： Cyprian Emeka Uzoh , Homayoun Talieh
发明人： Cyprian Emeka Uzoh , Homayoun Talieh
IPC分类号： B08B310
CPC分类号： H01L21/324 , C25D5/50 , H01L21/288 , H01L21/321 , H01L21/67051 , H01L21/67109 , Y10S438/906
摘要： The present invention is directed to a method and apparatus for simultaneously cleaning and annealing a plated semiconductor workpiece. A chamber for simultaneously cleaning and annealing a semiconductor workpiece is provided herein. The method according to the present invention includes the steps rinsing the workpiece with mineral acids and DI water, then simultaneously cleaning/annealing the workpiece with heated deoxygenated DI water. By this present method, tool cross contamination by way of plated metal is greatly reduced, and also grain recovery and grain growth at room temperature is greatly accelerated. Thus, the annealing time of grain growth is dramatically reduced using the present method and apparatus.
摘要翻译：本发明涉及同时清洗和退火镀覆的半导体工件的方法和装置。本文提供了用于同时清洁和退火半导体工件的腔室。根据本发明的方法包括用无机酸和去离子水冲洗工件的步骤，然后用加热的脱氧去离子水同时清洗/退火工件。通过本方法，大大减少了通过电镀金属的工具交叉污染，并且大大加速了室温下的晶粒恢复和晶粒生长。因此，使用本方法和装置，晶粒生长的退火时间显着减少。

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