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1. 发明申请

US20100246739A1 METHOD FOR MEASURING PHASE LOCKED LOOP BANDWIDTH PARAMETERS FOR HIGH-SPEED SERIAL LINKS 有权
标题翻译：用于测量高速串行链路的相位锁定环带宽度参数的方法
公开(公告)号：US20100246739A1
公开(公告)日：2010-09-30
申请号：US12410413
申请日：2009-03-24
申请人： Dongming Lou , Pengfei Hu , Junqiang Shang , Xin Liu
发明人： Dongming Lou , Pengfei Hu , Junqiang Shang , Xin Liu
IPC分类号： H04L7/00
CPC分类号： H03L7/08 , H04L7/033
摘要： A method for measuring a phase locked loop bandwidth parameter for a high-speed serial link includes the steps of initiating a jitter frequency of a clock input of a phase locked loop equal to a reference frequency with a frequency generator, determining a reference jitter amplitude value of a clock output of the phase locked loop with a waveform analyzer at the reference frequency, the reference jitter amplitude value being a function of a time interval error jitter trend of the clock output at the reference frequency; and adjusting the jitter frequency of the clock input with the frequency generator until an adjusted jitter amplitude value of the clock output reaches a goal value as determined by the waveform analyzer, the adjusted jitter amplitude being a function of a time interval error trend of the clock output at the adjusted frequency.
摘要翻译：一种用于测量高速串行链路的锁相环带宽参数的方法包括以下步骤：利用频率发生器启动等于参考频率的锁相环的时钟输入的抖动频率，确定参考抖动振幅值基准频率下的波形分析器的锁相环的时钟输出，参考抖动幅度值是参考频率时钟输出的时间间隔误差抖动趋势的函数; 并且通过频率发生器调整时钟输入的抖动频率，直到时钟输出的经调整的抖动幅度值达到由波形分析器确定的目标值，调整后的抖动幅度是时钟的时间间隔误差趋势的函数以调整频率输出。

2. 发明授权

US08254515B2 Method for measuring phase locked loop bandwidth parameters for high-speed serial links 有权
标题翻译：用于测量高速串行链路的锁相环带宽参数的方法
公开(公告)号：US08254515B2
公开(公告)日：2012-08-28
申请号：US12410413
申请日：2009-03-24
申请人： Dongming Lou , Pengfei Hu , Junqiang Shang , Xin Liu
发明人： Dongming Lou , Pengfei Hu , Junqiang Shang , Xin Liu
IPC分类号： H03D3/24 , H04Q1/20 , H04L23/00
CPC分类号： H03L7/08 , H04L7/033
摘要： A method for measuring a phase locked loop bandwidth parameter for a high-speed serial link includes the steps of initiating a jitter frequency of a clock input of a phase locked loop equal to a reference frequency with a frequency generator; determining a reference jitter amplitude value of a clock output of the phase locked loop with a waveform analyzer at the reference frequency, the reference jitter amplitude value being a function of a time interval error jitter trend of the clock output at the reference frequency; and adjusting the jitter frequency of the clock input with the frequency generator until an adjusted jitter amplitude value of the clock output reaches a goal value as determined by the waveform analyzer, the adjusted jitter amplitude being a function of a time interval error trend of the clock output at the adjusted frequency.
摘要翻译：用于测量高速串行链路的锁相环带宽参数的方法包括以下步骤：利用频率发生器启动等于参考频率的锁相环的时钟输入的抖动频率; 使用参考频率的波形分析器确定锁相环的时钟输出的参考抖动幅度值，参考抖动幅度值是参考频率时钟输出的时间间隔误差抖动趋势的函数; 并且通过频率发生器调整时钟输入的抖动频率，直到时钟输出的经调整的抖动幅度值达到由波形分析器确定的目标值，调整后的抖动幅度是时钟的时间间隔误差趋势的函数以调整频率输出。

3. 发明授权

US08548773B2 High speed chip screening method using delay locked loop 有权
标题翻译：使用延迟锁定环的高速芯片筛选方法
公开(公告)号：US08548773B2
公开(公告)日：2013-10-01
申请号：US12607576
申请日：2009-10-28
申请人： Junqiang Shang , Liang Zhang , Yong Wang , Xin Liu
发明人： Junqiang Shang , Liang Zhang , Yong Wang , Xin Liu
IPC分类号： G06F11/30 , H03L7/06
CPC分类号： G01R31/31718 , G01R31/31725
摘要： A voltage controlled delay line (VCDL) for measuring the maximum speed of a chip includes a first input configured to receive a reference clock signal, a first output configured to output an output clock signal, and a second input configured to receive a phase error signal representing a phase delay between the reference and output clock signals. A register stores a delay code applied by the VCDL to the reference clock signal to delay the reference clock signal to generate the output clock signal. The delay code is adjusted according to the phase error signal until the phase delay is equal to a predetermined value. A second output is coupled to an interface that reads the delay code from the register and outputs the delay code to automated testing equipment when the phase delay is equal to the predetermined value. The outputted delay code corresponds to the maximum chip speed.
摘要翻译：用于测量芯片的最大速度的电压控制延迟线（VCDL）包括被配置为接收参考时钟信号的第一输入，被配置为输出输出时钟信号的第一输出和被配置为接收相位误差信号的第二输入表示参考和输出时钟信号之间的相位延迟。寄存器将由VCDL施加的延迟码存储到参考时钟信号以延迟参考时钟信号以产生输出时钟信号。根据相位误差信号调整延迟码，直到相位延迟等于预定值。当相位延迟等于预定值时，第二输出耦合到从寄存器读取延迟码并将延迟代码输出到自动测试设备的接口。输出的延迟代码对应于最大芯片速度。

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