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1. 发明申请

US20100246739A1 METHOD FOR MEASURING PHASE LOCKED LOOP BANDWIDTH PARAMETERS FOR HIGH-SPEED SERIAL LINKS 有权
标题翻译：用于测量高速串行链路的相位锁定环带宽度参数的方法
公开(公告)号：US20100246739A1
公开(公告)日：2010-09-30
申请号：US12410413
申请日：2009-03-24
申请人： Dongming Lou , Pengfei Hu , Junqiang Shang , Xin Liu
发明人： Dongming Lou , Pengfei Hu , Junqiang Shang , Xin Liu
IPC分类号： H04L7/00
CPC分类号： H03L7/08 , H04L7/033
摘要： A method for measuring a phase locked loop bandwidth parameter for a high-speed serial link includes the steps of initiating a jitter frequency of a clock input of a phase locked loop equal to a reference frequency with a frequency generator, determining a reference jitter amplitude value of a clock output of the phase locked loop with a waveform analyzer at the reference frequency, the reference jitter amplitude value being a function of a time interval error jitter trend of the clock output at the reference frequency; and adjusting the jitter frequency of the clock input with the frequency generator until an adjusted jitter amplitude value of the clock output reaches a goal value as determined by the waveform analyzer, the adjusted jitter amplitude being a function of a time interval error trend of the clock output at the adjusted frequency.
摘要翻译：一种用于测量高速串行链路的锁相环带宽参数的方法包括以下步骤：利用频率发生器启动等于参考频率的锁相环的时钟输入的抖动频率，确定参考抖动振幅值基准频率下的波形分析器的锁相环的时钟输出，参考抖动幅度值是参考频率时钟输出的时间间隔误差抖动趋势的函数; 并且通过频率发生器调整时钟输入的抖动频率，直到时钟输出的经调整的抖动幅度值达到由波形分析器确定的目标值，调整后的抖动幅度是时钟的时间间隔误差趋势的函数以调整频率输出。

2. 发明授权

US08254515B2 Method for measuring phase locked loop bandwidth parameters for high-speed serial links 有权
标题翻译：用于测量高速串行链路的锁相环带宽参数的方法
公开(公告)号：US08254515B2
公开(公告)日：2012-08-28
申请号：US12410413
申请日：2009-03-24
申请人： Dongming Lou , Pengfei Hu , Junqiang Shang , Xin Liu
发明人： Dongming Lou , Pengfei Hu , Junqiang Shang , Xin Liu
IPC分类号： H03D3/24 , H04Q1/20 , H04L23/00
CPC分类号： H03L7/08 , H04L7/033
摘要： A method for measuring a phase locked loop bandwidth parameter for a high-speed serial link includes the steps of initiating a jitter frequency of a clock input of a phase locked loop equal to a reference frequency with a frequency generator; determining a reference jitter amplitude value of a clock output of the phase locked loop with a waveform analyzer at the reference frequency, the reference jitter amplitude value being a function of a time interval error jitter trend of the clock output at the reference frequency; and adjusting the jitter frequency of the clock input with the frequency generator until an adjusted jitter amplitude value of the clock output reaches a goal value as determined by the waveform analyzer, the adjusted jitter amplitude being a function of a time interval error trend of the clock output at the adjusted frequency.
摘要翻译：用于测量高速串行链路的锁相环带宽参数的方法包括以下步骤：利用频率发生器启动等于参考频率的锁相环的时钟输入的抖动频率; 使用参考频率的波形分析器确定锁相环的时钟输出的参考抖动幅度值，参考抖动幅度值是参考频率时钟输出的时间间隔误差抖动趋势的函数; 并且通过频率发生器调整时钟输入的抖动频率，直到时钟输出的经调整的抖动幅度值达到由波形分析器确定的目标值，调整后的抖动幅度是时钟的时间间隔误差趋势的函数以调整频率输出。

3. 发明授权

US08680910B1 Method and apparatus for glitch-free switching of multiple phase clock 有权
标题翻译：多相时钟无毛刺切换的方法和装置
公开(公告)号：US08680910B1
公开(公告)日：2014-03-25
申请号：US12640750
申请日：2009-12-17
申请人： Pengfei Hu , Liang Zhang
发明人： Pengfei Hu , Liang Zhang
IPC分类号： G06F1/04
CPC分类号： G06F1/10 , G11C7/222 , H03K2005/00104 , H03K2005/00241
摘要： A method and apparatus for glitch-free switching of multiple phase clock have been disclosed where switching from one phase to another phase is done step-by-step to avoid generating a glitch.
摘要翻译：已经公开了一种用于多相时钟的无毛刺切换的方法和装置，其中从一个相位切换到另一个相位是逐步完成的，以避免产生毛刺。

4. 发明授权

US07864092B2 Thermo-decoder circuit 有权
标题翻译：热解码电路
公开(公告)号：US07864092B2
公开(公告)日：2011-01-04
申请号：US12367410
申请日：2009-02-06
申请人： Jinfu Chen , Pengfei Hu , Qinghua Yue
发明人： Jinfu Chen , Pengfei Hu , Qinghua Yue
IPC分类号： H03M1/66
CPC分类号： H03M7/165
摘要： A digital-to-thermometer-code converter is disclosed for converting a digital signal into its thermometer-code equivalent. Embodiments of the digital-to-thermometer-code include a binary-to-control signal converter that generates a column control signal and a row control signal based on a binary input signal, and a control signal-to-thermometer-code decoder that includes an array of decoder circuit blocks coupled to receive the column control signal and the row control signal, wherein each of the decoder circuit blocks determine at least one bit of the thermometer-code output signal based on at least a first bit of the column control signal.
摘要翻译：公开了一种数字到温度计代码转换器，用于将数字信号转换为其温度计代码等价物。数字到温度计代码的实施例包括二进制到控制信号转换器，其基于二进制输入信号产生列控制信号和行控制信号，以及控制信号到温度计代码解码器，其包括耦合以接收列控制信号和行控制信号的解码器电路块的阵列，其中每个解码器电路块基于列控制信号的至少第一位确定温度计代码输出信号的至少一位。

5. 发明申请

US20100201557A1 THERMO-DECODER CIRCUIT 有权
标题翻译：热解码器电路
公开(公告)号：US20100201557A1
公开(公告)日：2010-08-12
申请号：US12367410
申请日：2009-02-06
申请人： JINFU CHEN , Pengfei Hu , Qinghua Yue
发明人： JINFU CHEN , Pengfei Hu , Qinghua Yue
IPC分类号： H03M1/66 , H03M1/76
CPC分类号： H03M7/165
摘要： A digital-to-thermometer-code converter is disclosed for converting a digital signal into its thermometer-code equivalent. Embodiments of the digital-to-thermometer-code include a binary-to-control signal converter that generates a column control signal and a row control signal based on a binary input signal, and a control signal-to-thermometer-code decoder that includes an array of decoder circuit blocks coupled to receive the column control signal and the row control signal, wherein each of the decoder circuit blocks determine at least one bit of the thermometer-code output signal based on at least a first bit of the column control signal.
摘要翻译：公开了一种数字到温度计代码转换器，用于将数字信号转换为其温度计代码等价物。数字到温度计代码的实施例包括二进制到控制信号转换器，其基于二进制输入信号产生列控制信号和行控制信号，以及控制信号到温度计代码解码器，其包括耦合以接收列控制信号和行控制信号的解码器电路块的阵列，其中每个解码器电路块基于列控制信号的至少第一位确定温度计代码输出信号的至少一位。

6. 发明授权

US08018289B1 Holdover circuit for phase-lock loop 有权
标题翻译：锁相电路用于锁相环
公开(公告)号：US08018289B1
公开(公告)日：2011-09-13
申请号：US12544201
申请日：2009-08-19
申请人： Pengfei Hu , Song Gao
发明人： Pengfei Hu , Song Gao
IPC分类号： H03L7/00
CPC分类号： H03L7/14 , H03L7/146
摘要： A clock circuit includes a phase-lock loop and a holdover circuit. The phase-lock loop generates an output clock signal having a constant frequency based on a loop filter voltage of a loop filter in the phase-lock loop. The holdover circuit generates and stores a digital value indicating the loop filter voltage and generates an analog voltage signal having the loop filter voltage indicated by the digital value. Further, the holdover circuit maintains the output clock signal at the constant frequency during a holdover of the phase-lock loop by regenerating the loop filter voltage based on the analog voltage signal. Because the analog voltage signal is based on the digital value, the voltage of the loop filter does not decay over time during the holdover of the phase-lock loop. As a result, the output clock signal remains at the constant frequency during the holdover of the phase-lock loop.
摘要翻译：时钟电路包括锁相环和保持电路。相位锁定环路基于锁相环中的环路滤波器的环路滤波器电压产生具有恒定频率的输出时钟信号。保持电路产生并存储指示环路滤波器电压的数字值，并产生具有由数字值表示的环路滤波器电压的模拟电压信号。此外，保持电路在通过基于模拟电压信号再生环路滤波器电压而在锁相环保持期间将输出时钟信号保持在恒定频率。由于模拟电压信号基于数字值，因此在锁相环路保持期间环路滤波器的电压不会随时间衰减。因此，在锁相环路保持期间，输出时钟信号保持恒定的频率。

7. 发明授权

US07598775B2 Phase and frequency detector with zero static phase error 有权
标题翻译：相位和频率检测器具有零静态相位误差
公开(公告)号：US07598775B2
公开(公告)日：2009-10-06
申请号：US12004271
申请日：2007-12-19
申请人： Pengfei Hu , Juan Qiao , Zhongyuan Chang
发明人： Pengfei Hu , Juan Qiao , Zhongyuan Chang
IPC分类号： H03D13/00
CPC分类号： H03D13/00 , H03L7/0891
摘要： A method and circuit for phase and frequency detection having zero static phase error for use in a phase-locked loop system is presented. The phase and frequency detector utilizes a first phase and frequency detector configured to generate first and second pulsed PFD signals. Pulse blocking circuitry is utilized to provide first and second output signals based on the first and second pulsed signals respectively, wherein a time period when both first and second output signals are asserted is substantially reduced from a time period when both first and second pulsed signals are asserted. By reducing the time the first and second output signals are simultaneously asserted, the effects of charge pump current source mismatch are minimized and static phase error is reduced.
摘要翻译：提出了一种用于相位和频率检测的方法和电路，具有用于锁相环系统的零静态相位误差。相位和频率检测器利用被配置为产生第一和第二脉冲PFD信号的第一相位和频率检测器。脉冲阻塞电路被用于分别基于第一和第二脉冲信号提供第一和第二输出信号，其中第一和第二输出信号被断言的时间周期从第一和第二脉冲信号两者的时间段大大减少断言通过减少第一和第二输出信号同时断言的时间，电荷泵电流源失配的影响被最小化，静态相位误差降低。

8. 发明授权

US07786917B2 Digital-to-analog converter 有权
标题翻译：数模转换器
公开(公告)号：US07786917B2
公开(公告)日：2010-08-31
申请号：US12218397
申请日：2008-07-14
申请人： Pengfei Hu , JinFu Chen , Qinghua Yue
发明人： Pengfei Hu , JinFu Chen , Qinghua Yue
IPC分类号： H03M1/66
CPC分类号： H03M1/68 , H03M1/804
摘要： A digital-to-analog converter is disclosed for converting a digital signal into its analog equivalent. The digital-to-analog converter includes a two switches capable of coupling circuit nodes to ground, a scaling capacitor having a capacitance value that equals a unit capacitance value, a first array of capacitors coupled to the first circuit node and a first switching array which couples the first array of capacitors to either ground or a reference voltage depending on the digital values of the least significant bits of the digital word being converted, a second array of capacitors coupled to the second circuit node and a second switching array which couples the second array of capacitors to either ground or the reference voltage depending on the digital values of the most significant bits of the digital word being converted.
摘要翻译：公开了一种数模转换器，用于将数字信号转换为其模拟等效。数模转换器包括能够将电路节点耦合到地的两个开关，具有等于单位电容值的电容值的缩放电容器，耦合到第一电路节点的第一电容器阵列和第一开关阵列，取决于正在转换的数字字的最低有效位的数字值，耦合到第二电路节点的第二电容器阵列和耦合第二电容器的第二开关阵列，将第一阵列电容器耦合到接地或参考电压; 根据要转换的数字字的最高有效位的数字值，电容器阵列到接地或参考电压。

9. 发明申请

US20100007539A1 Digital-to-analog converter 有权
标题翻译：数模转换器
公开(公告)号：US20100007539A1
公开(公告)日：2010-01-14
申请号：US12218397
申请日：2008-07-14
申请人： Pengfei Hu , JinFu Chen , Qinghua Yue
发明人： Pengfei Hu , JinFu Chen , Qinghua Yue
IPC分类号： H03M1/66
CPC分类号： H03M1/68 , H03M1/804
摘要： A digital-to-analog converter is disclosed for converting a digital signal into its analog equivalent. The digital-to-analog converter includes a switch capable of coupling a first and a second circuit node to ground, a scaling capacitor having a capacitance value that equals a unit capacitance value coupled between the first and the second circuit node, a first array of capacitors coupled to the first circuit node, a first switching array configured to selectively couple the first array of capacitors to either ground or a reference voltage depending on the digital values of the least significant bits of the digital word being converted, a second array of capacitors coupled to the second circuit node, and a second switching array configured to selectively couple the second array of capacitors to either ground or the reference voltage depending on the digital values of the most significant bits of the digital word being converted.
摘要翻译：公开了一种数模转换器，用于将数字信号转换为其模拟等效。数模转换器包括能够将第一和第二电路节点耦合到地的开关，具有等于耦合在第一和第二电路节点之间的单位电容值的电容值的缩放电容器，第一阵列耦合到第一电路节点的电容器，第一开关阵列，被配置为根据正被转换的数字字的最低有效位的数字值，将第一阵列电容器选择性地耦合到接地或参考电压;第二电容阵列耦合到第二电路节点，以及第二开关阵列，其被配置为根据所转换的数字字的最高有效位的数字值，将第二电容阵列选择性地耦合到接地或参考电压。

10. 发明申请

US20090160487A1 Phase and frequency detector with zero static phase error 有权
公开(公告)号：US20090160487A1
公开(公告)日：2009-06-25
申请号：US12004271
申请日：2007-12-19
申请人： Pengfei Hu , Juan Qiao , Zhongyuan Chang
发明人： Pengfei Hu , Juan Qiao , Zhongyuan Chang
IPC分类号： H03D13/00
CPC分类号： H03D13/00 , H03L7/0891
摘要： A method and circuit for phase and frequency detection having zero static phase error for use in a phase-locked loop system is presented. The phase and frequency detector utilizes a first phase and frequency detector configured to generate first and second pulsed PFD signals. Pulse blocking circuitry is utilized to provide first and second output signals based on the first and second pulsed signals respectively, wherein a time period when both first and second output signals are asserted is substantially reduced from a time period when both first and second pulsed signals are asserted. By reducing the time the first and second output signals are simultaneously asserted, the effects of charge pump current source mismatch are minimized and static phase error is reduced.

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