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1. 发明授权

KR880000297B1 CENTRAL PROCESSING UNIT FOR EXECUTING INSTRUCTIONS OF VARIABLE LENGTH 失效
公开(公告)号：KR880000297B1
公开(公告)日：1988-03-19
申请号：KR820003773
申请日：1982-08-23
申请人： HITACHI LTD , HITACHI ENG CO LTD
发明人： FUKUNAGA YASUSHI , HIRASAWA KOTARO , IDE JUSHI , BANDOH TADAAKI , MATSUMOTO HIDEKAZU , KATOH TAKESHI
IPC分类号： G06F9/30 , G06F9/318 , G06F9/36
摘要： Instructions are fetched from a cache memory by an instruction fetch unit. A decoder connected to the instruction fetch unit decodes an operand specifier and an operation code. On the basis of the decoded operand specifier, an address calculating unit calculates the address of the specified operand in the cache. An operand fetch unit then retrieves the operand from the cache address calculated. An operation code decoder is provided, in the decoder, to decode the operand from the cache address calculated.

2. 发明专利

DE3689389D1 未知
公开(公告)号：DE3689389D1
公开(公告)日：1994-01-27
申请号：DE3689389
申请日：1986-07-03
申请人： HITACHI LTD , HITACHI ENG CO LTD
发明人： YAMAGUCHI SHINICHIRO , MATSUMOTO HIDEKAZU , BANDOH TADAAKI , NAKANISHI HIROAKI , HIROSE KENZI , KOBAYASHI TAKAO , MIYAZAKI YOSHIHIRO
IPC分类号： G06F9/30 , G06F9/318 , G06F9/44
摘要： A data processor (100) for execution of tagged data and tagless data has a decoder (130) for discriminating whether the data is tagged or tagless one and in case of a tagged data, separates a tag part and uses the remaining part for address computation. The data processor also comprises a unit for evaluating the tag part and a micro program controller (290) for multi-branching in accordance with the evaluation result of the tag part. The tag evaluating unit includes an extender eliminating part (250) for extracting the tag part from data on a data bus (340), a plurality of tag part storing registers (260, 270) for storing the tag part from the eliminating part under the control of the micro program controller, and a tag multi-way jump encoder (292) for generating a tag multi-way jump address to feed it to the controller on the basis of the outputs of the registers and a signal from the micro program controller, thereby enabling tag multi-way jump.

3. 发明专利

DE3176512D1 A VIRTUAL STORAGE DATA PROCESSING SYSTEM 未知
公开(公告)号：DE3176512D1
公开(公告)日：1987-12-10
申请号：DE3176512
申请日：1981-11-16
申请人： HITACHI LTD , HITACHI ENG CO LTD
发明人： FUKUNAGA YASUSHI , BANDOH TADAAKI , MATSUMOTO HIDEKAZU , HIRAOKA RYOSEI , IDE JUSHI , KATO TAKESHI , KAWAKAMI TETSUYA
IPC分类号： G06F12/08 , G06F12/10 , G06F13/00
摘要： A virtual storage data processing system having an address translation unit (75) shared by a plurality of processors, located in a memory control unit (12) connected to a main memory (10) is disclosed. One of the plurality of processors is a job processor (40) which accesses the main memory with a virtual address to execute an instruction and includes a cache memory (41, 42) which is accessed with a virtual address. One of the plurality of processors is a file processor, (22) which accesses the main memory with a virtual address to transfer data between the main memory and an external memory (20). The cache memory receives the virtual address when the file processor writes to the main memory and if it contains a data block corresponding to the virtual address, it invalidates the corresponding data block. The address translation unit translates the address differently for the access from the file processor and the accesses from other processors.

4. 发明专利

CA1179069A DATA TRANSMISSION APPARATUS FOR A MULTIPROCESSOR SYSTEM 未知
公开(公告)号：CA1179069A
公开(公告)日：1984-12-04
申请号：CA400616
申请日：1982-04-07
申请人： HITACHI LTD , HITACHI ENG CO LTD
发明人： FUKUNAGA YASUSHI , BANDOH TADAAKI , HIRAOKA RYOSEI , MATSUMOTO HIDEKAZU , IDE JUSHI , KAWAKAMI TETSUYA
IPC分类号： G06F13/374 , G06F13/00
摘要： In a multiprocessor system having a main memory and a plurality of processors connected through common address bus, data bus and answer bus for the data transfer, a data transmission apparatus is provided for each of the main memory and the processors and includes bus request control lines for transferring bus request signals and bus control signals and a bus controller for separately controlling selections of the address bus, the data bus and the answer bus in response to the signals on the bus request control lines and the request signal. Overlapped processing such as data write and data write answer or data read and data read answer in one cycle is permitted.

5. 发明专利

DE3278442D1 CENTRAL PROCESSING UNIT FOR EXECUTING INSTRUCTIONS OF VARIABLE LENGTH 未知
公开(公告)号：DE3278442D1
公开(公告)日：1988-06-09
申请号：DE3278442
申请日：1982-08-19
申请人： HITACHI LTD , HITACHI ENG CO LTD
发明人： FUKUNAGA YASUSHI , BANDOH TADAAKI , HIRASAWA KOTARO , MATSUMOTO HIDEKAZU , IDE JUSHI , KATOH TAKESHI , NAKANISHI HIROAKI , KAWAKAMI TETSUYA , HIRAOKA RYOSEI
IPC分类号： G06F9/30 , G06F9/318 , G06F9/34
摘要： A central processing unit for executing instructions of variable length in which an operand specifier for specifying the addressing mode of an operand is independent of an operation code for ascertaining the kind of an operation and the number of operands. Each operand specifier is formed of one or more data bytes, and has a stop bit flag indicating whether or not the particular operand specifier is the last operand specifier. By adding the stop bit flag, the operand specifier can be shared, and different processing can be executed with an identical operation code. In a case where, when operation code decoding means has provided an output indicative of the last operand, the stop bit flag is not detected in the corresponding operand specifier, the corresponding instruction is detected as an error.

6. 发明专利

DE3267523D1 DATA PROCESSING APPARATUS FOR A MULTIPROCESSOR SYSTEM 未知
公开(公告)号：DE3267523D1
公开(公告)日：1986-01-02
申请号：DE3267523
申请日：1982-04-08
申请人： HITACHI LTD , HITACHI ENG CO LTD
发明人： FUKUNAGA YASUSHI MORIYAMA-APAR , BANDOH TADAAKI , HIRAOKA RYOSEI , MATSUMOTO HIDEKAZU MORIYAMA-AP , IDE JUSHI , KAWAKAMI TETSUYA
IPC分类号： G06F13/374 , G06F13/36
摘要： In a multiprocessor system having a main memory and a plurality of processors connected through common address bus, data bus and answer bus for data transfer, a data transmission apparatus is provided for each of the main memory and the processors and includes bus request control lines for transferring bus request signals and bus control signals, and a bus controller for separately controlling selections of the address bus, the data bus and the answer bus in response to the signals on the bus request control lines and the request signal. Overlapped processing such as data write and data write answer or data read and data read answer in one cycle is possible.

7. 发明专利

CA1173567A SHARED VIRTUAL ADDRESS TRANSLATION UNIT FOR A MULTIPROCESSOR SYSTEM 未知
公开(公告)号：CA1173567A
公开(公告)日：1984-08-28
申请号：CA390161
申请日：1981-11-16
申请人： HITACHI LTD , HITACHI ENG CO LTD
发明人： FUKUNAGA YASUSHI , BANDOH TADAAKI , MATSUMOTO HIDEKAZU , HIRAOKA RYOSEI , IDE JUSHI , KATO TAKESHI , KAWAKAMI TETSUYA
IPC分类号： G06F12/08 , G06F12/10 , G11C9/06
摘要： A virtual storage data processing system having an address translation unit shared by a plurality of processors, located in a memory control unit connected to a main memory is disclosed. One of the plurality of processors is a job processor which accesses the main memory with a virtual address to execute an instruction and includes a cache memory which is accessed with a virtual address. One of the plurality of processors is a file processor which accesses the main memory with a virtual address to transfer data between the main memory and an external memory. The cache memory receives the virtual address when the file processor writes to the main memory and if it contains a data block corresponding to the virtual address, it invalidates the corresponding data block. The address translation unit translates the address differently for the access from the file processor and the accesses from other processors.

8. 发明专利

DE3689389T2 未知
公开(公告)号：DE3689389T2
公开(公告)日：1994-04-07
申请号：DE3689389
申请日：1986-07-03
申请人： HITACHI LTD , HITACHI ENG CO LTD
发明人： YAMAGUCHI SHINICHIRO , MATSUMOTO HIDEKAZU , BANDOH TADAAKI , NAKANISHI HIROAKI , HIROSE KENZI , KOBAYASHI TAKAO , MIYAZAKI YOSHIHIRO
IPC分类号： G06F9/30 , G06F9/318 , G06F9/44
摘要： A data processor (100) for execution of tagged data and tagless data has a decoder (130) for discriminating whether the data is tagged or tagless one and in case of a tagged data, separates a tag part and uses the remaining part for address computation. The data processor also comprises a unit for evaluating the tag part and a micro program controller (290) for multi-branching in accordance with the evaluation result of the tag part. The tag evaluating unit includes an extender eliminating part (250) for extracting the tag part from data on a data bus (340), a plurality of tag part storing registers (260, 270) for storing the tag part from the eliminating part under the control of the micro program controller, and a tag multi-way jump encoder (292) for generating a tag multi-way jump address to feed it to the controller on the basis of the outputs of the registers and a signal from the micro program controller, thereby enabling tag multi-way jump.

9. 发明授权

KR880000462B1 DATA TRANSMISSION APPARATUS FOR A MULTIPROCESSOR SYSTEM 失效
公开(公告)号：KR880000462B1
公开(公告)日：1988-04-06
申请号：KR820001547
申请日：1982-04-08
申请人： HITACHI LTD
发明人： FUKUNAGA YASUSHI , BANDOH TADAAKI , HIRAOKA RYOSEI , MATSUMOTO HIDEKAZU , JUSHI IDE , KAWAKAMI TETSUYA
IPC分类号： H04L5/22 , G06F13/36 , G06F13/42 , H04L11/16
摘要： The appts. has memory units, a number of processors, a common bus, an address bus, a data bus, an answer bus connected between the memory unit and processors, and a bus control unit for controlling data transfer. The appts. includes separate bus request control lines associated with the address bus, data bus and answer bus and connected to the memory unit and processors. The bus control unit is connected to these control lines to control bus selection by a bus requesting unit and/or processor for each bus in response to a bus request signal.

10. 发明专利

DE69032812T2 未知
公开(公告)号：DE69032812T2
公开(公告)日：1999-04-29
申请号：DE69032812
申请日：1990-07-06
申请人： HITACHI LTD
发明人： KUROSAWA KENICHI , TANAKA SHIGEYA , NAKATSUKA YASUHIRO , BANDOH TADAAKI
IPC分类号： G06F9/318 , G06F9/38 , G06F12/08 , G06F15/177
摘要： The described parallel processing apparatus and method turns a processing state discrimination flag (PE, 116) off, increases a program count by 1 at a time, reads out one instruction, and processes that instruction in an arithmetic unit, when it executes successivc processing of conventional software, and when it executes parallel processing of new software turns the processing state discrimination flag (PE, 116) on, increases the program count by m at a time, reads out m instructions, and exercises parallel processing over m instructions in m arithmetic units. In order to select either of the above described two kinds of processing, a discrimination changeover instruction having function of changing over the processing state discrimination flag (PE, 116) is added. The instructions are processed in one or in m arithmetic unit(s) (108, 109) in accordance with the processing state discrimination flag. In this way, successive processing and parallel processing are provided with compatibility and are selectively executed.

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