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1. 发明授权

KR880000297B1 CENTRAL PROCESSING UNIT FOR EXECUTING INSTRUCTIONS OF VARIABLE LENGTH 失效
公开(公告)号：KR880000297B1
公开(公告)日：1988-03-19
申请号：KR820003773
申请日：1982-08-23
申请人： HITACHI LTD , HITACHI ENG CO LTD
发明人： FUKUNAGA YASUSHI , HIRASAWA KOTARO , IDE JUSHI , BANDOH TADAAKI , MATSUMOTO HIDEKAZU , KATOH TAKESHI
IPC分类号： G06F9/30 , G06F9/318 , G06F9/36
摘要： Instructions are fetched from a cache memory by an instruction fetch unit. A decoder connected to the instruction fetch unit decodes an operand specifier and an operation code. On the basis of the decoded operand specifier, an address calculating unit calculates the address of the specified operand in the cache. An operand fetch unit then retrieves the operand from the cache address calculated. An operation code decoder is provided, in the decoder, to decode the operand from the cache address calculated.

2. 发明专利

DE3176512D1 A VIRTUAL STORAGE DATA PROCESSING SYSTEM 未知
公开(公告)号：DE3176512D1
公开(公告)日：1987-12-10
申请号：DE3176512
申请日：1981-11-16
申请人： HITACHI LTD , HITACHI ENG CO LTD
发明人： FUKUNAGA YASUSHI , BANDOH TADAAKI , MATSUMOTO HIDEKAZU , HIRAOKA RYOSEI , IDE JUSHI , KATO TAKESHI , KAWAKAMI TETSUYA
IPC分类号： G06F12/08 , G06F12/10 , G06F13/00
摘要： A virtual storage data processing system having an address translation unit (75) shared by a plurality of processors, located in a memory control unit (12) connected to a main memory (10) is disclosed. One of the plurality of processors is a job processor (40) which accesses the main memory with a virtual address to execute an instruction and includes a cache memory (41, 42) which is accessed with a virtual address. One of the plurality of processors is a file processor, (22) which accesses the main memory with a virtual address to transfer data between the main memory and an external memory (20). The cache memory receives the virtual address when the file processor writes to the main memory and if it contains a data block corresponding to the virtual address, it invalidates the corresponding data block. The address translation unit translates the address differently for the access from the file processor and the accesses from other processors.

3. 发明专利

CA1179069A DATA TRANSMISSION APPARATUS FOR A MULTIPROCESSOR SYSTEM 未知
公开(公告)号：CA1179069A
公开(公告)日：1984-12-04
申请号：CA400616
申请日：1982-04-07
申请人： HITACHI LTD , HITACHI ENG CO LTD
发明人： FUKUNAGA YASUSHI , BANDOH TADAAKI , HIRAOKA RYOSEI , MATSUMOTO HIDEKAZU , IDE JUSHI , KAWAKAMI TETSUYA
IPC分类号： G06F13/374 , G06F13/00
摘要： In a multiprocessor system having a main memory and a plurality of processors connected through common address bus, data bus and answer bus for the data transfer, a data transmission apparatus is provided for each of the main memory and the processors and includes bus request control lines for transferring bus request signals and bus control signals and a bus controller for separately controlling selections of the address bus, the data bus and the answer bus in response to the signals on the bus request control lines and the request signal. Overlapped processing such as data write and data write answer or data read and data read answer in one cycle is permitted.

4. 发明专利

DE3278442D1 CENTRAL PROCESSING UNIT FOR EXECUTING INSTRUCTIONS OF VARIABLE LENGTH 未知
公开(公告)号：DE3278442D1
公开(公告)日：1988-06-09
申请号：DE3278442
申请日：1982-08-19
申请人： HITACHI LTD , HITACHI ENG CO LTD
发明人： FUKUNAGA YASUSHI , BANDOH TADAAKI , HIRASAWA KOTARO , MATSUMOTO HIDEKAZU , IDE JUSHI , KATOH TAKESHI , NAKANISHI HIROAKI , KAWAKAMI TETSUYA , HIRAOKA RYOSEI
IPC分类号： G06F9/30 , G06F9/318 , G06F9/34
摘要： A central processing unit for executing instructions of variable length in which an operand specifier for specifying the addressing mode of an operand is independent of an operation code for ascertaining the kind of an operation and the number of operands. Each operand specifier is formed of one or more data bytes, and has a stop bit flag indicating whether or not the particular operand specifier is the last operand specifier. By adding the stop bit flag, the operand specifier can be shared, and different processing can be executed with an identical operation code. In a case where, when operation code decoding means has provided an output indicative of the last operand, the stop bit flag is not detected in the corresponding operand specifier, the corresponding instruction is detected as an error.

5. 发明专利

DE3267523D1 DATA PROCESSING APPARATUS FOR A MULTIPROCESSOR SYSTEM 未知
公开(公告)号：DE3267523D1
公开(公告)日：1986-01-02
申请号：DE3267523
申请日：1982-04-08
申请人： HITACHI LTD , HITACHI ENG CO LTD
发明人： FUKUNAGA YASUSHI MORIYAMA-APAR , BANDOH TADAAKI , HIRAOKA RYOSEI , MATSUMOTO HIDEKAZU MORIYAMA-AP , IDE JUSHI , KAWAKAMI TETSUYA
IPC分类号： G06F13/374 , G06F13/36
摘要： In a multiprocessor system having a main memory and a plurality of processors connected through common address bus, data bus and answer bus for data transfer, a data transmission apparatus is provided for each of the main memory and the processors and includes bus request control lines for transferring bus request signals and bus control signals, and a bus controller for separately controlling selections of the address bus, the data bus and the answer bus in response to the signals on the bus request control lines and the request signal. Overlapped processing such as data write and data write answer or data read and data read answer in one cycle is possible.

6. 发明专利

CA1173567A SHARED VIRTUAL ADDRESS TRANSLATION UNIT FOR A MULTIPROCESSOR SYSTEM 未知
公开(公告)号：CA1173567A
公开(公告)日：1984-08-28
申请号：CA390161
申请日：1981-11-16
申请人： HITACHI LTD , HITACHI ENG CO LTD
发明人： FUKUNAGA YASUSHI , BANDOH TADAAKI , MATSUMOTO HIDEKAZU , HIRAOKA RYOSEI , IDE JUSHI , KATO TAKESHI , KAWAKAMI TETSUYA
IPC分类号： G06F12/08 , G06F12/10 , G11C9/06
摘要： A virtual storage data processing system having an address translation unit shared by a plurality of processors, located in a memory control unit connected to a main memory is disclosed. One of the plurality of processors is a job processor which accesses the main memory with a virtual address to execute an instruction and includes a cache memory which is accessed with a virtual address. One of the plurality of processors is a file processor which accesses the main memory with a virtual address to transfer data between the main memory and an external memory. The cache memory receives the virtual address when the file processor writes to the main memory and if it contains a data block corresponding to the virtual address, it invalidates the corresponding data block. The address translation unit translates the address differently for the access from the file processor and the accesses from other processors.

7. 发明专利

DE3246872A1 未知
公开(公告)号：DE3246872A1
公开(公告)日：1983-07-07
申请号：DE3246872
申请日：1982-12-17
申请人： HITACHI LTD
发明人： YABUUCHI SHIGERU , ENDO TAKEYUKI , KODAMA KAZUYUKI , IDE JUSHI
IPC分类号： G06F7/04 , G06F7/64 , G06F7/48 , G06F15/328
摘要： In a floating point digital differential analyzer, multiplication and division of constants are carried out by an adder which truncates a summation SDYi of l secondary increments calculated by into a third increment having an n-bit mantissa including a sign bit, and an integrator for carrying out an integration of Ri:=Ri-1+Yix DELTA Xi- DELTA Zi irrespective of a value of a first increment DELTA Xi to generate DELTA Zi from Ri.

8. 发明专利

DE3201088A1 未知
公开(公告)号：DE3201088A1
公开(公告)日：1982-08-05
申请号：DE3201088
申请日：1982-01-15
申请人： HITACHI LTD , HITACHI ELECTRONICS
发明人： YABUUCHI SHIGERU , ENDOH TAKEYUKI , KODAMA KAZUYUKI , IDE JUSHI
IPC分类号： G06F7/64 , G06F17/13 , G06F17/17 , H03H17/00 , H03H17/02 , H03H17/08 , G06F15/31
摘要： In order to deliver an input signal of each operation cycle after a desired time delay, there are disposed data memory means for storing the input signal, counter means for appointing write addresses of the data memory means, and address memory means for appointing read addresses of the data memory means. The address memory means is divided into partial memory areas equal in number to time delay elements, whereupon while sampling the input signal at a predetermined sampling period and changing the count value of the counter means one by one for each of the desired time delay elements at each sampling point, the variations of the input signal in a sampling interval between the particular sampling point and the adjacent sampling point are successively written into the memory means. Further, while changing the contents of the partial memory areas corresponding to the desired time delay element to the number of the time delay elements in each sampling interval, the variations in a sampling interval preceding a predetermined sampling number to the particular sampling interval are successively read out from the memory means. The input signal of each operation cycle in the preceding sampling interval is presumed by an interpolation operation based on the variation and the sampling period, and the result is used as an output signal of the desired time delay element.

9. 发明专利

DE3037883A1 Digital integrator - has control and arithmetic processor base unit to perform integration for digital solution of differential equation 未知
公开(公告)号：DE3037883A1
公开(公告)日：1982-04-22
申请号：DE3037883
申请日：1980-10-07
申请人： HITACHI LTD
发明人： NOGUCHI ATOMI , KUWAHARA HIROSHI , IDE JUSHI , MIYAZAKI YOSHIHIRO
IPC分类号： G06F17/13 , G06F15/328
摘要： The digital integrator (12) has a control processor (16), arithmetic processor (17), data memory (18) and a processor interface (13). All the elements are coupled onto a bus (15) with direct memory access. A separate control link (19) connects the processors. The control processor has an arithmetic logic unit directed by a built in control stage responding to a micro-programme memory. Operating together with the main processor (17), the unit performs the necessary interative addition involved in the integration process.

10. 发明专利

DE3735828C2 未知
公开(公告)号：DE3735828C2
公开(公告)日：1994-11-10
申请号：DE3735828
申请日：1987-10-22
申请人： HITACHI LTD
发明人： YAMAGUCHI SHINICHIRO , MATSUMOTO HIDEKAZU , BANDOH TADAAKI , HIRAYAMA HIROKAZU , MORIOKA TAKAYUKI , TAKAYA SOICHI , KAWAMOTO YUKIO , IDE JUSHI , MIYAZAKI YOSHIHIRO
IPC分类号： G06F11/14 , G06F9/26
摘要： Method and apparatus for instruction restart processing in a microprogram - controlled data processing apparatus, wherein, in restarting an instruction execution after instruction suspension, the internal information of the data processing apparatus at the time of instruction execution suspension is saved in a memory, and after a suspension cause removal process performed the saved internal information is recovered. A check point address associated with the address of a currently executing microprogram is stored in accordance with a designation by the microprogram. After a suspension causes removal process is performed, the execution of the instruction restarts using the check point address. If a check point address has not been stored after the suspension cause removal process is performed, the execution of the instruction restarts from a read operation of the suspended instruction from the main storage.

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