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1. 发明授权

KR880000297B1 CENTRAL PROCESSING UNIT FOR EXECUTING INSTRUCTIONS OF VARIABLE LENGTH 失效
公开(公告)号：KR880000297B1
公开(公告)日：1988-03-19
申请号：KR820003773
申请日：1982-08-23
申请人： HITACHI LTD , HITACHI ENG CO LTD
发明人： FUKUNAGA YASUSHI , HIRASAWA KOTARO , IDE JUSHI , BANDOH TADAAKI , MATSUMOTO HIDEKAZU , KATOH TAKESHI
IPC分类号： G06F9/30 , G06F9/318 , G06F9/36
摘要： Instructions are fetched from a cache memory by an instruction fetch unit. A decoder connected to the instruction fetch unit decodes an operand specifier and an operation code. On the basis of the decoded operand specifier, an address calculating unit calculates the address of the specified operand in the cache. An operand fetch unit then retrieves the operand from the cache address calculated. An operation code decoder is provided, in the decoder, to decode the operand from the cache address calculated.

2. 发明专利

DE3176512D1 A VIRTUAL STORAGE DATA PROCESSING SYSTEM 未知
公开(公告)号：DE3176512D1
公开(公告)日：1987-12-10
申请号：DE3176512
申请日：1981-11-16
申请人： HITACHI LTD , HITACHI ENG CO LTD
发明人： FUKUNAGA YASUSHI , BANDOH TADAAKI , MATSUMOTO HIDEKAZU , HIRAOKA RYOSEI , IDE JUSHI , KATO TAKESHI , KAWAKAMI TETSUYA
IPC分类号： G06F12/08 , G06F12/10 , G06F13/00
摘要： A virtual storage data processing system having an address translation unit (75) shared by a plurality of processors, located in a memory control unit (12) connected to a main memory (10) is disclosed. One of the plurality of processors is a job processor (40) which accesses the main memory with a virtual address to execute an instruction and includes a cache memory (41, 42) which is accessed with a virtual address. One of the plurality of processors is a file processor, (22) which accesses the main memory with a virtual address to transfer data between the main memory and an external memory (20). The cache memory receives the virtual address when the file processor writes to the main memory and if it contains a data block corresponding to the virtual address, it invalidates the corresponding data block. The address translation unit translates the address differently for the access from the file processor and the accesses from other processors.

3. 发明专利

CA1179069A DATA TRANSMISSION APPARATUS FOR A MULTIPROCESSOR SYSTEM 未知
公开(公告)号：CA1179069A
公开(公告)日：1984-12-04
申请号：CA400616
申请日：1982-04-07
申请人： HITACHI LTD , HITACHI ENG CO LTD
发明人： FUKUNAGA YASUSHI , BANDOH TADAAKI , HIRAOKA RYOSEI , MATSUMOTO HIDEKAZU , IDE JUSHI , KAWAKAMI TETSUYA
IPC分类号： G06F13/374 , G06F13/00
摘要： In a multiprocessor system having a main memory and a plurality of processors connected through common address bus, data bus and answer bus for the data transfer, a data transmission apparatus is provided for each of the main memory and the processors and includes bus request control lines for transferring bus request signals and bus control signals and a bus controller for separately controlling selections of the address bus, the data bus and the answer bus in response to the signals on the bus request control lines and the request signal. Overlapped processing such as data write and data write answer or data read and data read answer in one cycle is permitted.

4. 发明专利

DE3278442D1 CENTRAL PROCESSING UNIT FOR EXECUTING INSTRUCTIONS OF VARIABLE LENGTH 未知
公开(公告)号：DE3278442D1
公开(公告)日：1988-06-09
申请号：DE3278442
申请日：1982-08-19
申请人： HITACHI LTD , HITACHI ENG CO LTD
发明人： FUKUNAGA YASUSHI , BANDOH TADAAKI , HIRASAWA KOTARO , MATSUMOTO HIDEKAZU , IDE JUSHI , KATOH TAKESHI , NAKANISHI HIROAKI , KAWAKAMI TETSUYA , HIRAOKA RYOSEI
IPC分类号： G06F9/30 , G06F9/318 , G06F9/34
摘要： A central processing unit for executing instructions of variable length in which an operand specifier for specifying the addressing mode of an operand is independent of an operation code for ascertaining the kind of an operation and the number of operands. Each operand specifier is formed of one or more data bytes, and has a stop bit flag indicating whether or not the particular operand specifier is the last operand specifier. By adding the stop bit flag, the operand specifier can be shared, and different processing can be executed with an identical operation code. In a case where, when operation code decoding means has provided an output indicative of the last operand, the stop bit flag is not detected in the corresponding operand specifier, the corresponding instruction is detected as an error.

5. 发明专利

CA1173567A SHARED VIRTUAL ADDRESS TRANSLATION UNIT FOR A MULTIPROCESSOR SYSTEM 未知
公开(公告)号：CA1173567A
公开(公告)日：1984-08-28
申请号：CA390161
申请日：1981-11-16
申请人： HITACHI LTD , HITACHI ENG CO LTD
发明人： FUKUNAGA YASUSHI , BANDOH TADAAKI , MATSUMOTO HIDEKAZU , HIRAOKA RYOSEI , IDE JUSHI , KATO TAKESHI , KAWAKAMI TETSUYA
IPC分类号： G06F12/08 , G06F12/10 , G11C9/06
摘要： A virtual storage data processing system having an address translation unit shared by a plurality of processors, located in a memory control unit connected to a main memory is disclosed. One of the plurality of processors is a job processor which accesses the main memory with a virtual address to execute an instruction and includes a cache memory which is accessed with a virtual address. One of the plurality of processors is a file processor which accesses the main memory with a virtual address to transfer data between the main memory and an external memory. The cache memory receives the virtual address when the file processor writes to the main memory and if it contains a data block corresponding to the virtual address, it invalidates the corresponding data block. The address translation unit translates the address differently for the access from the file processor and the accesses from other processors.

6. 发明专利

JPS5864690A CONTROL METHOD FOR CASH MEMORY 失效
公开(公告)号：JPS5864690A
公开(公告)日：1983-04-18
申请号：JP16269281
申请日：1981-10-14
申请人： HITACHI LTD , HITACHI ENG CO LTD
发明人： KAWAKAMI TETSUYA , BANDOU TADAAKI , FUKUNAGA YASUSHI , HIRAOKA YOSHINARI , MATSUMOTO HIDEKAZU , KATOU TAKESHI , IDE TOSHIYUKI
IPC分类号： G06F12/08 , G06F12/10 , G06F15/16 , G06F15/177
摘要： PURPOSE:To obtain data coincidence between a main and cash memories by performing the processing of resetting a significant bit in a cash through invalidating processing and the processing of setting a new significant bit in the order of access signals to a common bus. CONSTITUTION:In response to a write access signal being transferred through a start bus 55 and a data bus 56 as common buses by time slots 1 and 3, a check on an invalidating directory 83 is made by time slots 2 and 4, and the contents of a significant bit register 84 are cleared in the former halves of time slots 3 and 5 to perform invadiating processing. With regard to read access which causes a cash error, an address is transferred to the start but 55 by the time slot 2, so access to a main memory is done after write access being transferred through the start bus 55 by the time slot 1 and after write access being transferred by the start bus 55 by the time slot 3.

7. 发明专利

JPS5844539A DATA PROCESSOR HANDLING INSTRUCTION OF UNFIXED LENGTH 失效
公开(公告)号：JPS5844539A
公开(公告)日：1983-03-15
申请号：JP14110381
申请日：1981-09-09
申请人： HITACHI LTD , HITACHI ENG CO LTD
发明人： FUKUNAGA YASUSHI , BANDOU TADAAKI , HIRAOKA YOSHINARI , HIRASAWA KOUTAROU , MATSUMOTO HIDEKAZU , IDE TOSHIYUKI , KATOU TAKESHI , NAKANISHI HIROAKI , KAWAKAMI TETSUYA
IPC分类号： G06F9/32 , G06F9/34
摘要： PURPOSE:To ensure the sharing of an operand designator to plural operands, by using the operand designator again in case the setting of the continuation information of the operand designator is detected. CONSTITUTION:A signal line 205 showing an operand end flag E, a signal line 205 showing the continuous bit S of an operand designator and a signal line 215 showing the byte number of the operand designator are fed to a detector 65 of decoding process byte number. The value of addition of a DP register 69 is delivered to a signal line 214 to show address of the next operand designator. In case the flag E is not 1 and the signal having the designator continuation information of 1 is given, 0 is delivered to the line 214 so that the register 69 has the value as it is. Thus the same operand designator is used also for the process of the next operand. As a result, the same operand is repetitively used.

8. 发明专利

JPS57168318A DATA TRANSMITTING DEVICE 失效
公开(公告)号：JPS57168318A
公开(公告)日：1982-10-16
申请号：JP5294981
申请日：1981-04-10
申请人： HITACHI LTD , HITACHI ENG CO LTD
发明人： FUKUNAGA YASUSHI , BANDOU TADAAKI , HIRAOKA YOSHINARI , MATSUMOTO HIDEKAZU , IDE TOSHIYUKI , KAWAKAMI TETSUYA
IPC分类号： G06F11/00 , G06F11/08 , G06F11/30 , G06F13/00 , G06F15/16 , G06F15/177
摘要： PURPOSE:To eliminate an error checking means to be provided to each processor, by feeding the error information to the processor that performs the transmission of data when a transmission error is detected on a bus after setting a bus monitor mechanism. CONSTITUTION:Various types of processors 12-1-12-N are connected to an address bus 13, a data bus 14 and an answer bus 15 which are provided commonly to a storage device 10. These processors carry out the transmission of data to a memory 10 by using the buses 13, 14 and 15 for the data write and read requests, the data write request and the data read answer, and the data write and read answers respectively. A bus monitor mechanism 11 is connected to each bus to monitor the error of transmission. In case an error is detected by the mechanism 11, the error information is fed to the processor that is performing the transmission of data, via an error informing signal line 16. Thus each processor receives only the result of the error checking to eliminate an individual installation of an error checking circuit. As a result, the hard quantity can be reduced.

9. 发明专利

JPS57100680A PAGE FAULT PROCESSING SYSTEM 失效
公开(公告)号：JPS57100680A
公开(公告)日：1982-06-22
申请号：JP17586380
申请日：1980-12-15
申请人： HITACHI LTD , HITACHI ENG CO LTD
发明人： BANDOU TADAAKI , MATSUMOTO HIDEKAZU , FUKUNAGA YASUSHI , HIRAOKA YOSHINARI , IDE TOSHIYUKI , KAWAKAMI TETSUYA
IPC分类号： G06F12/08 , G06F12/10
摘要： PURPOSE:To perform page fault processing at a high speed without increasing overhead, by storing the address of an instruction, etc., interrupted according to a page fault signal, in a store buffer temporarily and by handling it when the instruction is restarted. CONSTITUTION:Once a page fault occurs, the contents of an address register 26 are transferred to a store buffer 38, wherein the same contents as those written in a cash register consisting of a directory part 29 and a data part 30 in writing operation, temporarily according to an interruption instruction. Simultaneously, an interruption signal is generated and when page fault processing ends, reading operation is restarted by an instruction which corresponds to an address, etc., held in the buffer 38 temporarily. In case of an error page fault during writing operation, the address of a next instruction is stored in the buffer 38 after the writing operation ends and restarting processing is performed similarly. Therefore, the need to make an address check or to retain instruction input data before reading and writing operation is eliminated, and the page fault processing is performed at a high speed without increasing an overhead.

10. 发明专利

JPS5736490A Address conversion system 失效
标题翻译：空值
公开(公告)号：JPS5736490A
公开(公告)日：1982-02-27
申请号：JP10831580
申请日：1980-08-08
申请人： Hitachi Eng Co Ltd , Hitachi Ltd
发明人： KAWAKAMI TETSUYA , BANDO TADAAKI , FUKUNAGA YASUSHI
IPC分类号： G06F12/10
CPC分类号： G06F12/10
摘要： PURPOSE:To reduce the address conversion time, by reducing the number of conversion pairs connected with pointers, in an address conversion system making the conversion from a logical address to a physical address. CONSTITUTION:A logical address set to a logical address register 11 is selected with a selector 81 and a conversion table 70 is accessed with the lower rank bit of a PID. Next, the label 71 of the conversion pair and the upper rank bit of the PID are compared at a comparator 82. As a result of comparison, when the both are equal, the physical address is formed with FID and BID. If the label 71 is smaller, an NP1 is selected with selectors 83, 81 for the next search. If the label 71 is greater, search is made with the value of an NP2. If the value of pointer is made coincide with the value of a completion display register 84, the page is absent on the main memory.
摘要翻译：目的：通过减少与指针连接的转换对数，减少地址转换时间，从地址转换系统进行从逻辑地址到物理地址的转换。构成：通过选择器81选择设置到逻辑地址寄存器11的逻辑地址，并且利用PID的较低等级位访问转换表70。接下来，在比较器82中比较转换对的标签71和PID的高位。作为比较的结果，当两者相等时，物理地址由FID和BID形成。如果标签71较小，则用选择器83,81选择NP1用于下一次搜索。如果标签71较大，则以NP2的值进行搜索。如果指示符的值与完成显示寄存器84的值一致，则在主存储器上不存在该页面。

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