专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20140189239A1 PROCESSORS HAVING VIRTUALLY CLUSTERED CORES AND CACHE SLICES 审中-公开
标题翻译：具有虚拟聚合的CORES和CACHE SLICES的处理程序
公开(公告)号：US20140189239A1
公开(公告)日：2014-07-03
申请号：US13729579
申请日：2012-12-28
申请人： Herbert H. Hum , Brinda Ganesh , James R. Vash , Ganesh Kumar , Leena K. Puthiyedath , Scott J. Erlanger , Eric J. Dehaemer , Adrian C. Moga , Michelle M. Sebot , Richard L. Carlson , David Bubien , Eric Delano
发明人： Herbert H. Hum , Brinda Ganesh , James R. Vash , Ganesh Kumar , Leena K. Puthiyedath , Scott J. Erlanger , Eric J. Dehaemer , Adrian C. Moga , Michelle M. Sebot , Richard L. Carlson , David Bubien , Eric Delano
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F12/0811 , G06F12/084
摘要： A processor of an aspect includes a plurality of logical processors each having one or more corresponding lower level caches. A shared higher level cache is shared by the plurality of logical processors. The shared higher level cache includes a distributed cache slice for each of the logical processors. The processor includes logic to direct an access that misses in one or more lower level caches of a corresponding logical processor to a subset of the distributed cache slices in a virtual cluster that corresponds to the logical processor. Other processors, methods, and systems are also disclosed.
摘要翻译：一方面的处理器包括多个逻辑处理器，每个逻辑处理器具有一个或多个相应的较低级别的高速缓存。共享的较高级缓存由多个逻辑处理器共享。共享的较高级缓存包括用于每个逻辑处理器的分布式缓存片。处理器包括用于将对应逻辑处理器的一个或多个较低级别高速缓存中的访问指向与对应于逻辑处理器的虚拟集群中的分布式高速缓存片段的子集的逻辑。还公开了其他处理器，方法和系统。

2. 发明授权

US08799586B2 Memory mirroring and migration at home agent 有权
标题翻译：内部镜像和迁移在本地代理
公开(公告)号：US08799586B2
公开(公告)日：2014-08-05
申请号：US12571382
申请日：2009-09-30
申请人： Ganesh Kumar , Dheemanth Nagaraj , Vincent R. Freytag , Eric Delano , Gregory S. Averill
发明人： Ganesh Kumar , Dheemanth Nagaraj , Vincent R. Freytag , Eric Delano , Gregory S. Averill
IPC分类号： G06F12/08 , G06F12/16
CPC分类号： G06F12/0817
摘要： Methods and apparatus relating to memory mirroring and migration at a Home Agent (HA) are described. In one embodiment, a home agent may mirror its data at a slave agent. In some embodiments, a bit in a directory may indicate status of cache lines. Other embodiments are also disclosed.
摘要翻译：描述了与归属代理（HA）的内存镜像和迁移有关的方法和设备。在一个实施例中，归属代理可以在从属代理处镜像其数据。在一些实施例中，目录中的位可以指示高速缓存行的状态。还公开了其他实施例。

3. 发明授权

US08327228B2 Home agent data and memory management 失效
标题翻译：家庭代理数据和内存管理
公开(公告)号：US08327228B2
公开(公告)日：2012-12-04
申请号：US12571381
申请日：2009-09-30
申请人： Ganesh Kumar , Dheemanth Nagaraj , Vincent R. Freytag , Eric Delano , Gregory S. Averill
发明人： Ganesh Kumar , Dheemanth Nagaraj , Vincent R. Freytag , Eric Delano , Gregory S. Averill
IPC分类号： G11C29/00
CPC分类号： G06F12/0817
摘要： Methods and apparatus relating to home agent data and memory management are described. In one embodiment, a scrubber logic corrects an error at a location in a memory corresponding to a target address by writing back the corrected version of data to the target location. In an embodiment, a map out logic maps out an index or way of a directory cache in response to a number of errors, corresponding to the directory cache, exceeding a threshold value. Other embodiments are also disclosed.
摘要翻译：描述与归属代理数据和存储器管理有关的方法和装置。在一个实施例中，洗涤器逻辑通过将校正的数据版本写回到目标位置来校正与目标地址相对应的存储器中的位置处的错误。在一个实施例中，映射逻辑响应于对应于目录高速缓存的多个错误超过阈值来映射目录高速缓存的索引或方式。还公开了其他实施例。

4. 发明申请

US20110078384A1 MEMORY MIRRORING AND MIGRATION AT HOME AGENT 有权
标题翻译：在家庭代理记忆转移和移动
公开(公告)号：US20110078384A1
公开(公告)日：2011-03-31
申请号：US12571382
申请日：2009-09-30
申请人： Ganesh Kumar , Dheemanth Nagaraj , Vincent R. Freytag , Eric Delano , Gregory S. Averill
发明人： Ganesh Kumar , Dheemanth Nagaraj , Vincent R. Freytag , Eric Delano , Gregory S. Averill
IPC分类号： G06F12/08 , G06F12/00 , G06F12/16
CPC分类号： G06F12/0817
摘要： Methods and apparatus relating to memory mirroring and migration at a Home Agent (HA) are described. In one embodiment, a home agent may mirror its data at a slave agent. In some embodiments, a bit in a directory may indicate status of cache lines. Other embodiments are also disclosed.
摘要翻译：描述了与归属代理（HA）的内存镜像和迁移有关的方法和设备。在一个实施例中，归属代理可以在从属代理处镜像其数据。在一些实施例中，目录中的位可以指示高速缓存行的状态。还公开了其他实施例。

5. 发明申请

US20100332767A1 Controllably Exiting An Unknown State Of A Cache Coherency Directory 有权
标题翻译：可控地退出高速缓存一致性目录的未知状态
公开(公告)号：US20100332767A1
公开(公告)日：2010-12-30
申请号：US12492280
申请日：2009-06-26
申请人： Ganesh Kumar , Dheemanth Nagaraj , Vincent R. Freytag , Eric Delano , Gregory S. Averill
发明人： Ganesh Kumar , Dheemanth Nagaraj , Vincent R. Freytag , Eric Delano , Gregory S. Averill
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0817 , G06F9/5033 , G06F2212/1032
摘要： In one embodiment, a method includes receiving a read request from a first caching agent and if a directory entry associated with the request is in an unknown state, an invalidating snoop message is sent to at least one other caching agent to invalidate information in a cache location of the other caching agent corresponding to the location of the read request, to enable setting of the directory entry into a known state. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，一种方法包括从第一高速缓存代理接收读取请求，并且如果与请求相关联的目录条目处于未知状态，则向至少一个其他高速缓存代理发送无效侦听消息以使高速缓存中的信息无效与读取请求的位置相对应的其他高速缓存代理的位置，以使目录项进入已知状态。描述和要求保护其他实施例。

6. 发明申请

US20110078492A1 HOME AGENT DATA AND MEMORY MANAGEMENT 失效
标题翻译：家庭代理数据和内存管理
公开(公告)号：US20110078492A1
公开(公告)日：2011-03-31
申请号：US12571381
申请日：2009-09-30
申请人： Ganesh Kumar , Dheemanth Nagaraj , Vincent R. Freytag , Eric Delano , Gregory S. Averill
发明人： Ganesh Kumar , Dheemanth Nagaraj , Vincent R. Freytag , Eric Delano , Gregory S. Averill
IPC分类号： G06F11/00 , G06F12/08 , G06F12/00
CPC分类号： G06F12/0817
摘要： Methods and apparatus relating to home agent data and memory management are described. In one embodiment, a scrubber logic corrects an error at a location in a memory corresponding to a target address by writing back the corrected version of data to the target location. In an embodiment, a map out logic maps out an index or way of a directory cache in response to a number of errors, corresponding to the directory cache, exceeding a threshold value. Other embodiments are also disclosed.
摘要翻译：描述与归属代理数据和存储器管理有关的方法和装置。在一个实施例中，洗涤器逻辑通过将校正的数据版本写回到目标位置来校正与目标地址相对应的存储器中的位置处的错误。在一个实施例中，映射逻辑响应于对应于目录高速缓存的多个错误超过阈值来映射目录高速缓存的索引或方式。还公开了其他实施例。

7. 发明申请

US20140173207A1 Power Gating A Portion Of A Cache Memory 有权
标题翻译：电源门控部分缓存内存
公开(公告)号：US20140173207A1
公开(公告)日：2014-06-19
申请号：US13715613
申请日：2012-12-14
申请人： Ren Wang , Ahmad Samih , Eric Delano , Pinkesh J. Shah , Zeshan A. Chishti , Christian Maciocco , Tsung-Yuan Charlie Tai
发明人： Ren Wang , Ahmad Samih , Eric Delano , Pinkesh J. Shah , Zeshan A. Chishti , Christian Maciocco , Tsung-Yuan Charlie Tai
IPC分类号： G06F12/08
CPC分类号： G06F12/0802 , G06F1/32 , G06F1/3215 , G06F1/3225 , G06F1/3243 , G06F1/3287 , G06F12/0811 , G06F2212/1028 , Y02D10/13
摘要： In an embodiment, a processor includes multiple tiles, each including a core and a tile cache hierarchy. This tile cache hierarchy includes a first level cache, a mid-level cache (MLC) and a last level cache (LLC), and each of these caches is private to the tile. A controller coupled to the tiles includes a cache power control logic to receive utilization information regarding the core and the tile cache hierarchy of a tile and to cause the LLC of the tile to be independently power gated, based at least in part on this information. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括多个瓦片，每个瓦片包括核心和瓦片高速缓存层级。该瓦片高速缓存层级包括第一级高速缓存，中级缓存（MLC）和最后级高速缓存（LLC），并且这些高速缓存中的每一个对于该瓦片是私有的。耦合到瓦片的控制器包括高速缓存功率控制逻辑，用于至少部分地基于该信息来接收关于瓦片的核心和瓦片高速缓存层级的利用信息，并且使瓦片的LLC独立地进行电源门控。描述和要求保护其他实施例。

8. 发明申请

US20050240811A1 Core-level processor lockstepping 有权
标题翻译：核心级处理器锁步
公开(公告)号：US20050240811A1
公开(公告)日：2005-10-27
申请号：US10818975
申请日：2004-04-06
申请人： Kevin Safford , Christopher Lyles , Eric Delano
发明人： Kevin Safford , Christopher Lyles , Eric Delano
IPC分类号： G06F11/18 , G06F11/00 , G06F11/16 , G06F11/20
CPC分类号： G06F11/1679 , G06F11/1641
摘要： A device is provided which includes a first microprocessor core to generate a first output signal; a second microprocessor core to generate a second output signal; a switching fabric having a first input/output port; and lockstep logic, coupled between the first input/output port of the switching fabric and the first and second microprocessor cores, to detect whether the first output signal differs from the second output signal.
摘要翻译：提供一种装置，其包括用于产生第一输出信号的第一微处理器核心; 第二微处理器核心，用于产生第二输出信号; 具有第一输入/输出端口的交换结构; 以及耦合在交换结构的第一输入/输出端口与第一和第二微处理器核心之间的锁步逻辑，以检测第一输出信号是否与第二输出信号不同。

9. 发明申请

US20050138478A1 Error detection method and system for processors that employ alternating threads 审中-公开
标题翻译：使用交替线程的处理器的错误检测方法和系统
公开(公告)号：US20050138478A1
公开(公告)日：2005-06-23
申请号：US10714258
申请日：2003-11-14
申请人： Kevin Safford , Donald Soltis , Stephen Undy , James Gibson , Eric Delano
发明人： Kevin Safford , Donald Soltis , Stephen Undy , James Gibson , Eric Delano
IPC分类号： G06F11/14 , G06F11/00
CPC分类号： G06F11/1497 , G06F9/3861
摘要： Microprocessor that includes a mechanism for detecting soft errors. The processor includes an instruction fetch unit for fetching an instruction and an instruction decoder for decoding the instruction. The mechanism for detecting soft errors includes duplication hardware for duplicating the instruction and comparison hardware. The processor further includes a first execution unit for executing the instruction in a first execution cycle and the duplicated instruction in a second execution cycle. The comparison hardware compares the results of the first execution cycle and the results of the second execution cycle. The comparison hardware can include an exception unit for generating an exception (e.g., raising a fault) when the results are not the same. The processor also includes a commit unit for committing one of the results when the results are the same.
摘要翻译：微处理器，包括检测软错误的机制。处理器包括用于取出指令的指令获取单元和用于解码指令的指令解码器。用于检测软错误的机制包括用于复制指令和比较硬件的复制硬件。处理器还包括用于在第一执行周期中执行指令的第一执行单元和在第二执行周期中的复制指令。比较硬件比较第一个执行周期的结果和第二个执行周期的结果。当结果不相同时，比较硬件可以包括用于产生异常（例如，引起故障）的异常单元。处理器还包括提交单元，用于在结果相同时提交其中一个结果。

10. 发明授权

US08171121B2 Method, system, and apparatus for dynamic reconfiguration of resources 有权
标题翻译：用于动态重新配置资源的方法，系统和装置
公开(公告)号：US08171121B2
公开(公告)日：2012-05-01
申请号：US12236047
申请日：2008-09-23
申请人： Mani Ayyar , Eric Delano , Ioannis T. Schoinas , Akhilesh Kumar , Jay Jayasimha , Jose A. Vargas
发明人： Mani Ayyar , Eric Delano , Ioannis T. Schoinas , Akhilesh Kumar , Jay Jayasimha , Jose A. Vargas
IPC分类号： G06F15/177 , G06F15/76
CPC分类号： G06F9/44505 , G06F9/50 , G06F9/5011 , G06F13/00 , G06F13/24 , G06F13/4081 , G06F13/409
摘要： A dynamic reconfiguration to include on-line addition, deletion, and replacement of individual modules of to support dynamic partitioning of a system, interconnect (link) reconfiguration, memory RAS to allow migration and mirroring without OS intervention, dynamic memory reinterleaving, CPU and socket migration, and support for global shared memory across partitions is described. To facilitate the on-line addition or deletion, the firmware is able to quiesce and de-quiesce the domain of interest so that many system resources, such as routing tables and address decoders, can be updated in what essentially appears to be an atomic operation to the software layer above the firmware.
摘要翻译：动态重新配置，包括单独模块的在线添加，删除和替换，以支持系统的动态分区，互连（链接）重新配置，存储器RAS以允许无OS干预的迁移和镜像，动态内存重新交织，CPU和插座描述了跨分区的全局共享内存的迁移和支持。为了便于在线添加或删除，固件能够静默和解除感兴趣的域，以便许多系统资源（如路由表和地址解码器）可以在基本上看起来是原子操作到固件上方的软件层。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式