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1. 发明申请

US20140189239A1 PROCESSORS HAVING VIRTUALLY CLUSTERED CORES AND CACHE SLICES 审中-公开
标题翻译：具有虚拟聚合的CORES和CACHE SLICES的处理程序
公开(公告)号：US20140189239A1
公开(公告)日：2014-07-03
申请号：US13729579
申请日：2012-12-28
申请人： Herbert H. Hum , Brinda Ganesh , James R. Vash , Ganesh Kumar , Leena K. Puthiyedath , Scott J. Erlanger , Eric J. Dehaemer , Adrian C. Moga , Michelle M. Sebot , Richard L. Carlson , David Bubien , Eric Delano
发明人： Herbert H. Hum , Brinda Ganesh , James R. Vash , Ganesh Kumar , Leena K. Puthiyedath , Scott J. Erlanger , Eric J. Dehaemer , Adrian C. Moga , Michelle M. Sebot , Richard L. Carlson , David Bubien , Eric Delano
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F12/0811 , G06F12/084
摘要： A processor of an aspect includes a plurality of logical processors each having one or more corresponding lower level caches. A shared higher level cache is shared by the plurality of logical processors. The shared higher level cache includes a distributed cache slice for each of the logical processors. The processor includes logic to direct an access that misses in one or more lower level caches of a corresponding logical processor to a subset of the distributed cache slices in a virtual cluster that corresponds to the logical processor. Other processors, methods, and systems are also disclosed.
摘要翻译：一方面的处理器包括多个逻辑处理器，每个逻辑处理器具有一个或多个相应的较低级别的高速缓存。共享的较高级缓存由多个逻辑处理器共享。共享的较高级缓存包括用于每个逻辑处理器的分布式缓存片。处理器包括用于将对应逻辑处理器的一个或多个较低级别高速缓存中的访问指向与对应于逻辑处理器的虚拟集群中的分布式高速缓存片段的子集的逻辑。还公开了其他处理器，方法和系统。

2. 发明申请

US20140181394A1 DIRECTORY CACHE SUPPORTING NON-ATOMIC INPUT/OUTPUT OPERATIONS 有权
标题翻译：目录缓存支持非原始输入/输出操作
公开(公告)号：US20140181394A1
公开(公告)日：2014-06-26
申请号：US13724214
申请日：2012-12-21
申请人： Herbert H. Hum , James R. Vash , Eric A. Gouldey , Ganesh Kumar , David Bubien , Manoj K. Arora , Luke Chang , Lavanya Nama , Mahak Gupta
发明人： Herbert H. Hum , James R. Vash , Eric A. Gouldey , Ganesh Kumar , David Bubien , Manoj K. Arora , Luke Chang , Lavanya Nama , Mahak Gupta
IPC分类号： G06F12/08
CPC分类号： G06F12/082 , G06F12/0824 , G06F12/0833 , G06F12/0835 , G06F2212/1016 , G06F2212/621
摘要： Responsive to receiving a write request for a cache line from an input/output device, a caching agent of a first processor determines that the cache line is managed by a home agent of a second processor. The caching agent sends an ownership request for the cache line to the second processor. A home agent of the second processor receives the ownership request, generates an entry in a directory cache for the cache line, the entry identifying the remote caching agent as having ownership of the cache line, and grants ownership of the cache line to the remote caching agent. Responsive to receiving the grant of ownership for the cache line from the home agent an input/output controller of the first processor adds an entry for the cache line to an input/output write cache, the entry comprising a first indicator that the cache line is managed by the home agent of the second processor.
摘要翻译：响应于从输入/输出设备接收对高速缓存线的写入请求，第一处理器的高速缓存代理器确定高速缓存行由第二处理器的归属代理管理。缓存代理向第二处理器发送高速缓存行的所有权请求。第二处理器的归属代理接收所有权请求，在高速缓存行的目录高速缓存中生成条目，将远程高速缓存代理标识为具有高速缓存行的所有权的条目，并将高速缓存行的所有权授予远程缓存代理商响应于从所述归属代理接收对所述高速缓存行的所有权的许可，所述第一处理器的输入/输出控制器将用于所述高速缓存行的条目添加到输入/输出写入高速缓存，所述条目包括所述高速缓存行是由第二处理器的归属代理管理。

3. 发明授权

US09170946B2 Directory cache supporting non-atomic input/output operations 有权
标题翻译：支持非原子输入/输出操作的目录缓存
公开(公告)号：US09170946B2
公开(公告)日：2015-10-27
申请号：US13724214
申请日：2012-12-21
申请人： Herbert H. Hum , James R. Vash , Eric A. Gouldey , Ganesh Kumar , David Bubien , Manoj K. Arora , Luke Chang , Lavanya Nama , Mahak Gupta
发明人： Herbert H. Hum , James R. Vash , Eric A. Gouldey , Ganesh Kumar , David Bubien , Manoj K. Arora , Luke Chang , Lavanya Nama , Mahak Gupta
IPC分类号： G06F12/08
CPC分类号： G06F12/082 , G06F12/0824 , G06F12/0833 , G06F12/0835 , G06F2212/1016 , G06F2212/621
摘要： Responsive to receiving a write request for a cache line from an input/output device, a caching agent of a first processor determines that the cache line is managed by a home agent of a second processor. The caching agent sends an ownership request for the cache line to the second processor. A home agent of the second processor receives the ownership request, generates an entry in a directory cache for the cache line, the entry identifying the remote caching agent as having ownership of the cache line, and grants ownership of the cache line to the remote caching agent. Responsive to receiving the grant of ownership for the cache line from the home agent an input/output controller of the first processor adds an entry for the cache line to an input/output write cache, the entry comprising a first indicator that the cache line is managed by the home agent of the second processor.
摘要翻译：响应于从输入/输出设备接收对高速缓存线的写入请求，第一处理器的高速缓存代理器确定高速缓存行由第二处理器的归属代理管理。缓存代理向第二处理器发送高速缓存行的所有权请求。第二处理器的归属代理接收所有权请求，在高速缓存行的目录高速缓存中生成条目，将远程高速缓存代理标识为具有高速缓存行的所有权的条目，并将高速缓存行的所有权授予远程缓存代理商响应于从所述归属代理接收对所述高速缓存行的所有权的许可，所述第一处理器的输入/输出控制器将用于所述高速缓存行的条目添加到输入/输出写入高速缓存，所述条目包括所述高速缓存行是由第二处理器的归属代理管理。

4. 发明授权

US08904079B2 Tunneling platform management messages through inter-processor interconnects 有权
标题翻译：隧道平台管理消息通过处理器间互连
公开(公告)号：US08904079B2
公开(公告)日：2014-12-02
申请号：US13532085
申请日：2012-06-25
申请人： Luke Chang , Mahesh S. Natu , James R. Vash , Michelle M. Sebot , Robert J. Safranek
发明人： Luke Chang , Mahesh S. Natu , James R. Vash , Michelle M. Sebot , Robert J. Safranek
IPC分类号： G06F13/20
CPC分类号： G06F13/20 , G06F15/17 , G06F2213/0026
摘要： Methods and apparatus for tunneling platform management messages through inter-processor interconnects. Platform management messages are received from a management entity such as a management engine (ME) at a management component of a first processor targeted for a managed device operatively coupled to a second processor. Management message content is encapsulated in a tunnel message that is tunneled from the first processor to a second management component in the second processor via a socket-to-socket interconnect link between the processors. Once received at the second management component the encapsulated management message content is extracted and the original management message is recreated. The recreated management message is then used to manage the targeted device in a manner similar to if the ME was directly connected to the second processor. The disclosed techniques enable management of platform devices operatively coupled to processors in a multi-processor platform via a single management entity.
摘要翻译：通过处理器互连隧道化平台管理消息的方法和装置。从管理实体（诸如管理引擎（ME））处接收平台管理消息，该管理引擎（ME）处于针对可操作地耦合到第二处理器的被管理设备的第一处理器的管理组件。管理消息内容被封装在隧道消息中，隧道消息通过处理器之间的套接字到套接字互连链路从第一处理器隧道传送到第二处理器中的第二管理组件。一旦在第二管理组件被接收到，则提取封装的管理消息内容，并重新创建原始管理消息。然后，重新创建的管理消息用于以与ME直接连接到第二处理器相似的方式来管理目标设备。所公开的技术使得能够经由单个管理实体来管理与多处理器平台中的处理器可操作地耦合的平台设备。

5. 发明申请

US20130346666A1 TUNNELING PLATFORM MANAGEMENT MESSAGES THROUGH INTER-PROCESSOR INTERCONNECTS 有权
标题翻译：通过互联网互连连接隧道式平台管理信息
公开(公告)号：US20130346666A1
公开(公告)日：2013-12-26
申请号：US13532085
申请日：2012-06-25
申请人： Luke Chang , Mahesh S. Natu , James R. Vash , Michelle M. Sebot , Robert J. Safranek
发明人： Luke Chang , Mahesh S. Natu , James R. Vash , Michelle M. Sebot , Robert J. Safranek
IPC分类号： G06F13/14
CPC分类号： G06F13/20 , G06F15/17 , G06F2213/0026
摘要： Methods and apparatus for tunneling platform management messages through inter-processor interconnects. Platform management messages are received from a management entity such as a management engine (ME) at a management component of a first processor targeted for a managed device operatively coupled to a second processor. Management message content is encapsulated in a tunnel message that is tunneled from the first processor to a second management component in the second processor via a socket-to-socket interconnect link between the processors. Once received at the second management component the encapsulated management message content is extracted and the original management message is recreated. The recreated management message is then used to manage the targeted device in a manner similar to if the ME was directly connected to the second processor. The disclosed techniques enable management of platform devices operatively coupled to processors in a multi-processor platform via a single management entity.
摘要翻译：通过处理器互连隧道化平台管理消息的方法和装置。从管理实体（诸如管理引擎（ME））处接收平台管理消息，该管理引擎（ME）处于针对可操作地耦合到第二处理器的被管理设备的第一处理器的管理组件。管理消息内容被封装在隧道消息中，隧道消息通过处理器之间的套接字到套接字互连链路从第一处理器隧道传送到第二处理器中的第二管理组件。一旦在第二管理组件被接收到，则提取封装的管理消息内容，并重新创建原始管理消息。然后，重新创建的管理消息用于以与ME直接连接到第二处理器相似的方式来管理目标设备。所公开的技术使得能够经由单个管理实体来管理与多处理器平台中的处理器可操作地耦合的平台设备。

6. 发明申请

US20140208141A1 DYNAMICALLY CONTROLLING INTERCONNECT FREQUENCY IN A PROCESSOR 有权
标题翻译：在处理器中动态地控制互连频率
公开(公告)号：US20140208141A1
公开(公告)日：2014-07-24
申请号：US13997386
申请日：2012-03-13
申请人： Malini K. Bhandaru , Ankush Varma , James R. Vash , Monica Wong-Chan , Eric J. Dehaemer , Christopher Allan Poirier, SR. , Scott P. Bobholz
发明人： Malini K. Bhandaru , Ankush Varma , James R. Vash , Monica Wong-Chan , Eric J. Dehaemer , Christopher Allan Poirier, SR. , Scott P. Bobholz
IPC分类号： G06F1/32 , G06F9/38 , G06F12/08
CPC分类号： G06F1/3243 , G06F1/3206 , G06F1/324 , G06F1/3296 , G06F9/3885 , G06F12/0802 , Y02D10/126 , Y02D10/172
摘要： In one embodiment, the present invention includes a method for determining whether a number of stalled cores of a multicore processor is greater than a stall threshold. If so, a recommendation may be made that an operating frequency of system agent circuitry of the processor be increased. Then based on multiple recommendations, a candidate operating frequency of the system agent circuitry can be set. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于确定多核处理器的多个停滞的核心是否大于失速阈值的方法。如果是这样，可以建议增加处理器的系统代理电路的工作频率。然后，基于多个建议，可以设置系统代理电路的候选工作频率。描述和要求保护其他实施例。

7. 发明授权

US09323316B2 Dynamically controlling interconnect frequency in a processor 有权
标题翻译：动态控制处理器中的互连频率
公开(公告)号：US09323316B2
公开(公告)日：2016-04-26
申请号：US13997386
申请日：2012-03-13
申请人： Malini K. Bhandaru , Ankush Varma , James R. Vash , Monica Wong-Chan , Eric J. Dehaemer , Christopher Allan Poirier, Sr. , Scott P. Bobholz
发明人： Malini K. Bhandaru , Ankush Varma , James R. Vash , Monica Wong-Chan , Eric J. Dehaemer , Christopher Allan Poirier, Sr. , Scott P. Bobholz
IPC分类号： G06F1/32 , G06F9/38 , G06F12/08
CPC分类号： G06F1/3243 , G06F1/3206 , G06F1/324 , G06F1/3296 , G06F9/3885 , G06F12/0802 , Y02D10/126 , Y02D10/172
摘要： In one embodiment, the present invention includes a method for determining whether a number of stalled cores of a multicore processor is greater than a stall threshold. If so, a recommendation may be made that an operating frequency of system agent circuitry of the processor be increased. Then based on multiple recommendations, a candidate operating frequency of the system agent circuitry can be set. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于确定多核处理器的多个停滞的核心是否大于失速阈值的方法。如果是这样，可以建议增加处理器的系统代理电路的工作频率。然后，基于多个建议，可以设置系统代理电路的候选工作频率。描述和要求保护其他实施例。

8. 发明申请

US20110161769A1 RETRY BASED PROTOCOL WITH SOURCE/RECEIVER FIFO RECOVERY AND ANTI-STARVATION MECHANISM TO SUPPORT DYNAMIC PIPELINE LENGTHENING FOR ECC ERROR CORRECTION 有权
标题翻译：具有源/接收器FIFO恢复和反作用机制的重新构建协议支持动态管道加密用于ECC错误校正
公开(公告)号：US20110161769A1
公开(公告)日：2011-06-30
申请号：US12978581
申请日：2010-12-26
申请人： James R. Vash , Danielle N. Devereaux , Scott J. Erlanger , Robert E. Faber
发明人： James R. Vash , Danielle N. Devereaux , Scott J. Erlanger , Robert E. Faber
IPC分类号： H04L1/08 , H03M13/05 , G06F11/10 , G06F11/14
CPC分类号： G06F11/10 , G06F11/1443 , H03M13/37 , H03M13/3723 , H03M13/6508 , H04L1/1874
摘要： Methods and apparatus relating to retry based protocol with source/receiver FIFO (First-In, First-Out) buffer recovery and anti-starvation mechanism to support dynamic pipeline lengthening for ECC error correction are described. In an embodiment, upon detection of an error, a portion of transmitted data is stored in one or more storage devices before retransmission. Other embodiments are also described and claimed.
摘要翻译：描述了基于重试协议的方法和设备，具有源/接收器FIFO（先进先出）缓冲器恢复和抗饥饿机制，以支持用于ECC纠错的动态管道延长。在一个实施例中，一旦检测到错误，一部分传输的数据就被重新存储在一个或多个存储设备中。还描述和要求保护其他实施例。

9. 发明授权

US08943379B2 Retry based protocol with source/receiver FIFO recovery and anti-starvation mechanism to support dynamic pipeline lengthening for ECC error correction 有权
标题翻译：具有源/接收器FIFO恢复和抗饥饿机制的基于重试协议，支持动态管道延长用于ECC纠错
公开(公告)号：US08943379B2
公开(公告)日：2015-01-27
申请号：US12978581
申请日：2010-12-26
申请人： James R. Vash , Danielle N. Devereaux , Scott J. Erlanger , Robert E. Faber
发明人： James R. Vash , Danielle N. Devereaux , Scott J. Erlanger , Robert E. Faber
IPC分类号： H03M13/00 , G06F11/10 , H03M13/37 , H04L1/18 , G06F11/14
CPC分类号： G06F11/10 , G06F11/1443 , H03M13/37 , H03M13/3723 , H03M13/6508 , H04L1/1874
摘要： Methods and apparatus relating to retry based protocol with source/receiver FIFO (First-In, First-Out) buffer recovery and anti-starvation mechanism to support dynamic pipeline lengthening for ECC error correction are described. In an embodiment, upon detection of an error, a portion of transmitted data is stored in one or more storage devices before retransmission. Other embodiments are also described and claimed.
摘要翻译：描述了基于重试协议的方法和设备，具有源/接收器FIFO（先进先出）缓冲器恢复和抗饥饿机制，以支持用于ECC纠错的动态管道延长。在一个实施例中，一旦检测到错误，一部分传输的数据就被重新存储在一个或多个存储设备中。还描述和要求保护其他实施例。

10. 发明申请

US20120079032A1 APPARATUS, SYSTEM, AND METHODS FOR FACILITATING ONE-WAY ORDERING OF MESSAGES 有权
标题翻译：设备，系统和方法，促进消息的单向订购
公开(公告)号：US20120079032A1
公开(公告)日：2012-03-29
申请号：US12889802
申请日：2010-09-24
申请人： James R. Vash , Vida Vakilotojar , Bongjin Jung , Yen-Cheng Liu
发明人： James R. Vash , Vida Vakilotojar , Bongjin Jung , Yen-Cheng Liu
IPC分类号： G06F15/16 , G06F5/00 , G06F12/08
CPC分类号： H04L67/10 , G06F15/17325
摘要： Methods, apparatus and systems for facilitating one-way ordering of otherwise independent message classes. A one-way message ordering mechanism facilitates one-way ordering of messages of different message classes sent between interconnects employing independent pathways for the message classes. In one aspect, messages of a second message class may not pass messages of a first message class. Moreover, when messages of the first and second classes are received in sequence, the ordering mechanism ensures that messages of the first class are forwarded to, and received at, a next hop prior to forwarding messages of the second class.
摘要翻译：用于促进独立消息类别的单向排序的方法，装置和系统。单向消息排序机制有助于在使用消息类的独立路径的互连之间发送的不同消息类别的消息的单向排序。在一个方面，第二消息类的消息可能不会传递第一消息类的消息。此外，当顺序地接收到第一类和第二类的消息时，排序机制确保在转发第二类的消息之前将第一类的消息转发到下一跳并在其中接收。

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