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1. 发明申请

US20140189239A1 PROCESSORS HAVING VIRTUALLY CLUSTERED CORES AND CACHE SLICES 审中-公开
标题翻译：具有虚拟聚合的CORES和CACHE SLICES的处理程序
公开(公告)号：US20140189239A1
公开(公告)日：2014-07-03
申请号：US13729579
申请日：2012-12-28
申请人： Herbert H. Hum , Brinda Ganesh , James R. Vash , Ganesh Kumar , Leena K. Puthiyedath , Scott J. Erlanger , Eric J. Dehaemer , Adrian C. Moga , Michelle M. Sebot , Richard L. Carlson , David Bubien , Eric Delano
发明人： Herbert H. Hum , Brinda Ganesh , James R. Vash , Ganesh Kumar , Leena K. Puthiyedath , Scott J. Erlanger , Eric J. Dehaemer , Adrian C. Moga , Michelle M. Sebot , Richard L. Carlson , David Bubien , Eric Delano
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F12/0811 , G06F12/084
摘要： A processor of an aspect includes a plurality of logical processors each having one or more corresponding lower level caches. A shared higher level cache is shared by the plurality of logical processors. The shared higher level cache includes a distributed cache slice for each of the logical processors. The processor includes logic to direct an access that misses in one or more lower level caches of a corresponding logical processor to a subset of the distributed cache slices in a virtual cluster that corresponds to the logical processor. Other processors, methods, and systems are also disclosed.
摘要翻译：一方面的处理器包括多个逻辑处理器，每个逻辑处理器具有一个或多个相应的较低级别的高速缓存。共享的较高级缓存由多个逻辑处理器共享。共享的较高级缓存包括用于每个逻辑处理器的分布式缓存片。处理器包括用于将对应逻辑处理器的一个或多个较低级别高速缓存中的访问指向与对应于逻辑处理器的虚拟集群中的分布式高速缓存片段的子集的逻辑。还公开了其他处理器，方法和系统。

2. 发明申请

US20140181394A1 DIRECTORY CACHE SUPPORTING NON-ATOMIC INPUT/OUTPUT OPERATIONS 有权
标题翻译：目录缓存支持非原始输入/输出操作
公开(公告)号：US20140181394A1
公开(公告)日：2014-06-26
申请号：US13724214
申请日：2012-12-21
申请人： Herbert H. Hum , James R. Vash , Eric A. Gouldey , Ganesh Kumar , David Bubien , Manoj K. Arora , Luke Chang , Lavanya Nama , Mahak Gupta
发明人： Herbert H. Hum , James R. Vash , Eric A. Gouldey , Ganesh Kumar , David Bubien , Manoj K. Arora , Luke Chang , Lavanya Nama , Mahak Gupta
IPC分类号： G06F12/08
CPC分类号： G06F12/082 , G06F12/0824 , G06F12/0833 , G06F12/0835 , G06F2212/1016 , G06F2212/621
摘要： Responsive to receiving a write request for a cache line from an input/output device, a caching agent of a first processor determines that the cache line is managed by a home agent of a second processor. The caching agent sends an ownership request for the cache line to the second processor. A home agent of the second processor receives the ownership request, generates an entry in a directory cache for the cache line, the entry identifying the remote caching agent as having ownership of the cache line, and grants ownership of the cache line to the remote caching agent. Responsive to receiving the grant of ownership for the cache line from the home agent an input/output controller of the first processor adds an entry for the cache line to an input/output write cache, the entry comprising a first indicator that the cache line is managed by the home agent of the second processor.
摘要翻译：响应于从输入/输出设备接收对高速缓存线的写入请求，第一处理器的高速缓存代理器确定高速缓存行由第二处理器的归属代理管理。缓存代理向第二处理器发送高速缓存行的所有权请求。第二处理器的归属代理接收所有权请求，在高速缓存行的目录高速缓存中生成条目，将远程高速缓存代理标识为具有高速缓存行的所有权的条目，并将高速缓存行的所有权授予远程缓存代理商响应于从所述归属代理接收对所述高速缓存行的所有权的许可，所述第一处理器的输入/输出控制器将用于所述高速缓存行的条目添加到输入/输出写入高速缓存，所述条目包括所述高速缓存行是由第二处理器的归属代理管理。

3. 发明授权

US09170946B2 Directory cache supporting non-atomic input/output operations 有权
标题翻译：支持非原子输入/输出操作的目录缓存
公开(公告)号：US09170946B2
公开(公告)日：2015-10-27
申请号：US13724214
申请日：2012-12-21
申请人： Herbert H. Hum , James R. Vash , Eric A. Gouldey , Ganesh Kumar , David Bubien , Manoj K. Arora , Luke Chang , Lavanya Nama , Mahak Gupta
发明人： Herbert H. Hum , James R. Vash , Eric A. Gouldey , Ganesh Kumar , David Bubien , Manoj K. Arora , Luke Chang , Lavanya Nama , Mahak Gupta
IPC分类号： G06F12/08
CPC分类号： G06F12/082 , G06F12/0824 , G06F12/0833 , G06F12/0835 , G06F2212/1016 , G06F2212/621
摘要： Responsive to receiving a write request for a cache line from an input/output device, a caching agent of a first processor determines that the cache line is managed by a home agent of a second processor. The caching agent sends an ownership request for the cache line to the second processor. A home agent of the second processor receives the ownership request, generates an entry in a directory cache for the cache line, the entry identifying the remote caching agent as having ownership of the cache line, and grants ownership of the cache line to the remote caching agent. Responsive to receiving the grant of ownership for the cache line from the home agent an input/output controller of the first processor adds an entry for the cache line to an input/output write cache, the entry comprising a first indicator that the cache line is managed by the home agent of the second processor.
摘要翻译：响应于从输入/输出设备接收对高速缓存线的写入请求，第一处理器的高速缓存代理器确定高速缓存行由第二处理器的归属代理管理。缓存代理向第二处理器发送高速缓存行的所有权请求。第二处理器的归属代理接收所有权请求，在高速缓存行的目录高速缓存中生成条目，将远程高速缓存代理标识为具有高速缓存行的所有权的条目，并将高速缓存行的所有权授予远程缓存代理商响应于从所述归属代理接收对所述高速缓存行的所有权的许可，所述第一处理器的输入/输出控制器将用于所述高速缓存行的条目添加到输入/输出写入高速缓存，所述条目包括所述高速缓存行是由第二处理器的归属代理管理。

4. 发明申请

US20140189417A1 APPARATUS AND METHOD FOR PARTIAL MEMORY MIRRORING 有权
标题翻译：用于部分存储器镜像的装置和方法
公开(公告)号：US20140189417A1
公开(公告)日：2014-07-03
申请号：US13730482
申请日：2012-12-28
申请人： Herbert H. Hum , Ganesh Kumar , Robert C. Swanson , David Bubien
发明人： Herbert H. Hum , Ganesh Kumar , Robert C. Swanson , David Bubien
IPC分类号： G06F11/00 , G06F11/07
CPC分类号： G06F11/004 , G06F11/006 , G06F11/0793 , G06F11/1666
摘要： An apparatus and method are described for performing partial memory mirroring operations. For example, one embodiment of a processor comprises: a processor core for generating a read or write transaction having a system memory address; a home agent identified to service the read or write transaction based on the system memory address; one or more target address decoders (TADs) associated with the home agent to determine whether the system memory address is within a mirrored memory region or a non-mirrored memory region, wherein: if the system memory address is within a mirrored memory region, then the one or more TADs identifying multiple mirrored memory channels for the read or write transaction; and if the system memory address is not within a mirrored memory region, then the one or more TADs identifying a single memory channel for the read or write transaction.
摘要翻译：描述了用于执行部分存储器镜像操作的装置和方法。例如，处理器的一个实施例包括：处理器核，用于产生具有系统存储器地址的读或写事务; 被识别为基于系统存储器地址来服务于读或写事务的归属代理; 与归属代理相关联的一个或多个目标地址解码器（TAD），以确定系统存储器地址是否在镜像存储器区域或非镜像存储器区域内，其中：如果系统存储器地址在镜像存储器区域内，则所述一个或多个TAD识别用于读取或写入事务的多个镜像存储器通道; 并且如果系统存储器地址不在镜像存储器区域内，则该一个或多个标识用于读取或写入事务的单个存储器通道的TAD。

5. 发明申请

US20210004328A1 HARDWARE/SOFTWARE CO-OPTIMIZATION TO IMPROVE PERFORMANCE AND ENERGY FOR INTER-VM COMMUNICATION FOR NFVS AND OTHER PRODUCER-CONSUMER WORKLOADS 有权
公开(公告)号：US20210004328A1
公开(公告)日：2021-01-07
申请号：US17027248
申请日：2020-09-21
申请人： Ren Wang , Andrew J. Herdrich , Yen-cheng Liu , Herbert H. Hum , Jong Soo Park , Christopher J. Hughes , Namakkal N. Venkatesan , Adrian C. Moga , Aamer Jaleel , Zeshan A. Chishti , Mesut A. Ergin , Jr-shian Tsai , Alexander W. Min , Tsung-yuan C. Tai , Christian Maciocco , Rajesh Sankaran
发明人： Ren Wang , Andrew J. Herdrich , Yen-cheng Liu , Herbert H. Hum , Jong Soo Park , Christopher J. Hughes , Namakkal N. Venkatesan , Adrian C. Moga , Aamer Jaleel , Zeshan A. Chishti , Mesut A. Ergin , Jr-shian Tsai , Alexander W. Min , Tsung-yuan C. Tai , Christian Maciocco , Rajesh Sankaran
IPC分类号： G06F12/0842 , G06F12/0831 , G06F12/0893 , G06F12/109 , G06F12/0813 , G06F9/455
摘要： Methods and apparatus implementing Hardware/Software co-optimization to improve performance and energy for inter-VM communication for NFVs and other producer-consumer workloads. The apparatus include multi-core processors with multi-level cache hierarchies including and L1 and L2 cache for each core and a shared last-level cache (LLC). One or more machine-level instructions are provided for proactively demoting cachelines from lower cache levels to higher cache levels, including demoting cachelines from L1/L2 caches to an LLC. Techniques are also provided for implementing hardware/software co-optimization in multi-socket NUMA architecture system, wherein cachelines may be selectively demoted and pushed to an LLC in a remote socket. In addition, techniques are disclosure for implementing early snooping in multi-socket systems to reduce latency when accessing cachelines on remote sockets.

6. 发明申请

US20120079214A1 ALLOCATION AND WRITE POLICY FOR A GLUELESS AREA-EFFICIENT DIRECTORY CACHE FOR HOTLY CONTESTED CACHE LINES 有权
标题翻译：用于高速缓存高速缓存线路的无障碍区域高效目录的分配和写入策略
公开(公告)号：US20120079214A1
公开(公告)日：2012-03-29
申请号：US12890649
申请日：2010-09-25
申请人： Adrian C. Moga , Malcom Mandviwalla , Vedaraman Geetha , Herbert H. Hum
发明人： Adrian C. Moga , Malcom Mandviwalla , Vedaraman Geetha , Herbert H. Hum
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0831 , G06F12/082 , G06F2212/2542
摘要： Methods and apparatus relating to allocation and/or write policy for a glueless area-efficient directory cache for hotly contested cache lines are described. In one embodiment, a directory cache stores data corresponding to a caching status of a cache line. The caching status of the cache line is stored for each of a plurality of caching agents in the system. An write-on-allocate policy is used for the directory cache by using a special state (e.g., snoop-all state) that indicates one or more snoops are to be broadcasted to all agents in the system. Other embodiments are also disclosed.
摘要翻译：描述与用于热挑战的高速缓存行的无胶带区域高效目录高速缓存的分配和/或写入策略有关的方法和装置。在一个实施例中，目录高速缓存存储与高速缓存行的高速缓存状态对应的数据。为系统中的多个缓存代理中的每一个存储缓存行的高速缓存状态。通过使用指示要广播到系统中的所有代理的一个或多个窥探的特殊状态（例如，窥探全状态），对目录高速缓存使用写入分配策略。还公开了其他实施例。

7. 发明申请

US20150178206A1 CACHE COHERENCY APPARATUS AND METHOD MINIMIZING MEMORY WRITEBACK OPERATIONS 有权
标题翻译：高速缓存设备和方法最小化存储器写回操作
公开(公告)号：US20150178206A1
公开(公告)日：2015-06-25
申请号：US14136131
申请日：2013-12-20
申请人： Jeffrey D. Chamberlain , Vedaraman Geetha , Robert G. Blankenship , Yen-Cheng Liu , Adrian C. Moga , Herbert H. Hum , Sailesh Kottapalli
发明人： Jeffrey D. Chamberlain , Vedaraman Geetha , Robert G. Blankenship , Yen-Cheng Liu , Adrian C. Moga , Herbert H. Hum , Sailesh Kottapalli
IPC分类号： G06F12/08
CPC分类号： G06F12/0817 , G06F12/0815
摘要： An apparatus and method for reducing or eliminating writeback operations. For example, one embodiment of a method comprises: detecting a first operation associated with a cache line at a first requestor cache; detecting that the cache line exists in a first cache in a modified (M) state; forwarding the cache line from the first cache to the first requestor cache and storing the cache line in the first requestor cache in a second modified (M′) state; detecting a second operation associated with the cache line at a second requestor; responsively forwarding the cache line from the first requestor cache to the second requestor cache and storing the cache line in the second requestor cache in an owned (O) state if the cache line has not been modified in the first requestor cache; and setting the cache line to a shared (S) state in the first requestor cache.
摘要翻译：一种用于减少或消除写回操作的设备和方法。例如，方法的一个实施例包括：在第一请求者高速缓存处检测与高速缓存行相关联的第一操作; 检测到所述高速缓存行存在于修改（M）状态的第一高速缓存中; 将所述高速缓存行从所述第一高速缓存转发到所述第一请求者高速缓存，并且以第二修改（M'）状态将所述高速缓存行存储在所述第一请求程序高速缓存中; 在第二请求者处检测与所述高速缓存线相关联的第二操作; 响应地将所述高速缓存行从所述第一请求者缓存转发到所述第二请求器高速缓存，并且如果所述高速缓存行尚未在所述第一请求者高速缓存中被修改则将所述高速缓存行存储在所述第二请求程序高速缓存中; 以及将所述高速缓存行设置为所述第一请求者缓存中的共享（S）状态。

8. 发明授权

US08392665B2 Allocation and write policy for a glueless area-efficient directory cache for hotly contested cache lines 有权
标题翻译：一个无缝区域高效的目录缓存的分配和写入策略，用于热烈争议的缓存行
公开(公告)号：US08392665B2
公开(公告)日：2013-03-05
申请号：US12890649
申请日：2010-09-25
申请人： Adrian C. Moga , Malcolm Mandviwalla , Vedaraman Geetha , Herbert H. Hum
发明人： Adrian C. Moga , Malcolm Mandviwalla , Vedaraman Geetha , Herbert H. Hum
IPC分类号： G06F12/00
CPC分类号： G06F12/0831 , G06F12/082 , G06F2212/2542
摘要： Methods and apparatus relating to allocation and/or write policy for a glueless area-efficient directory cache for hotly contested cache lines are described. In one embodiment, a directory cache stores data corresponding to a caching status of a cache line. The caching status of the cache line is stored for each of a plurality of caching agents in the system. An write-on-allocate policy is used for the directory cache by using a special state (e.g., snoop-all state) that indicates one or more snoops are to be broadcasted to all agents in the system. Other embodiments are also disclosed.
摘要翻译：描述与用于热挑战的高速缓存行的无胶带区域高效目录高速缓存的分配和/或写入策略有关的方法和装置。在一个实施例中，目录高速缓存存储与高速缓存行的高速缓存状态对应的数据。为系统中的多个缓存代理中的每一个存储缓存行的高速缓存状态。通过使用指示要广播到系统中的所有代理的一个或多个窥探的特殊状态（例如，窥探全状态），对目录高速缓存使用写入分配策略。还公开了其他实施例。

9. 发明申请

US20110154002A1 Methods And Apparatuses For Efficient Load Processing Using Buffers 有权
标题翻译：使用缓冲器高效加载处理的方法和设备
公开(公告)号：US20110154002A1
公开(公告)日：2011-06-23
申请号：US12640707
申请日：2009-12-17
申请人： Wei Liu , Youfeng Wu , Christopher B. Wilkerson , Herbert H. Hum
发明人： Wei Liu , Youfeng Wu , Christopher B. Wilkerson , Herbert H. Hum
IPC分类号： G06F9/38
CPC分类号： G06F12/0888 , G06F8/4442 , G06F9/30043 , G06F9/3826 , G06F9/383 , Y02D10/13
摘要： Various embodiments of the invention concern methods and apparatuses for power and time efficient load handling. A compiler may identify producer loads, consumer reuse loads, consumer forwarded loads, and producer/consumer hybrid loads. Based on this identification, performance of the load may be efficiently directed to a load value buffer, store buffer, data cache, or elsewhere. Consequently, accesses to cache are reduced, through direct loading from load value buffers and store buffers, thereby efficiently processing the loads.
摘要翻译：本发明的各种实施例涉及用于功率和时间有效的负载处理的方法和装置。编译器可以识别生产者负载，消费者重用负载，消费者转发负载以及生产者/消费者混合负载。基于该识别，可以将负载的性能有效地指向负载值缓冲器，存储缓冲器，数据高速缓存或其他位置。因此，通过从负载值缓冲区和存储缓冲区直接加载，从而降低对高速缓存的访问，从而有效地处理负载。

10. 发明授权

US06922745B2 Method and apparatus for handling locks 有权
标题翻译：处理锁的方法和装置
公开(公告)号：US06922745B2
公开(公告)日：2005-07-26
申请号：US10139215
申请日：2002-05-02
申请人： Harish Kumar , Aravindh Baktha , Mike D. Upton , KS Venkatraman , Herbert H. Hum , Zhongying Zhang
发明人： Harish Kumar , Aravindh Baktha , Mike D. Upton , KS Venkatraman , Herbert H. Hum , Zhongying Zhang
IPC分类号： G06F9/312 , G06F9/318 , G06F9/38 , G06F12/08 , G06F12/14
CPC分类号： G06F9/3836 , G06F9/3004 , G06F9/30087 , G06F9/30181 , G06F9/30185 , G06F9/3834 , G06F9/3851 , G06F9/3855 , G06F9/3857 , G06F12/0815
摘要： A method and device for determining an attribute associated with a locked load instruction and selecting a lock protocol based upon the attribute of the locked load instruction. Also disclosed is a method for concurrently executing the respective lock sequences associated with multiple threads of a processing device.
摘要翻译：一种用于确定与锁定的加载指令相关联的属性并基于所述锁定加载指令的属性来选择锁定协议的方法和装置。还公开了一种用于并行执行与处理装置的多个线程相关联的各个锁定序列的方法。

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