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1. 发明申请

US20120173907A1 METHOD, APPARATUS, AND SYSTEM FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION INCLUDING DYNAMIC C0-STATE CACHE RESIZING 有权
标题翻译：能量效率和能量守恒的方法，装置和系统，包括动态C0状态缓存
公开(公告)号：US20120173907A1
公开(公告)日：2012-07-05
申请号：US13341657
申请日：2011-12-30
申请人： Jaideep MOSES , Rameshkumar G. Illikkal , Ravishankar Iyer , Jared E. Bendt , Sadagopan Srinivasan , Andrew J. Herdrich , Ashish V. Choubal , Avinash N. Ananthakrishnan , Vijay S.R. Degalahal
发明人： Jaideep MOSES , Rameshkumar G. Illikkal , Ravishankar Iyer , Jared E. Bendt , Sadagopan Srinivasan , Andrew J. Herdrich , Ashish V. Choubal , Avinash N. Ananthakrishnan , Vijay S.R. Degalahal
IPC分类号： G06F1/32
CPC分类号： G06F1/3275 , G06F1/3225 , G06F1/3287 , G06F12/0864 , G06F2212/1028 , G06F2212/601 , Y02D10/13 , Y02D10/14 , Y02D10/171
摘要： Embodiments of systems, apparatuses, and methods for energy-efficient operation of a device are described. In some embodiments, a cache performance indicator of a cache is monitored, and a set of one or more cache performance parameters based on the cache performance indicator is determined. The cache is dynamically resized to an optimal cache size based on a comparison of the cache performance parameters to their energy-efficient targets to reduce power consumption.
摘要翻译：描述了用于设备的能量效率操作的系统，装置和方法的实施例。在一些实施例中，监视高速缓存的高速缓存性能指示符，并且确定基于高速缓存性能指示符的一个或多个高速缓存性能参数的集合。基于缓存性能参数与其节能目标的比较来缓存高速缓存大小，以达到最佳高速缓存大小，从而降低功耗。

2. 发明授权

US08984311B2 Method, apparatus, and system for energy efficiency and energy conservation including dynamic C0-state cache resizing 有权
标题翻译：包括动态C0状态缓存调整大小的节能和节能的方法，装置和系统
公开(公告)号：US08984311B2
公开(公告)日：2015-03-17
申请号：US13341657
申请日：2011-12-30
申请人： Jaideep Moses , Rameshkumar G. Illikkal , Ravishankar Iyer , Jared E. Bendt , Sadagopan Srinivasan , Andrew J. Herdrich , Ashish V. Choubal , Avinash N. Ananthakrishnan , Vijay S. R. Degalahal
发明人： Jaideep Moses , Rameshkumar G. Illikkal , Ravishankar Iyer , Jared E. Bendt , Sadagopan Srinivasan , Andrew J. Herdrich , Ashish V. Choubal , Avinash N. Ananthakrishnan , Vijay S. R. Degalahal
IPC分类号： G06F1/26 , G06F1/32
CPC分类号： G06F1/3275 , G06F1/3225 , G06F1/3287 , G06F12/0864 , G06F2212/1028 , G06F2212/601 , Y02D10/13 , Y02D10/14 , Y02D10/171
摘要： Embodiments of systems, apparatuses, and methods for energy-efficient operation of a device are described. In some embodiments, a cache performance indicator of a cache is monitored, and a set of one or more cache performance parameters based on the cache performance indicator is determined. The cache is dynamically resized to an optimal cache size based on a comparison of the cache performance parameters to their energy-efficient targets to reduce power consumption.
摘要翻译：描述了用于设备的能量效率操作的系统，装置和方法的实施例。在一些实施例中，监视高速缓存的高速缓存性能指示符，并且确定基于高速缓存性能指示符的一个或多个高速缓存性能参数的集合。基于缓存性能参数与其节能目标的比较来缓存高速缓存大小，以达到最佳高速缓存大小，从而降低功耗。

3. 发明申请

US20140281457A1 METHOD FOR BOOTING A HETEROGENEOUS SYSTEM AND PRESENTING A SYMMETRIC CORE VIEW 有权
标题翻译：用于打造异质系统并提供对称核心视图的方法
公开(公告)号：US20140281457A1
公开(公告)日：2014-09-18
申请号：US13854001
申请日：2013-03-29
申请人： Elierzer Weissmann , Rinat Rappoport , Michael Mishaeli , Hisham Shafi , Oron Lenz , Jason W. Brandt , Stephen A. Fischer , Bret L. Toll , Inder M. Sodhi , Alon Naveh , Ganapati N. Srinivasa , Ashish V. Choubal , Scott D. Hahn , David A. Koufaty , Russel J. Fenger , Gaurav Khanna , Eugene Gorbatov , Mishali Naik , Andrew J. Herdrich , Abirami Prabhakaran , Sanjeev S. Sahagirdar , Paul Brett , Paolo Narvaez , Andrew D. Henroid , Dheeraj R. Subbareddy
发明人： Elierzer Weissmann , Rinat Rappoport , Michael Mishaeli , Hisham Shafi , Oron Lenz , Jason W. Brandt , Stephen A. Fischer , Bret L. Toll , Inder M. Sodhi , Alon Naveh , Ganapati N. Srinivasa , Ashish V. Choubal , Scott D. Hahn , David A. Koufaty , Russel J. Fenger , Gaurav Khanna , Eugene Gorbatov , Mishali Naik , Andrew J. Herdrich , Abirami Prabhakaran , Sanjeev S. Sahagirdar , Paul Brett , Paolo Narvaez , Andrew D. Henroid , Dheeraj R. Subbareddy
IPC分类号： G06F9/44
CPC分类号： G06F9/4401 , G06F9/45558 , G06F9/5077 , G06F9/5094 , Y02D10/22 , Y02D10/36
摘要： A heterogeneous processor architecture and a method of booting a heterogeneous processor is described. A processor according to one embodiment comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; and a package unit, to enable a bootstrap processor. The bootstrap processor initializes the homogeneous physical processor cores, while the heterogeneous processor presents the appearance of a homogeneous processor to a system firmware interface.
摘要翻译：描述异构处理器架构和启动异构处理器的方法。根据一个实施例的处理器包括：一组大的物理处理器核心; 一组具有相对较低性能处理能力的小物理处理器核和相对于大型物理处理器核的相对较低的功率使用; 以及一个包装单元，用于启用自举处理器。引导处理器初始化同构物理处理器内核，而异构处理器将均匀处理器的外观呈现给系统固件界面。

4. 发明授权

US09250901B2 Execution context swap between heterogeneous functional hardware units 有权
标题翻译：异构功能硬件单元之间执行上下文交换
公开(公告)号：US09250901B2
公开(公告)日：2016-02-02
申请号：US13795338
申请日：2013-03-12
申请人： Inder M. Sodhi , Marc Torrant , Zeev Offen , Michael Mishaeli , Ashish V. Choubal , Jason W. Brandt
发明人： Inder M. Sodhi , Marc Torrant , Zeev Offen , Michael Mishaeli , Ashish V. Choubal , Jason W. Brandt
IPC分类号： G06F9/30 , G06F9/38 , G06F1/32 , G06F9/46
CPC分类号： G06F9/30123 , G06F1/32 , G06F1/3243 , G06F1/3287 , G06F9/3836 , G06F9/461 , Y02D10/152 , Y02D10/171
摘要： Remapping technologies for execution context swap between heterogeneous functional hardware units are described. A computing system includes multiple registers configured to store remote contexts of functional units. A mapping table maps the remote context to the functional units. An execution unit is configured to execute a remapping tool that intercepts an operation to access a remote context of a first functional unit of the plurality of functional units that is taken offline. The remapping tool determines that the first functional unit is remapped to a second functional unit using the mapping table. The operation is performed to access the remote context that is remapped to the second functional unit. The first functional unit and the second functional unit may be heterogeneous functional units.
摘要翻译：描述用于异构功能硬件单元之间执行上下文交换的重新映射技术。计算系统包括配置成存储功能单元的远程上下文的多个寄存器。映射表将远程上下文映射到功能单元。执行单元被配置为执行重新映射工具，该重新映射工具拦截用于访问脱机的多个功能单元中的第一功能单元的远程上下文的操作。重新映射工具确定使用映射表将第一功能单元重新映射到第二功能单元。执行操作以访问被重新映射到第二功能单元的远程上下文。第一功能单元和第二功能单元可以是异构功能单元。

5. 发明授权

US07562158B2 Message context based TCP transmission 失效
标题翻译：基于消息上下文的TCP传输
公开(公告)号：US07562158B2
公开(公告)日：2009-07-14
申请号：US10809077
申请日：2004-03-24
申请人： Hemal V. Shah , Gary Y. Tsao , Ashish V. Choubal , Harlan T. Beverly , Christopher T. Foulds
发明人： Hemal V. Shah , Gary Y. Tsao , Ashish V. Choubal , Harlan T. Beverly , Christopher T. Foulds
IPC分类号： G06F15/16
CPC分类号： H04L49/90 , H04L69/12
摘要： A method and system for transmitting packets. Packets may be transmitted when a protocol control block is copied from a host processing system to a network protocol offload engine. Message information that contains packet payload addresses may be provided to the network protocol offload engine to generate a plurality of message contexts in the offload engine. With the message contexts, protocol processing may be performed at the offload engine while leaving the packet payload in the host memory. Thus, packet payloads may be transmitted directly from the host memory to a network communication link during transmission of the packets by the offload engine. Other embodiments are also described.
摘要翻译：一种用于传输数据包的方法和系统。当协议控制块从主机处理系统复制到网络协议卸载引擎时，可以传送分组。可以将包含分组有效载荷地址的消息信息提供给网络协议卸载引擎，以在卸载引擎中生成多个消息上下文。利用消息上下文，可以在卸载引擎处执行协议处理，同时将分组有效载荷留在主机存储器中。因此，分组有效载荷可以由卸载引擎在分组的传输期间直接从主机存储器发送到网络通信链路。还描述了其它实施例。

6. 发明授权

US09026817B2 Joint optimization of processor frequencies and system sleep states 有权
标题翻译：联合优化处理器频率和系统睡眠状态
公开(公告)号：US09026817B2
公开(公告)日：2015-05-05
申请号：US13538103
申请日：2012-06-29
申请人： Alexander W. Min , Ren Wang , Jr-Shian Tsai , Mesut A. Ergin , Tsung-Yuan C. Tai , Andrew D. Henroid , Ashish V. Choubal , Bruce L. Fleming
发明人： Alexander W. Min , Ren Wang , Jr-Shian Tsai , Mesut A. Ergin , Tsung-Yuan C. Tai , Andrew D. Henroid , Ashish V. Choubal , Bruce L. Fleming
IPC分类号： G06F1/32 , G06F1/00
CPC分类号： G06F1/324 , Y02D10/126 , Y02D50/20
摘要： Systems and methods may provide for identifying a workload cycle for a computing platform, wherein the workload cycle is to include a busy duration and an idle duration. Additionally, platform energy consumption information may be determined for the workload cycle, and a frequency setting may be selected for the busy duration based at least in part on the platform energy consumption information.
摘要翻译：系统和方法可以提供用于识别计算平台的工作负载周期，其中工作负载周期将包括忙持续时间和空闲持续时间。另外，可以针对工作负载周期来确定平台能量消耗信息，并且可以至少部分地基于平台能量消耗信息来选择忙碌持续时间的频率设置。

7. 发明申请

US20140359311A1 Controlling Power Delivery To A Processor Via A Bypass 有权
标题翻译：通过旁路控制处理器的电力输送
公开(公告)号：US20140359311A1
公开(公告)日：2014-12-04
申请号：US13906652
申请日：2013-05-31
申请人： Sanjeev S. Jahagirdar , Satish K. Damaraju , Yun-Han Chen , Ryan D. Wells , Inder M. Sodhi , Vishram Sarurkar , Ken Drottar , Ashish V. Choubal , Rabiul Islam
发明人： Sanjeev S. Jahagirdar , Satish K. Damaraju , Yun-Han Chen , Ryan D. Wells , Inder M. Sodhi , Vishram Sarurkar , Ken Drottar , Ashish V. Choubal , Rabiul Islam
IPC分类号： G06F1/26
CPC分类号： G06F1/26 , G06F1/3243 , G06F1/3296 , G06F9/5094 , Y02D10/152 , Y02D10/172 , Y02D10/22
摘要： In one embodiment, a processor includes a plurality of domains each to operate at an independently controllable voltage and frequency, a plurality of linear regulators each to receive a first voltage from an off-chip source and controllable to provide a regulated voltage to at least one of the plurality of domains, and a plurality of selectors each coupled to one of the domains, where each selector is configured to provide a regulated voltage from one of the linear regulators or a bypass voltage to a corresponding domain. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括多个域，每个域以独立可控的电压和频率工作，多个线性稳压器各自接收来自芯片外源的第一电压并可控制以将调节电压提供给至少一个以及多个选择器，每个选择器都耦合到所述域中的一个，其中每个选择器被配置为从所述线性调节器之一提供调节电压或将旁路电压提供给相应的域。描述和要求保护其他实施例。

8. 发明授权

US07165144B2 Managing input/output (I/O) requests in a cache memory system 有权
标题翻译：在缓存系统中管理输入/输出（I / O）请求
公开(公告)号：US07165144B2
公开(公告)日：2007-01-16
申请号：US10805105
申请日：2004-03-19
申请人： Ashish V. Choubal , Christopher T. Foulds , Madhu R. Gumma , Quang T. Le
发明人： Ashish V. Choubal , Christopher T. Foulds , Madhu R. Gumma , Quang T. Le
IPC分类号： G06F12/00
CPC分类号： G06F12/0835
摘要： Provided are a method, system, and program for managing Input/Output (I/O) requests in a cache memory system. A request is received to data at a memory address in a first memory device, wherein data in the first memory device is cached in a second memory device. A determination is made as to whether to fetch the requested data from the first memory device to cache in the second memory device in response to determining that the requested data is not in the second memory device. The requested data in the first memory device is accessed and the second memory device is bypassed to execute the request in response to determining not to fetch the requested data from the first memory device to cache in the second memory device.
摘要翻译：提供了一种用于管理缓存存储器系统中的输入/输出（I / O）请求的方法，系统和程序。接收到第一存储器设备中的存储器地址上的数据的请求，其中第一存储器设备中的数据被高速缓存在第二存储器设备中。响应于确定所请求的数据不在第二存储器设备中，确定是否从第一存储器设备获取所请求的数据以缓存在第二存储器设备中。响应于确定不从第一存储器设备获取所请求的数据以缓存在第二存储器设备中，访问第一存储器设备中所请求的数据并绕过第二存储器件以执行请求。

9. 发明申请

US20150268711A1 Selecting A Low Power State Based On Cache Flush Latency Determination 有权
标题翻译：基于缓存冲突延迟确定选择低功耗状态
公开(公告)号：US20150268711A1
公开(公告)日：2015-09-24
申请号：US14221696
申请日：2014-03-21
申请人： Sundar Ramani , Arvind Raman , Arvind Mandhani , Ashish V. Choubal , Kalyan Muthukumar , Ajaya V. Durg , Samudyatha Chakki
发明人： Sundar Ramani , Arvind Raman , Arvind Mandhani , Ashish V. Choubal , Kalyan Muthukumar , Ajaya V. Durg , Samudyatha Chakki
IPC分类号： G06F1/32 , G06F12/08
CPC分类号： G06F1/3287 , G06F1/3203 , G06F1/324 , G06F1/3243 , G06F1/3275 , G06F1/3296 , G06F12/0804 , G06F12/0808 , G06F12/0811 , G06F12/0815 , G06F12/0831 , G06F12/084 , G06F12/128 , G06F2212/1028 , G06F2212/314 , G06F2212/621 , G06F2212/69 , Y02D10/126 , Y02D10/13 , Y02D10/14 , Y02D10/152 , Y02D10/172 , Y02D50/20
摘要： In an embodiment, a processor includes a plurality of cores to independently execute instructions, a shared cache coupled to the cores and including a plurality of lines to store data, and a power controller including a low power control logic to calculate a flush latency to flush the shared cache based on a state of the plurality of lines. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括多个核以独立地执行指令，耦合到核的共享高速缓存并且包括多条线来存储数据，以及包括低功率控制逻辑的功率控制器来计算冲洗等待时间所述共享高速缓存基于所述多条线路的状态。描述和要求保护其他实施例。

10. 发明授权

US07761529B2 Method, system, and program for managing memory requests by devices 失效
标题翻译：用于管理设备的内存请求的方法，系统和程序
公开(公告)号：US07761529B2
公开(公告)日：2010-07-20
申请号：US10882560
申请日：2004-06-30
申请人： Ashish V. Choubal , Madhu R. Gumma , Christopher T. Foulds , Mohannad M. Noah
发明人： Ashish V. Choubal , Madhu R. Gumma , Christopher T. Foulds , Mohannad M. Noah
IPC分类号： H04L29/06
CPC分类号： G06F13/1605
摘要： Provided are a method, system, and program for managing memory requests for logic blocks or clients of a device. In one embodiment, busses are separated by the type of data to be carried by the busses. In another aspect, data transfers are decoupled from the memory requests which initiate the data transfers. In another aspect, clients competing for busses are arbitrated and selected memory requests may be provided programmable higher priority than other memory operations of a similar type.
摘要翻译：提供了一种用于管理对设备的逻辑块或客户端的存储器请求的方法，系统和程序。在一个实施例中，总线由总线所承载的数据类型分开。在另一方面，数据传输与启动数据传输的存储器请求分离。在另一方面，对于竞争总线的客户端进行仲裁，并且选择的存储器请求可以被提供为比类似类型的其他存储器操作可编程的更高优先级。

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