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1. 发明申请

US20160283232A1 Instruction and Logic for Speculative Request Support for Prefetching 审中-公开
标题翻译：提取请求支持预取的指令和逻辑
公开(公告)号：US20160283232A1
公开(公告)日：2016-09-29
申请号：US14671569
申请日：2015-03-27
申请人： Raanan Sade , Ryan L. Carlson , Larisa Novakovsky , Erik G. Hallnor , Ravi Rajwar , Roman Dementiev
发明人： Raanan Sade , Ryan L. Carlson , Larisa Novakovsky , Erik G. Hallnor , Ravi Rajwar , Roman Dementiev
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30047 , G06F9/383 , G06F9/3834 , G06F9/3842 , G06F9/46
摘要： A processor includes a core and a prefetcher. The prefetcher includes logic to issue a request for data including a requested prefetch. The core includes logic to receive an indication of the request, determine whether the request is for a restricted region of memory, and, based upon whether the request is for the restricted region of memory, allow or deny the request.
摘要翻译：处理器包括核心和预取器。预取器包括发出对包括请求的预取的数据的请求的逻辑。核心包括用于接收请求的指示的逻辑，确定请求是否是针对存储器的受限区域，以及基于该请求是针对该存储器的受限区域，允许还是拒绝该请求。

2. 发明申请

US20180095759A1 SUSPENDABLE LOAD ADDRESS TRACKING INSIDE TRANSACTIONS 审中-公开
公开(公告)号：US20180095759A1
公开(公告)日：2018-04-05
申请号：US15282011
申请日：2016-09-30
申请人： Raanan Sade , Roman Dementiev , Ravi Rajwar , Ady Tal , Alex Gerber
发明人： Raanan Sade , Roman Dementiev , Ravi Rajwar , Ady Tal , Alex Gerber
IPC分类号： G06F9/30 , G06F12/0855 , G06F12/123 , G06F12/0875
CPC分类号： G06F9/30043 , G06F9/3838 , G06F9/466 , G06F9/467 , G06F12/0857 , G06F12/0862 , G06F12/0875 , G06F12/1027 , G06F12/12 , G06F12/123 , G06F2212/1024 , G06F2212/452 , G06F2212/6022
摘要： Suspendable load address tracking inside transactions is disclosed. An example processing device of implementations of the disclosure includes a transactional memory (TM) read set tracking component circuitry to identify a suspend read tracking instruction within a transaction executed by the processing device, mark load instructions occurring in the transaction subsequent to the identified suspend read tracking instruction with a suspend attribute, wherein the addresses corresponding to the marked load instructions are excluded from a read set maintained for the transaction, identify a resume read tracking instruction within the transaction, and stop marking the load instructions occurring subsequent to the identified resume read tracking instruction with the suspend attribute.

3. 发明授权

US09990287B2 Apparatus and method for memory-hierarchy aware producer-consumer instruction 有权
公开(公告)号：US09990287B2
公开(公告)日：2018-06-05
申请号：US13994122
申请日：2011-12-21
申请人： Shlomo Raikin , Raanan Sade , Robert Valentine , Julius Yuli Mandelblat , Ron Shalev , Larisa Novakovsky
发明人： Shlomo Raikin , Raanan Sade , Robert Valentine , Julius Yuli Mandelblat , Ron Shalev , Larisa Novakovsky
IPC分类号： G06F13/38 , G06T1/20 , G06F12/0811 , G06F9/30 , G06F9/38 , G06F13/16 , G06T1/60 , G09G5/00 , G06F12/0866
CPC分类号： G06F12/0811 , G06F9/30043 , G06F9/30047 , G06F9/30087 , G06F9/3881 , G06F12/0866 , G06F13/1673 , G06F13/38 , G06T1/20 , G06T1/60 , G09G5/006
摘要： An apparatus and method are described for efficiently transferring data from a core of a central processing unit (CPU) to a graphics processing unit (GPU). For example, one embodiment of a method comprises: writing data to a buffer within the core of the CPU until a designated amount of data has been written; upon detecting that the designated amount of data has been written, responsively generating an eviction cycle, the eviction cycle causing the data to be transferred from the buffer to a cache accessible by both the core and the GPU; setting an indication to indicate to the GPU that data is available in the cache; and upon the GPU detecting the indication, providing the data to the GPU from the cache upon receipt of a read signal from the GPU.

4. 发明申请

US20140192069A1 APPARATUS AND METHOD FOR MEMORY-HIERARCHY AWARE PRODUCER-CONSUMER INSTRUCTION 有权
标题翻译：用于记忆级别生产者消费者指令的装置和方法
公开(公告)号：US20140192069A1
公开(公告)日：2014-07-10
申请号：US13994122
申请日：2011-12-21
申请人： Shlomo Raikin , Raanan Sade , Robert Valentine , Julius Yuli Mandelblat , Ron Shalev , Larisa Novakovsky
发明人： Shlomo Raikin , Raanan Sade , Robert Valentine , Julius Yuli Mandelblat , Ron Shalev , Larisa Novakovsky
IPC分类号： G06F13/38 , G06F13/16 , G06T1/60 , G06F12/08 , G06T1/20
CPC分类号： G06F12/0811 , G06F9/30043 , G06F9/30047 , G06F9/30087 , G06F9/3881 , G06F12/0866 , G06F13/1673 , G06F13/38 , G06T1/20 , G06T1/60 , G09G5/006
摘要： An apparatus and method are described for efficiently transferring data from a core of a central processing unit (CPU) to a graphics processing unit (GPU). For example, one embodiment of a method comprises: writing data to a buffer within the core of the CPU until a designated amount of data has been written; upon detecting that the designated amount of data has been written, responsively generating an eviction cycle, the eviction cycle causing the data to be transferred from the buffer to a cache accessible by both the core and the GPU; setting an indication to indicate to the GPU that data is available in the cache; and upon the GPU detecting the indication, providing the data to the GPU from the cache upon receipt of a read signal from the GPU.
摘要翻译：描述了一种有效地将数据从中央处理单元（CPU）的核心传输到图形处理单元（GPU）的装置和方法。例如，一种方法的一个实施例包括：将数据写入CPU的核心内的缓冲器，直到指定的数据量被写入为止; 在检测到指定量的数据已被写入时，响应地产生驱逐周期，驱逐循环使数据从缓冲器传送到可由核心和GPU访问的高速缓存; 设置指示以向GPU指示数据在高速缓存中可用; 并且在GPU检测到指示时，在从GPU接收到读取信号时，从高速缓存提供数据给GPU。

5. 发明申请

US20140122811A1 Method And Apparatus For Error Correction In A Cache 有权
标题翻译：缓存中误差校正的方法和装置
公开(公告)号：US20140122811A1
公开(公告)日：2014-05-01
申请号：US13664682
申请日：2012-10-31
申请人： Stanislav Shwartsman , Raanan Sade , Larisa Novakovsky , Arijit Biswas
发明人： Stanislav Shwartsman , Raanan Sade , Larisa Novakovsky , Arijit Biswas
IPC分类号： G06F12/08
CPC分类号： G06F12/121 , G06F11/1064 , G06F12/0811 , G06F12/0831 , G06F12/084 , G06F2212/1032 , G06T1/20
摘要： A processor includes a core to execute instructions and a cache memory coupled to the core and having a plurality of entries. Each entry of the cache memory may include a data storage including a plurality of data storage portions, each data storage portion to store a corresponding data portion. Each entry may also include a metadata storage to store a plurality of portion modification indicators, each portion modification indicator corresponding to one of the data storage portions. Each portion modification indicator is to indicate whether the data portion stored in the corresponding data storage portion has been modified, independently of cache coherency state information of the entry. Other embodiments are described as claimed.
摘要翻译：处理器包括执行指令的核心和耦合到核心并且具有多个条目的高速缓存存储器。高速缓冲存储器的每个条目可以包括包括多个数据存储部分的数据存储部分，每个数据存储部分存储对应的数据部分。每个条目还可以包括用于存储多个部分修改指示符的元数据存储器，每个部分修改指示符对应于数据存储部分之一。每个部分修改指示符用于指示存储在相应的数据存储部分中的数据部分是否已被修改，而与条目的高速缓存一致性状态信息无关。其他实施例被描述为所要求保护的。

6. 发明申请

US20140208031A1 APPARATUS AND METHOD FOR MEMORY-HIERARCHY AWARE PRODUCER-CONSUMER INSTRUCTIONS 审中-公开
标题翻译：用于记忆级别生产者消费者指令的装置和方法
公开(公告)号：US20140208031A1
公开(公告)日：2014-07-24
申请号：US13994724
申请日：2011-12-21
申请人： Shlomo Raikin , Robert Valentine , Raanan Sade , Julius Yuli Mandelbalt , Ron Shalev , Larisa Novakovsky
发明人： Shlomo Raikin , Robert Valentine , Raanan Sade , Julius Yuli Mandelbalt , Ron Shalev , Larisa Novakovsky
IPC分类号： G06F12/08 , G06T1/60
CPC分类号： G06F12/0811 , G06F9/3828 , G06F9/3891 , G06F12/0891 , G06T1/60
摘要： An apparatus and method are described for efficiently transferring data from a producer core to a consumer core within a central processing unit (CPU). For example, one embodiment of a method comprises: A method for transferring a chunk of data from a producer core of a central processing unit (CPU) to consumer core of the CPU, comprising: writing data to a buffer within the producer core of the CPU until a designated amount of data has been written; upon detecting that the designated amount of data has been written, responsively generating an eviction cycle, the eviction cycle causing the data to be transferred from the fill buffer to a cache accessible by both the producer core and the consumer core; and upon the consumer core detecting that data is available in the cache, providing the data to the consumer core from the cache upon receipt of a read signal from the consumer core.
摘要翻译：描述了一种用于在中央处理单元（CPU）内有效地将数据从生产者核心传送到消费者核心的装置和方法。例如，一种方法的一个实施例包括：一种用于将数据块从中央处理单元（CPU）的生产者核心转移到CPU的消费者核心的方法，包括：将数据写入到所述CPU的生产者核心内的缓冲器 CPU直到指定数据量被写入; 在检测到指定量的数据被写入时，响应地产生驱逐周期，使得将数据从填充缓冲器传送到可由生产者核心和消费者核心访问的高速缓存的逐出循环; 并且在消费者核心检测到数据在高速缓存中可用时，在从消费者核心接收到读取信号时从高速缓存提供数据给消费者核心。

7. 发明授权

US09405545B2 Method and apparatus for cutting senior store latency using store prefetching 有权
标题翻译：使用存储预取来切割高级存储延迟的方法和装置
公开(公告)号：US09405545B2
公开(公告)日：2016-08-02
申请号：US13993508
申请日：2011-12-30
申请人： Stanislav Shwartsman , Melih Ozgul , Sebastien Hily , Shlomo Raikin , Raanan Sade , Ron Shalev
发明人： Stanislav Shwartsman , Melih Ozgul , Sebastien Hily , Shlomo Raikin , Raanan Sade , Ron Shalev
IPC分类号： G06F12/08 , G06F9/38
CPC分类号： G06F9/3814 , G06F9/383 , G06F9/3834 , G06F9/3861 , G06F12/0808 , G06F12/0862 , G06F2212/6028 , G06F2212/62
摘要： In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for cutting senior store latency using store prefetching. For example, in one embodiment, such means may include an integrated circuit or an out of order processor means that processes out of order instructions and enforces in-order requirements for a cache. Such an integrated circuit or out of order processor means further includes means for receiving a store instruction; means for performing address generation and translation for the store instruction to calculate a physical address of the memory to be accessed by the store instruction; and means for executing a pre-fetch for a cache line based on the store instruction and the calculated physical address before the store instruction retires.
摘要翻译：根据本文公开的实施例，提供了使用商店预取来切割高级商店延迟的方法，系统，机制，技术和装置。例如，在一个实施例中，这种装置可以包括集成电路或乱序处理器装置，其处理不一致的指令并对高速缓存执行按顺序的要求。这样的集成电路或不按顺序的处理器装置还包括用于接收存储指令的装置; 用于执行所述存储指令的地址生成和转换以计算由所述存储指令访问的存储器的物理地址的装置; 以及用于在存储指令退出之前基于所述存储指令和所计算的物理地址来执行用于高速缓存行的预取的装置。

8. 发明授权

US08352683B2 Method and system to reduce the power consumption of a memory device 有权
标题翻译：降低存储器件功耗的方法和系统
公开(公告)号：US08352683B2
公开(公告)日：2013-01-08
申请号：US12823047
申请日：2010-06-24
申请人： Ehud Cohen , Oleg Margulis , Raanan Sade , Stanislav Shwartsman
发明人： Ehud Cohen , Oleg Margulis , Raanan Sade , Stanislav Shwartsman
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F1/00
CPC分类号： G06F12/0864 , G06F12/0859 , G06F2212/1028 , G06F2212/6082 , Y02D10/13
摘要： A method and system to reduce the power consumption of a memory device. In one embodiment of the invention, the memory device is a N-way set-associative level one (L1) cache memory and there is logic coupled with the data cache memory to facilitate access to only part of the N-ways of the N-way set-associative L1 cache memory in response to a load instruction or a store instruction. By reducing the number of ways to access the N-way set-associative L1 cache memory for each load or store request, the power requirements of the N-way set-associative L1 cache memory is reduced in one embodiment of the invention. In one embodiment of the invention, when a prediction is made that the accesses to cache memory only requires the data arrays of the N-way set-associative L1 cache memory, the access to the fill buffers are deactivated or disabled.
摘要翻译：一种降低存储器件功耗的方法和系统。在本发明的一个实施例中，存储器件是N路组合关联级（L1）高速缓冲存储器，并且存在与数据高速缓冲存储器耦合的逻辑，以便于仅访问N- 响应于加载指令或存储指令，单向设置关联L1高速缓冲存储器。通过减少针对每个加载或存储请求访问N路组合关联的L1高速缓冲存储器的方法的数量，在本发明的一个实施例中，减少了N路组合关联的L1高速缓冲存储器的功率需求。在本发明的一个实施例中，当预测到对高速缓存存储器的访问仅需要N路组关联的L1高速缓冲存储器的数据阵列时，对填充缓冲器的访问被去激活或禁用。

9. 发明申请

US20140223105A1 METHOD AND APPARATUS FOR CUTTING SENIOR STORE LATENCY USING STORE PREFETCHING 有权
标题翻译：使用商店预购切割高级商店的方法和装置
公开(公告)号：US20140223105A1
公开(公告)日：2014-08-07
申请号：US13993508
申请日：2011-12-30
申请人： Stanislav Shwartsman , Melih Ozgul , Sebastien Hily , Shlomo Raikin , Raanan Sade , Ron Shalev
发明人： Stanislav Shwartsman , Melih Ozgul , Sebastien Hily , Shlomo Raikin , Raanan Sade , Ron Shalev
IPC分类号： G06F9/38 , G06F12/08
CPC分类号： G06F9/3814 , G06F9/383 , G06F9/3834 , G06F9/3861 , G06F12/0808 , G06F12/0862 , G06F2212/6028 , G06F2212/62
摘要： In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for cutting senior store latency using store prefetching. For example, in one embodiment, such means may include an integrated circuit or an out of order processor means that processes out of order instructions and enforces in-order requirements for a cache. Such an integrated circuit or out of order processor means further includes means for receiving a store instruction; means for performing address generation and translation for the store instruction to calculate a physical address of the memory to be accessed by the store instruction; and means for executing a pre-fetch for a cache line based on the store instruction and the calculated physical address before the store instruction retires.
摘要翻译：根据本文公开的实施例，提供了使用商店预取来切割高级商店延迟的方法，系统，机制，技术和装置。例如，在一个实施例中，这种装置可以包括集成电路或乱序处理器装置，其处理不一致的指令并对高速缓存执行按顺序的要求。这样的集成电路或不按顺序的处理器装置还包括用于接收存储指令的装置; 用于执行所述存储指令的地址生成和转换以计算由所述存储指令访问的存储器的物理地址的装置; 以及用于在存储指令退出之前基于所述存储指令和所计算的物理地址来执行用于高速缓存行的预取的装置。

10. 发明申请

US20120072984A1 REGULATING ATOMIC MEMORY OPERATIONS TO PREVENT DENIAL OF SERVICE ATTACK 有权
标题翻译：调整原子性内存操作以防止服务攻击
公开(公告)号：US20120072984A1
公开(公告)日：2012-03-22
申请号：US12887898
申请日：2010-09-22
申请人： MICHAEL S. BAIR , David W. Burns , Robert S. Chappell , Prakash Math , Leslie A. Ong , Pankaj Raghuvanshi , Shlomo Raikin , Raanan Sade , Michael D. Tucknott , Igor Yanover
发明人： MICHAEL S. BAIR , David W. Burns , Robert S. Chappell , Prakash Math , Leslie A. Ong , Pankaj Raghuvanshi , Shlomo Raikin , Raanan Sade , Michael D. Tucknott , Igor Yanover
IPC分类号： G06F21/00
CPC分类号： G06F9/526
摘要： In one embodiment, the present invention includes a method for identifying a termination sequence for an atomic memory operation executed by a first thread, associating a timer with the first thread, and preventing the first thread from execution of a memory cluster operation after completion of the atomic memory operation until a prevention window has passed. This method may be executed by regulation logic associated with a memory execution unit of a processor, in some embodiments. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于识别由第一线程执行的原子存储器操作的终止序列的方法，其将定时器与第一线程相关联，并且在完成第一线程之后防止第一线程执行存储器簇操作原子记忆操作，直到预防窗口过去。在一些实施例中，该方法可以通过与处理器的存储器执行单元相关联的调节逻辑执行。描述和要求保护其他实施例。

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