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1. 发明授权

US08316184B2 Domain-based cache management, including domain event based priority demotion 有权
标题翻译：基于域的缓存管理，包括基于域事件的优先级降级
公开(公告)号：US08316184B2
公开(公告)日：2012-11-20
申请号：US12165350
申请日：2008-06-30
申请人： Zhen Fang , Erik G Hallnor , Nitin B Gupte , Steven Zhang
发明人： Zhen Fang , Erik G Hallnor , Nitin B Gupte , Steven Zhang
IPC分类号： G06F13/00 , G06F13/28 , H04N7/12
CPC分类号： G06F12/0864 , G06F12/126 , H04N19/43 , H04N19/433
摘要： Domain-based cache management methods and systems, including domain event based priority demotion (“EPD”). In EPD, priorities of cached data blocks are demoted upon one or more domain events, such as upon encoding of one or more macroblocks of a video frame. New data blocks may be written over lowest priority cached data blocks. New data blocks may initially be assigned a highest priority. Alternatively, or additionally, one or more new data blocks may initially be assigned one of a plurality of higher priorities based on domain-based information, such as a relative position of a requested data block within a video frame, and/or a relative direction associated with a requested data block. Domain-based cache management may be implemented with one or more other cache management techniques, such as least recently used techniques. Domain-based cache management may be implemented in associative caches, including set associative caches and fully associative caches, and may be implemented with indirect indexing.
摘要翻译：基于域的缓存管理方法和系统，包括基于域事件的优先级降级（EPD）。在EPD中，缓存的数据块的优先级在一个或多个域事件上降级，诸如在对视频帧的一个或多个宏块进行编码时降级。可以在最低优先级的缓存数据块上写入新的数据块。最初可以分配最新的数据块。或者或附加地，一个或多个新数据块可以基于基于域的信息，诸如在视频帧内的所请求的数据块的相对位置和/或相对方向，最初可被分配多个较高优先级中的一个与所请求的数据块相关联。基于域的高速缓存管理可以利用一个或多个其他高速缓存管理技术来实现，诸如最近最少使用的技术。基于域的缓存管理可以在关联高速缓存中实现，包括集合关联高速缓存和完全关联高速缓存，并且可以用间接索引来实现。

2. 发明申请

US20160283232A1 Instruction and Logic for Speculative Request Support for Prefetching 审中-公开
标题翻译：提取请求支持预取的指令和逻辑
公开(公告)号：US20160283232A1
公开(公告)日：2016-09-29
申请号：US14671569
申请日：2015-03-27
申请人： Raanan Sade , Ryan L. Carlson , Larisa Novakovsky , Erik G. Hallnor , Ravi Rajwar , Roman Dementiev
发明人： Raanan Sade , Ryan L. Carlson , Larisa Novakovsky , Erik G. Hallnor , Ravi Rajwar , Roman Dementiev
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30047 , G06F9/383 , G06F9/3834 , G06F9/3842 , G06F9/46
摘要： A processor includes a core and a prefetcher. The prefetcher includes logic to issue a request for data including a requested prefetch. The core includes logic to receive an indication of the request, determine whether the request is for a restricted region of memory, and, based upon whether the request is for the restricted region of memory, allow or deny the request.
摘要翻译：处理器包括核心和预取器。预取器包括发出对包括请求的预取的数据的请求的逻辑。核心包括用于接收请求的指示的逻辑，确定请求是否是针对存储器的受限区域，以及基于该请求是针对该存储器的受限区域，允许还是拒绝该请求。

3. 发明授权

US08392657B2 Monitoring cache usage in a distributed shared cache 有权
标题翻译：监控分布式共享缓存中的缓存使用情况
公开(公告)号：US08392657B2
公开(公告)日：2013-03-05
申请号：US12587670
申请日：2009-10-09
申请人： Li Zhao , Ravishankar Iyer , Rameshkumar G. Illikkal , Erik G. Hallnor , Martin G. Dixon , Donald K. Newell
发明人： Li Zhao , Ravishankar Iyer , Rameshkumar G. Illikkal , Erik G. Hallnor , Martin G. Dixon , Donald K. Newell
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0864
摘要： An apparatus, method, and system are disclosed. In one embodiment the apparatus includes a cache memory, which a number of sets. Each of the sets in the cache memory have several cache lines. The apparatus also includes at least one process resource table. The process resource table maintains a cache line occupancy count of a number of cache lines. Specifically, the cache line occupancy count for each cache line describes the number of cache lines in the cache storing information utilized by a process running on a computer system. Additionally, the process resource table stores the occupancy count of less cache lines than the total number of cache lines in the cache memory.
摘要翻译：公开了一种装置，方法和系统。在一个实施例中，该装置包括多个组的高速缓冲存储器。高速缓冲存储器中的每个集合具有多个高速缓存行。该装置还包括至少一个进程资源表。进程资源表维护多个高速缓存行的高速缓存行占用数。具体地说，每个高速缓存行的高速缓存线占用率表示高速缓存存储由计算机系统上运行的进程使用的信息的高速缓存行数。此外，处理资源表存储比高速缓冲存储器中的高速缓存行总数少的高速缓存行的占用数。

4. 发明授权

US10705961B2 Scalably mechanism to implement an instruction that monitors for writes to an address 有权
公开(公告)号：US10705961B2
公开(公告)日：2020-07-07
申请号：US14040375
申请日：2013-09-27
申请人： Yen-Cheng Liu , Bahaa Fahim , Erik G. Hallnor , Jeffrey D. Chamberlain , Stephen R. Van Doren , Antonio Juan
发明人： Yen-Cheng Liu , Bahaa Fahim , Erik G. Hallnor , Jeffrey D. Chamberlain , Stephen R. Van Doren , Antonio Juan
IPC分类号： G06F12/08 , G06F12/084 , G06F12/0831 , G06F12/0846 , G06F12/0811 , G06F9/00
摘要： A processor includes a cache-side address monitor unit corresponding to a first cache portion of a distributed cache that has a total number of cache-side address monitor storage locations less than a total number of logical processors of the processor. Each cache-side address monitor storage location is to store an address to be monitored. A core-side address monitor unit corresponds to a first core and has a same number of core-side address monitor storage locations as a number of logical processors of the first core. Each core-side address monitor storage location is to store an address, and a monitor state for a different corresponding logical processor of the first core. A cache-side address monitor storage overflow unit corresponds to the first cache portion, and is to enforce an address monitor storage overflow policy when no unused cache-side address monitor storage location is available to store an address to be monitored.

5. 发明申请

US20090292935A1 Method, System and Apparatus for Power Management of a Link Interconnect 有权
标题翻译：链路互连电源管理的方法，系统和设备
公开(公告)号：US20090292935A1
公开(公告)日：2009-11-26
申请号：US12126540
申请日：2008-05-23
申请人： Erik G. Hallnor , Zhen Fang , Hemant G. Rotithor
发明人： Erik G. Hallnor , Zhen Fang , Hemant G. Rotithor
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/3253 , G06F1/3278 , Y02D10/151 , Y02D10/157
摘要： A proposal for power management control of an interconnect structure based on power state transition control. The power state transition is based on generating early warning signals and an idle timeout value setting based on response time and detection of subsequent requests.
摘要翻译：基于功率状态转换控制的互连结构的电源管理控制方案。电源状态转换基于产生预警信号和基于响应时间的空闲超时值设置以及后续请求的检测。

6. 发明授权

US09336156B2 Method and apparatus for cache line state update in sectored cache with line state tracker 有权
标题翻译：线路状态跟踪器的扇区高速缓存行状态更新方法和装置
公开(公告)号：US09336156B2
公开(公告)日：2016-05-10
申请号：US13827271
申请日：2013-03-14
申请人： Zhongying Zhang , Erik G. Hallnor , Stanley S. Kulick , Jeffrey L. Miller
发明人： Zhongying Zhang , Erik G. Hallnor , Stanley S. Kulick , Jeffrey L. Miller
IPC分类号： G06F12/08
CPC分类号： G06F12/0891 , G06F12/0804 , G06F12/0815 , G06F12/0826 , G06F12/0864 , G06F12/0895 , G06F2212/60
摘要： A processing device and method for cache control including tracking updates to the line state of a cache superline are described. In response to a request pertaining to a superline, a cache controller of the processing device can perform one or more read-modify-write (RMW) operations to (a) a line state vector of a line state array and (b) a counter of the line state array. Based on a determination that one or more requests to the superline have completed, the line state vector from the line state array can be written to a tag array. The cache controller can track pending line state updates to a superline outside of the tag array, and a line state update can occur in the cache controller, rather than awaiting completion of all outstanding operations on a superline. Updates to multiple line states can be maintained simultaneously, and up-to-date ECCs computed.
摘要翻译：描述了用于高速缓存控制的处理设备和方法，包括跟踪对高速缓存超线程的线路状态的更新。响应于与超级线相关的请求，处理设备的高速缓存控制器可以执行一个或多个读 - 修改 - 写入（RMW）操作，以（a）线状态阵列的线状态向量和（b）计数器的行状态数组。基于对超线程的一个或多个请求已经完成的确定，来自线状态阵列的线状态向量可以被写入标签阵列。高速缓存控制器可以跟踪到标签阵列之外的超级线路的待处理线路状态更新，并且线路状态更新可能发生在高速缓存控制器中，而不是等待完成超级线上所有未完成的操作。可以同时维护对多行状态的更新，并计算最新的ECC。

7. 发明申请

US20140281251A1 METHOD AND APPARATUS FOR CACHE LINE STATE UPDATE IN SECTORED CACHE WITH LINE STATE TRACKER 有权
标题翻译：使用线状跟踪器在高速缓存中缓存线状态更新的方法和装置
公开(公告)号：US20140281251A1
公开(公告)日：2014-09-18
申请号：US13827271
申请日：2013-03-14
申请人： Zhongying Zhang , Erik G. Hallnor , Stanley S. Kulick , Jeffrey L. Miller
发明人： Zhongying Zhang , Erik G. Hallnor , Stanley S. Kulick , Jeffrey L. Miller
IPC分类号： G06F12/08
CPC分类号： G06F12/0891 , G06F12/0804 , G06F12/0815 , G06F12/0826 , G06F12/0864 , G06F12/0895 , G06F2212/60
摘要： Technologies for tracking updates to the line state of a cache superline are described. In response to a request pertaining to a superline, one or more read-modify-write (RMW) operations to (a) a line state vector of a line state array and (b) a counter of the line state array can be performed. Based on a determination that one or more requests to the superline have completed, the line state vector from the line state array can be written to a tag array.
摘要翻译：描述了用于跟踪对高速缓存超级线路的线路状态的更新的技术。响应于关于超级线的请求，可以执行一个或多个读 - 修改 - 写入（RMW）操作，以（a）线状态阵列的线状态向量和（b）行状态阵列的计数器。基于对超线程的一个或多个请求已经完成的确定，来自线状态阵列的线状态向量可以被写入标签阵列。

8. 发明授权

US08090967B2 Power state transition initiation control of memory interconnect based on early warning signal, memory response time, and wakeup delay 有权
标题翻译：基于预警信号，存储器响应时间和唤醒延迟的存储器互连的功率状态转换启动控制
公开(公告)号：US08090967B2
公开(公告)日：2012-01-03
申请号：US12126540
申请日：2008-05-23
申请人： Erik G. Hallnor , Zhen Fang , Hemant G. Rotithor
发明人： Erik G. Hallnor , Zhen Fang , Hemant G. Rotithor
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/3253 , G06F1/3278 , Y02D10/151 , Y02D10/157
摘要： A proposal for power management control of an interconnect structure based on power state transition control. The power state transition is based on generating early warning signals and an idle timeout value setting based on response time and detection of subsequent requests.
摘要翻译：基于功率状态转换控制的互连结构的电源管理控制方案。电源状态转换基于产生预警信号和基于响应时间的空闲超时值设置以及后续请求的检测。

9. 发明申请

US20110087843A1 Monitoring cache usage in a distributed shared cache 有权
标题翻译：监控分布式共享缓存中的缓存使用情况
公开(公告)号：US20110087843A1
公开(公告)日：2011-04-14
申请号：US12587670
申请日：2009-10-09
申请人： Li Zhao , Ravishankar Iyer , Rameshkumar G. Illikkal , Erik G. Hallnor , Martin G. Dixon , Donald K. Newell
发明人： Li Zhao , Ravishankar Iyer , Rameshkumar G. Illikkal , Erik G. Hallnor , Martin G. Dixon , Donald K. Newell
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0864
摘要： An apparatus, method, and system are disclosed. In one embodiment the apparatus includes a cache memory, which a number of sets. Each of the sets in the cache memory have several cache lines. The apparatus also includes at least one process resource table. The process resource table maintains a cache line occupancy count of a number of cache lines. Specifically, the cache line occupancy count for each cache line describes the number of cache lines in the cache storing information utilized by a process running on a computer system. Additionally, the process resource table stores the occupancy count of less cache lines than the total number of cache lines in the cache memory.
摘要翻译：公开了一种装置，方法和系统。在一个实施例中，该装置包括多个组的高速缓冲存储器。高速缓冲存储器中的每个集合具有多个高速缓存行。该装置还包括至少一个进程资源表。进程资源表维护多个高速缓存行的高速缓存行占用数。具体地说，每个高速缓存行的高速缓存线占用率表示高速缓存存储由计算机系统上运行的进程使用的信息的高速缓存行数。此外，处理资源表存储比高速缓冲存储器中的高速缓存行总数少的高速缓存行的占用数。

10. 发明申请

US20090327611A1 DOMAIN-BASED CACHE MANAGEMENT, INCLUDING DOMAIN EVENT BASED PRIORITY DEMOTION 有权
标题翻译：基于域的高速缓存管理，包括基于优先级的域名活动
公开(公告)号：US20090327611A1
公开(公告)日：2009-12-31
申请号：US12165350
申请日：2008-06-30
申请人： Zhen Fang , Erik G. Hallnor , Nitin B. Gupte , Steven Zhang
发明人： Zhen Fang , Erik G. Hallnor , Nitin B. Gupte , Steven Zhang
IPC分类号： G06F12/08 , H04N7/12
CPC分类号： G06F12/0864 , G06F12/126 , H04N19/43 , H04N19/433
摘要： Domain-based cache management methods and systems, including domain event based priority demotion (“EPD”). In EPD, priorities of cached data blocks are demoted upon one or more domain events, such as upon encoding of one or more macroblocks of a video frame. New data blocks may be written over lowest priority cached data blocks. New data blocks may initially be assigned a highest priority. Alternatively, or additionally, one or more new data blocks may initially be assigned one of a plurality of higher priorities based on domain-based information, such as a relative position of a requested data block within a video frame, and/or a relative direction associated with a requested data block. Domain-based cache management may be implemented with one or more other cache management techniques, such as least recently used techniques. Domain-based cache management may be implemented in associative caches, including set associative caches and fully associative caches, and may be implemented with indirect indexing.
摘要翻译：基于域的缓存管理方法和系统，包括基于域事件的优先级降级（“EPD”）。在EPD中，缓存的数据块的优先级在一个或多个域事件上降级，诸如在对视频帧的一个或多个宏块进行编码时降级。可以在最低优先级的缓存数据块上写入新的数据块。最初可以分配最新的数据块。或者或附加地，一个或多个新数据块可以基于基于域的信息，诸如在视频帧内的所请求的数据块的相对位置和/或相对方向，最初可被分配多个较高优先级中的一个与所请求的数据块相关联。基于域的高速缓存管理可以利用一个或多个其他高速缓存管理技术来实现，诸如最近最少使用的技术。基于域的缓存管理可以在关联高速缓存中实现，包括集合关联高速缓存和完全关联高速缓存，并且可以用间接索引来实现。

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