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1. 发明申请

US20160283232A1 Instruction and Logic for Speculative Request Support for Prefetching 审中-公开
标题翻译：提取请求支持预取的指令和逻辑
公开(公告)号：US20160283232A1
公开(公告)日：2016-09-29
申请号：US14671569
申请日：2015-03-27
申请人： Raanan Sade , Ryan L. Carlson , Larisa Novakovsky , Erik G. Hallnor , Ravi Rajwar , Roman Dementiev
发明人： Raanan Sade , Ryan L. Carlson , Larisa Novakovsky , Erik G. Hallnor , Ravi Rajwar , Roman Dementiev
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30047 , G06F9/383 , G06F9/3834 , G06F9/3842 , G06F9/46
摘要： A processor includes a core and a prefetcher. The prefetcher includes logic to issue a request for data including a requested prefetch. The core includes logic to receive an indication of the request, determine whether the request is for a restricted region of memory, and, based upon whether the request is for the restricted region of memory, allow or deny the request.
摘要翻译：处理器包括核心和预取器。预取器包括发出对包括请求的预取的数据的请求的逻辑。核心包括用于接收请求的指示的逻辑，确定请求是否是针对存储器的受限区域，以及基于该请求是针对该存储器的受限区域，允许还是拒绝该请求。

2. 发明授权

US08443151B2 Prefetch optimization in shared resource multi-core systems 失效
标题翻译：在共享资源多核系统中预取优化
公开(公告)号：US08443151B2
公开(公告)日：2013-05-14
申请号：US12614619
申请日：2009-11-09
申请人： Puqi P. Tang , Hemant G. Rotithor , Ryan L. Carlson , Nagi Aboulenein
发明人： Puqi P. Tang , Hemant G. Rotithor , Ryan L. Carlson , Nagi Aboulenein
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/0862 , G06F15/8069 , G06F2212/502 , Y02D10/13
摘要： An apparatus and method is described herein for optimization to prefetch throttling, which potentially enhances performance, reduces power consumption, and maintains positive gain for workloads that benefit from prefetching. More specifically, the optimizations described herein allow for bandwidth congestion and prefetch accuracy to be taken into account as feedbacks for throttling at the source of prefetch generation. As a result, when there is low congestion, full prefetch generation is allowed, even if the prefetch is inaccurate, since there is available bandwidth. However, when congestion is high, the determination of throttling falls to prefetch accuracy. If accuracy is high—miss rate is low—then less throttling is needed, because the prefetches are being utilized—performance is being enhanced. Yet, if prefetch accuracy is low—miss rate is high—then more prefetch throttling is needed to save power, because the prefetch are not being utilized—performance is not being enhanced by the large number of prefetches.
摘要翻译：本文描述了用于优化预取节流的装置和方法，其潜在地增强了性能，降低了功耗，并为从预取中受益的工作负载保持了正增益。更具体地说，这里描述的优化允许考虑带宽拥塞和预取精度作为用于在预取生成源处节流的反馈。结果，当拥塞低时，即使预取不准确，由于存在可用带宽，因此允许完全预取生成。然而，当拥塞较高时，节流的确定下降到预取精度。如果精度高，错失率低，则需要较少的节流，因为预取已被利用 - 性能正在提高。然而，如果预取精度低错过率高，则需要更多的预取节流来节省功率，因为预取不被利用 - 性能并没有被大量预取提高。

3. 发明授权

US08800926B2 Radio frequency shielding apparatus system and method 有权
标题翻译：射频屏蔽装置系统及方法
公开(公告)号：US08800926B2
公开(公告)日：2014-08-12
申请号：US11812300
申请日：2007-06-18
申请人： Kenneth P. Kirchoff , Patrick M. Njeim , Thomas K. Morrow , Joel J. Peterson , Michael R. Sirkis , Ryan L. Carlson , Bruce J. Donham , Jim Sears
发明人： Kenneth P. Kirchoff , Patrick M. Njeim , Thomas K. Morrow , Joel J. Peterson , Michael R. Sirkis , Ryan L. Carlson , Bruce J. Donham , Jim Sears
IPC分类号： B64C1/14
CPC分类号： B64C1/1484 , B64C1/1492 , B64D2045/006 , H05K9/0018
摘要： A system for shielding an aircraft from electromagnetic energy includes a fuselage, aperture, window mounting, and window plug. The fuselage provides an electrically conductive envelope. The aperture is disposed in the fuselage. The window mounting spans the aperture. The window plug spans the aperture. The window mounting and the window plug are electrically coupled to the fuselage and provide an electrical path spanning the aperture.
摘要翻译：用于屏蔽飞行器免受电磁能的系统包括机身，孔，窗安装和窗口塞。机身提供导电外壳。孔径设置在机身中。窗户安装横跨孔。窗口插头跨越光圈。窗户安装件和窗户插头电耦合到机身并提供跨越孔的电路径。

4. 发明授权

US07913385B2 Method of attenuating electromagnetic energy 有权
标题翻译：衰减电磁能的方法
公开(公告)号：US07913385B2
公开(公告)日：2011-03-29
申请号：US11292309
申请日：2005-12-02
申请人： Ryan L. Carlson , Bruce J. Donham , Jim Sears
发明人： Ryan L. Carlson , Bruce J. Donham , Jim Sears
IPC分类号： H01B19/00
CPC分类号： B64C1/1492 , Y10T29/49128 , Y10T29/4913 , Y10T29/49135 , Y10T29/49146 , Y10T29/49155 , Y10T29/49227
摘要： To attenuate electromagnetic energy, a capacitive bond between a window and a frame is provided by a capacitive coupling. This capacitive coupling includes an elastomeric matrix and a conductive media. The elastomeric matrix provides a seal between the window and the frame. The conductive media is bound to the matrix and conducts electromagnetic energy from the window to the frame.
摘要翻译：为了衰减电磁能量，通过电容耦合提供窗口和框架之间的电容性接合。该电容耦合包括弹性体基体和导电介质。弹性体基体在窗户和框架之间提供密封。导电介质与矩阵结合，并将电磁能从窗口传导到框架。

5. 发明申请

US20070137117A1 Conductive gasket apparatus and method 有权
标题翻译：导电垫片装置及方法
公开(公告)号：US20070137117A1
公开(公告)日：2007-06-21
申请号：US11292309
申请日：2005-12-02
申请人： Ryan L. Carlson , Bruce J. Donham , Jim Sears
发明人： Ryan L. Carlson , Bruce J. Donham , Jim Sears
IPC分类号： E06B1/04
CPC分类号： B64C1/1492 , Y10T29/49128 , Y10T29/4913 , Y10T29/49135 , Y10T29/49146 , Y10T29/49155 , Y10T29/49227
摘要： To attenuate electromagnetic energy, a capacitive bond between a window and a frame is provided by a capacitive coupling. This capacitive coupling includes an elastomeric matrix and a conductive media. The elastomeric matrix provides a seal between the window and the frame. The conductive media is bound to the matrix and conducts electromagnetic energy from the window to the frame.
摘要翻译：为了衰减电磁能量，通过电容耦合提供窗口和框架之间的电容性接合。该电容耦合包括弹性体基体和导电介质。弹性体基体在窗户和框架之间提供密封。导电介质与矩阵结合，并将电磁能从窗口传导到框架。

6. 发明授权

US08631207B2 Cache memory power reduction techniques 有权
标题翻译：高速缓存存储器功耗缩减技术
公开(公告)号：US08631207B2
公开(公告)日：2014-01-14
申请号：US12647461
申请日：2009-12-26
申请人： Zhen Fang , Meenakshisundara R. Chinthamani , Li Zhao , Milind B. Kamble , Ravishankar Iyer , Seung Eun Lee , Robert S. Chappell , Ryan L. Carlson
发明人： Zhen Fang , Meenakshisundara R. Chinthamani , Li Zhao , Milind B. Kamble , Ravishankar Iyer , Seung Eun Lee , Robert S. Chappell , Ryan L. Carlson
IPC分类号： G06F12/00
CPC分类号： G06F12/0864 , G06F1/3225 , G06F1/3275 , G06F12/0895 , G06F2212/1028 , Y02D10/13 , Y02D10/14
摘要： Methods and apparatus to provide for power consumption reduction in memories (such as cache memories) are described. In one embodiment, a virtual tag is used to determine whether to access a cache way. The virtual tag access and comparison may be performed earlier in the read pipeline than the actual tag access or comparison. In another embodiment, a speculative way hit may be used based on pre-ECC partial tag match to wake up a subset of data arrays. Other embodiments are also described.
摘要翻译：描述了提供存储器（诸如高速缓存存储器）中的功耗降低的方法和装置。在一个实施例中，使用虚拟标签来确定是否访问缓存方式。虚拟标签访问和比较可以在读取管道中比实际标签访问或比较更早地进行。在另一个实施例中，可以基于ECC前部分标签匹配来使用推测方式命中来唤醒数据阵列的子集。还描述了其它实施例。

7. 发明申请

US20110113199A1 PREFETCH OPTIMIZATION IN SHARED RESOURCE MULTI-CORE SYSTEMS 失效
标题翻译：共享资源多核系统中的优选优化
公开(公告)号：US20110113199A1
公开(公告)日：2011-05-12
申请号：US12614619
申请日：2009-11-09
申请人： Puqi P. Tang , Hemant G. Rotithor , Ryan L. Carlson , Nagi Aboulenein
发明人： Puqi P. Tang , Hemant G. Rotithor , Ryan L. Carlson , Nagi Aboulenein
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0862 , G06F15/8069 , G06F2212/502 , Y02D10/13
摘要： An apparatus and method is described herein for optimization to prefetch throttling, which potentially enhances performance, reduces power consumption, and maintains positive gain for workloads that benefit from prefetching. More specifically, the optimizations described herein allow for bandwidth congestion and prefetch accuracy to be taken into account as feedbacks for throttling at the source of prefetch generation. As a result, when there is low congestion, full prefetch generation is allowed, even if the prefetch is inaccurate, since there is available bandwidth. However, when congestion is high, the determination of throttling falls to prefetch accuracy. If accuracy is high—miss rate is low—then less throttling is needed, because the prefetches are being utilized—performance is being enhanced. Yet, if prefetch accuracy is low—miss rate is high—then more prefetch throttling is needed to save power, because the prefetch are not being utilized—performance is not being enhanced by the large number of prefetches.
摘要翻译：本文描述了用于优化预取节流的装置和方法，其潜在地增强了性能，降低了功耗，并为从预取中受益的工作负载保持了正增益。更具体地说，这里描述的优化允许考虑带宽拥塞和预取精度作为用于在预取生成源处节流的反馈。结果，当拥塞低时，即使预取不准确，由于存在可用带宽，因此允许完全预取生成。然而，当拥塞较高时，节流的确定下降到预取精度。如果精度高，错失率低，则需要较少的节流，因为预取已被利用 - 性能正在提高。然而，如果预取精度低错过率高，则需要更多的预取节流来节省功率，因为预取不被利用 - 性能并没有被大量预取提高。

8. 发明申请

US20150346804A1 METHOD, APPARATUS, AND SYSTEM FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION INCLUDING DETECTING AND CONTROLLING CURRENT RAMPS IN PROCESSING CIRCUIT 有权
标题翻译：用于能源效率和能源保护的方法，装置和系统，包括检测和控制处理电路中的电流RAM
公开(公告)号：US20150346804A1
公开(公告)日：2015-12-03
申请号：US14823994
申请日：2015-08-11
申请人： Anupama Suryanarayanan , Matthew C. Merten , Ryan L. Carlson , Stephen H. Gunther
发明人： Anupama Suryanarayanan , Matthew C. Merten , Ryan L. Carlson , Stephen H. Gunther
IPC分类号： G06F1/32
CPC分类号： G06F1/3243 , Y02D10/152
摘要： Some implementations provide techniques and arrangements for adjusting a rate at which operations are performed by a processor based on a comparison of a first indication of power consumed by the processor as a result of performing a first set of operations and a second indication of power consumed by the processor as a result of performing a second set of operations. The rate at which operations are performed by the processor may be adjusted when the comparison indicates that a difference between the first indication of power consumed by the processor and the second indication of power consumed by the processor is greater than a threshold value.
摘要翻译：一些实施方案提供了用于调整由处理器执行操作的速率的技术和布置，其基于由执行第一组操作的结果和由处理器消耗的功率的第二指示来比较由处理器消耗的功率的第一指示作为执行第二组操作的结果的处理器。当比较指示处理器消耗的功率的第一指示与处理器消耗的功率的第二指示之间的差异大于阈值时，可以调整由处理器执行操作的速率。

9. 发明申请

US20120221871A1 METHOD, APPARATUS, AND SYSTEM FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION INCLUDING DETECTING AND CONTROLLING CURRENT RAMPS IN PROCESSING CIRCUIT 有权
标题翻译：用于能源效率和能源保护的方法，装置和系统，包括检测和控制处理电路中的电流RAM
公开(公告)号：US20120221871A1
公开(公告)日：2012-08-30
申请号：US13340511
申请日：2011-12-29
申请人： Anupama Suryanarayanan , Matthew C. Merten , Ryan L. Carlson , Stephen H. Gunther
发明人： Anupama Suryanarayanan , Matthew C. Merten , Ryan L. Carlson , Stephen H. Gunther
IPC分类号： G06F1/32
CPC分类号： G06F1/3243 , Y02D10/152
摘要： Some implementations provide techniques and arrangements for adjusting a rate at which operations are performed by a processor based on a comparison of a first indication of power consumed by the processor as a result of performing a first set of operations and a second indication of power consumed by the processor as a result of performing a second set of operations. The rate at which operations are performed by the processor may be adjusted when the comparison indicates that a difference between the first indication of power consumed by the processor and the second indication of power consumed by the processor is greater than a threshold value.
摘要翻译：一些实施方案提供了用于调整由处理器执行操作的速率的技术和布置，其基于由执行第一组操作的结果和由处理器消耗的功率的第二指示来比较由处理器消耗的功率的第一指示作为执行第二组操作的结果的处理器。当比较指示处理器消耗的功率的第一指示与处理器消耗的功率的第二指示之间的差异大于阈值时，可以调整由处理器执行操作的速率。

10. 发明申请

US20110161595A1 CACHE MEMORY POWER REDUCTION TECHNIQUES 有权
标题翻译：缓存记忆功率降低技术
公开(公告)号：US20110161595A1
公开(公告)日：2011-06-30
申请号：US12647461
申请日：2009-12-26
申请人： Zhen Fang , Meenakshisundara R. Chinthamani , Li Zhao , Milind B. Kamble , Ravishankar Iyer , Seung Eun Lee , Robert S. Chappell , Ryan L. Carlson
发明人： Zhen Fang , Meenakshisundara R. Chinthamani , Li Zhao , Milind B. Kamble , Ravishankar Iyer , Seung Eun Lee , Robert S. Chappell , Ryan L. Carlson
IPC分类号： G06F12/08 , G06F12/00 , G06F1/32
CPC分类号： G06F12/0864 , G06F1/3225 , G06F1/3275 , G06F12/0895 , G06F2212/1028 , Y02D10/13 , Y02D10/14
摘要： Methods and apparatus to provide for power consumption reduction in memories (such as cache memories) are described. In one embodiment, a virtual tag is used to determine whether to access a cache way. The virtual tag access and comparison may be performed earlier in the read pipeline than the actual tag access or comparison. In another embodiment, a speculative way hit may be used based on pre-ECC partial tag match to wake up a subset of data arrays. Other embodiments are also described.
摘要翻译：描述了提供存储器（诸如高速缓存存储器）中的功耗降低的方法和装置。在一个实施例中，使用虚拟标签来确定是否访问缓存方式。虚拟标签访问和比较可以在读取管道中比实际标签访问或比较更早地进行。在另一个实施例中，可以基于ECC前部分标签匹配来使用推测方式命中来唤醒数据阵列的子集。还描述了其它实施例。

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