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1. 发明授权

US09268596B2 Instruction and logic to test transactional execution status 有权
标题翻译：测试事务执行状态的指令和逻辑
公开(公告)号：US09268596B2
公开(公告)日：2016-02-23
申请号：US13538951
申请日：2012-06-29
申请人： Ravi Rajwar , Bret L. Toll , Konrad K. Lai , Matthew C. Merten , Martin G. Dixon
发明人： Ravi Rajwar , Bret L. Toll , Konrad K. Lai , Matthew C. Merten , Martin G. Dixon
IPC分类号： G06F9/46 , G06F9/38 , G06F9/30
CPC分类号： G06F11/28 , G06F9/30047 , G06F9/30076 , G06F9/30087 , G06F9/3009 , G06F9/30098 , G06F9/30145 , G06F9/3016 , G06F9/3802 , G06F9/3834 , G06F9/384 , G06F9/3842 , G06F9/466 , G06F9/467 , G06F11/1407 , G06F11/2236 , G06F11/25 , G06F11/263 , G06F12/0811 , G06F12/0828 , G06F12/084 , G06F12/0862 , G06F12/0875 , G06F12/0897 , G06F2212/1032 , G06F2212/20 , G06F2212/283 , G06F2212/314 , G06F2212/452 , G06F2212/602 , G06F2212/608 , G06F2212/621 , G11C7/1072
摘要： Novel instructions, logic, methods and apparatus are disclosed to test transactional execution status. Embodiments include decoding a first instruction to start a transactional region. Responsive to the first instruction, a checkpoint for a set of architecture state registers is generated and memory accesses from a processing element in the transactional region associated with the first instruction are tracked. A second instruction to detect transactional execution of the transactional region is then decoded. An operation is executed, responsive to decoding the second instruction, to determine if an execution context of the second instruction is within the transactional region. Then responsive to the second instruction, a first flag is updated. In some embodiments, a register may optionally be updated and/or a second flag may optionally be updated responsive to the second instruction.
摘要翻译：公开了新的指令，逻辑，方法和装置来测试事务执行状态。实施例包括解码第一指令以启动事务区域。响应于第一指令，生成一组架构状态寄存器的检查点，并跟踪与第一指令相关联的事务区域中的处理元件的存储器访问。然后解码用于检测事务区域的事务执行的第二指令。执行对第二指令的解码的操作，以确定第二指令的执行上下文是否在事务区域内。然后响应于第二指令，更新第一标志。在一些实施例中，可以可选地更新寄存器和/或响应于第二指令任选地更新第二标志。

2. 发明申请

US20130205119A1 INSTRUCTION AND LOGIC TO TEST TRANSACTIONAL EXECUTION STATUS 有权
标题翻译：指令和逻辑测试交易执行状态
公开(公告)号：US20130205119A1
公开(公告)日：2013-08-08
申请号：US13538951
申请日：2012-06-29
申请人： Ravi Rajwar , Bret L. Toll , Konrad K. Lai , Matthew C. Merten , Martin G. Dixon
发明人： Ravi Rajwar , Bret L. Toll , Konrad K. Lai , Matthew C. Merten , Martin G. Dixon
IPC分类号： G06F9/46
CPC分类号： G06F11/28 , G06F9/30047 , G06F9/30076 , G06F9/30087 , G06F9/3009 , G06F9/30098 , G06F9/30145 , G06F9/3016 , G06F9/3802 , G06F9/3834 , G06F9/384 , G06F9/3842 , G06F9/466 , G06F9/467 , G06F11/1407 , G06F11/2236 , G06F11/25 , G06F11/263 , G06F12/0811 , G06F12/0828 , G06F12/084 , G06F12/0862 , G06F12/0875 , G06F12/0897 , G06F2212/1032 , G06F2212/20 , G06F2212/283 , G06F2212/314 , G06F2212/452 , G06F2212/602 , G06F2212/608 , G06F2212/621 , G11C7/1072
摘要： Novel instructions, logic, methods and apparatus are disclosed to test transactional execution status. Embodiments include decoding a first instruction to start a transactional region. Responsive to the first instruction, a checkpoint for a set of architecture state registers is generated and memory accesses from a processing element in the transactional region associated with the first instruction are tracked. A second instruction to detect transactional execution of the transactional region is then decoded. An operation is executed, responsive to decoding the second instruction, to determine if an execution context of the second instruction is within the transactional region. Then responsive to the second instruction, a first flag is updated. In some embodiments, a register may optionally be updated and/or a second flag may optionally be updated responsive to the second instruction.
摘要翻译：公开了新的指令，逻辑，方法和装置来测试事务执行状态。实施例包括解码第一指令以启动事务区域。响应于第一指令，生成一组架构状态寄存器的检查点，并跟踪与第一指令相关联的事务区域中的处理元件的存储器访问。然后解码用于检测事务区域的事务执行的第二指令。执行对第二指令的解码的操作，以确定第二指令的执行上下文是否在事务区域内。然后响应于第二指令，更新第一标志。在一些实施例中，可以可选地更新寄存器和/或响应于第二指令任选地更新第二标志。

3. 发明申请

US20150032998A1 METHOD, APPARATUS, AND SYSTEM FOR TRANSACTIONAL SPECULATION CONTROL INSTRUCTIONS 审中-公开
标题翻译：方法，装置和系统的交互式分析控制指令
公开(公告)号：US20150032998A1
公开(公告)日：2015-01-29
申请号：US13997243
申请日：2012-02-02
申请人： Ravi Rajwar , Martin G. Dixon , Konrad K. Lai , Alexandre J. Farcy , Bret L. Toll , Robert S. Chappell , Matthew C. Merten , Rajesh S. Parthasarathy , Per Hammarlund
发明人： Ravi Rajwar , Martin G. Dixon , Konrad K. Lai , Alexandre J. Farcy , Bret L. Toll , Robert S. Chappell , Matthew C. Merten , Rajesh S. Parthasarathy , Per Hammarlund
IPC分类号： G06F9/30
CPC分类号： G06F9/30181 , G06F9/3004 , G06F9/30087 , G06F9/30145 , G06F9/3834 , G06F9/3851 , G06F9/3859
摘要： An apparatus and method is described herein for providing speculation control instructions. An xAcquire and xRelease instruction are provided to define a critical section. In one embodiment, the xAcquire instruction includes a lock instruction with an elision prefix and the xRelease instruction includes a lock release instruction with an elision prefix. As a result, a processor is able to elide locks and transactionally execute a critical section defined in software by xAcquire and xRelease. But by adding only prefix hints, legacy processor are able to execute the same code by just ignoring the hints and executing the critical section traditionally with locks to guarantee mutual exclusion. Moreover, xBegin and xEnd are similarly provided for in an Instruction Set Architecture (ISA) to define a transactional code region. In addition, other control speculation instructions, such as xAbort to enable explicit abort of a critical or transactional code section and xTest to test a state of speculative execution is also provided in the ISA.
摘要翻译：这里描述了一种用于提供猜测控制指令的装置和方法。提供xAcquire和xRelease指令来定义关键部分。在一个实施例中，xAcquire指令包括具有检验前缀的锁定指令，并且xRelease指令包括具有检验前缀的锁定释放指令。因此，处理器能够通过xAcquire和xRelease来删除锁定和事务性地执行在软件中定义的关键部分。但是通过仅添加前缀提示，传统处理器能够通过忽略提示并执行传统的锁定关键部分来保证互斥，从而执行相同的代码。此外，xBegin和xEnd在指令集架构（ISA）中类似地提供以定义事务代码区域。此外，还在ISA中提供了其他控制推测指令，例如xAbort，以实现关键或事务代码段的显示中止，以及xTest测试推测执行状态。

4. 发明申请

US20140379996A1 METHOD, APPARATUS, AND SYSTEM FOR TRANSACTIONAL SPECULATION CONTROL INSTRUCTIONS 审中-公开
标题翻译：方法，装置和系统的交互式分析控制指令
公开(公告)号：US20140379996A1
公开(公告)日：2014-12-25
申请号：US13997245
申请日：2012-02-02
申请人： Ravi Rajwar , Martin G. Dixon , Konrad K. Lai , Robert S. Chappell , Bret L. Toll
发明人： Ravi Rajwar , Martin G. Dixon , Konrad K. Lai , Robert S. Chappell , Bret L. Toll
IPC分类号： G06F9/52 , G06F12/08 , G06F9/46
摘要： An apparatus and method is described herein for providing speculative escape instructions. Specifically, an explicit non-transactional load operation is described herein. During execution of a speculative code region (e.g. a transaction or critical section) loads are normally tracked in a read set. However, a programmer or compiler may utilize the explicit non-transactional read to load from a memory address into a destination register, while not adding the read/load to the transactional read set. Similarly, a non-transactional store is also provided. Here, a transactional store is performed and not added to a write set during speculative code execution. And the store may be immediately globally visible and/or persistent (even after an abort of the speculative code region). In other words, speculative escape operations are provided to ‘escape’ a speculative code region to perform non-transactional memory accesses without causing the speculative code region to abort or fail.
摘要翻译：这里描述了一种用于提供推测逃逸指令的装置和方法。具体地，本文描述了显式的非事务性加载操作。在推测性代码区域（例如交易或关键部分）的执行期间，通常在读取集合中跟踪负载。然而，程序员或编译器可以利用显式的非事务性读取从存储器地址加载到目标寄存器中，而不将读取/加载添加到事务读取集合。同样，也提供非事务存储。这里，在推测性代码执行期间执行事务存储并且不添加到写入集合。并且商店可能立即全局可见和/或持久（即使在推测性代码区域中止之后）。换句话说，提供推测性逃避操作以“逃逸”推测性代码区域以执行非事务性存储器访问，而不会导致推测性代码区域中止或失败。

5. 发明授权

US10114651B2 Gathering and scattering multiple data elements 有权
公开(公告)号：US10114651B2
公开(公告)日：2018-10-30
申请号：US15862407
申请日：2018-01-04
申请人： Christopher J. Hughes , Yen-Kuang (Y. K.) Chen , Mayank Bomb , Jason W. Brandt , Mark J. Buxton , Mark J. Charney , Srinivas Chennupaty , Jesus Corbal , Martin G. Dixon , Milind B. Girkar , Jonathan C. Hall , Hideki (Saito) Ido , Peter Lachner , Gilbert Neiger , Chris J. Newburn , Rajesh S. Parthasarathy , Bret L. Toll , Robert Valentine , Jeffrey G. Wiedemeier
发明人： Christopher J. Hughes , Yen-Kuang (Y. K.) Chen , Mayank Bomb , Jason W. Brandt , Mark J. Buxton , Mark J. Charney , Srinivas Chennupaty , Jesus Corbal , Martin G. Dixon , Milind B. Girkar , Jonathan C. Hall , Hideki (Saito) Ido , Peter Lachner , Gilbert Neiger , Chris J. Newburn , Rajesh S. Parthasarathy , Bret L. Toll , Robert Valentine , Jeffrey G. Wiedemeier
IPC分类号： G06F9/00 , G06F12/08 , G06F9/38 , G06F9/30
摘要： According to a first aspect, efficient data transfer operations can be achieved by: decoding by a processor device, a single instruction specifying a transfer operation for a plurality of data elements between a first storage location and a second storage location; issuing the single instruction for execution by an execution unit in the processor; detecting an occurrence of an exception during execution of the single instruction; and in response to the exception, delivering pending traps or interrupts to an exception handler prior to delivering the exception.

6. 发明申请

US20180129506A1 GATHERING AND SCATTERING MULTIPLE DATA ELEMENTS 审中-公开
公开(公告)号：US20180129506A1
公开(公告)日：2018-05-10
申请号：US15862407
申请日：2018-01-04
申请人： Christopher J. Hughes , Yen-Kuang (Y.K.) Chen , Mayank Bomb , Jason W. Brandt , Mark J. Buxton , Mark J. Charney , Srinivas Chennupaty , Jesus Corbal , Martin G. Dixon , Milind B. Girkar , Jonathan C. Hall , Hideki (Saito) Ido , Peter Lachner , Gilbert Neiger , Chris J. Newburn , Rajesh S. Parthasarathy , Bret L. Toll , Robert Valentine , Jeffrey G. Wiedemeier
发明人： Christopher J. Hughes , Yen-Kuang (Y.K.) Chen , Mayank Bomb , Jason W. Brandt , Mark J. Buxton , Mark J. Charney , Srinivas Chennupaty , Jesus Corbal , Martin G. Dixon , Milind B. Girkar , Jonathan C. Hall , Hideki (Saito) Ido , Peter Lachner , Gilbert Neiger , Chris J. Newburn , Rajesh S. Parthasarathy , Bret L. Toll , Robert Valentine , Jeffrey G. Wiedemeier
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3861 , G06F9/30036 , G06F9/30043 , G06F9/30145 , G06F9/345
摘要： According to a first aspect, efficient data transfer operations can be achieved by: decoding by a processor device, a single instruction specifying a transfer operation for a plurality of data elements between a first storage location and a second storage location; issuing the single instruction for execution by an execution unit in the processor; detecting an occurrence of an exception during execution of the single instruction; and in response to the exception, delivering pending traps or interrupts to an exception handler prior to delivering the exception.

7. 发明申请

US20110153997A1 Bit Range Isolation Instructions, Methods, and Apparatus 有权
标题翻译：位范围隔离说明，方法和设备
公开(公告)号：US20110153997A1
公开(公告)日：2011-06-23
申请号：US12645307
申请日：2009-12-22
申请人： Maxim Loktyukhin , Eric W. Mahurin , Bret L. Toll , Martin G. Dixon , Sean P. Mirkes , David L. Kreitzer , El Moustapha Ould-Ahmed-Vall , Vinodh Gopal
发明人： Maxim Loktyukhin , Eric W. Mahurin , Bret L. Toll , Martin G. Dixon , Sean P. Mirkes , David L. Kreitzer , El Moustapha Ould-Ahmed-Vall , Vinodh Gopal
IPC分类号： G06F9/305 , G06F9/30 , G06F12/02
CPC分类号： G06F9/30145 , G06F9/30018 , G06F9/30029 , G06F9/30094 , G06F9/3802
摘要： Receiving an instruction indicating a source operand and a destination operand. Storing a result in the destination operand in response to the instruction. The result operand may have: (1) first range of bits having a first end explicitly specified by the instruction in which each bit is identical in value to a bit of the source operand in a corresponding position; and (2) second range of bits that all have a same value regardless of values of bits of the source operand in corresponding positions. Execution of instruction may complete without moving the first range of the result relative to the bits of identical value in the corresponding positions of the source operand, regardless of the location of the first range of bits in the result. Execution units to execute such instructions, computer systems having processors to execute such instructions, and machine-readable medium storing such an instruction are also disclosed.
摘要翻译：接收指示源操作数和目标操作数的指令。将结果存储在目标操作数中以响应指令。结果操作数可以具有：（1）具有第一端的第一范围，其中每个位在相应位置中的每个位与源操作数的位相同的指令明确地指定; 和（2）与相应位置中的源操作数的位的值无关的所有位都具有相同值的第二范围。不管移动第一范围的结果相对于源操作数的相应位置中相同值的位，执行指令都可以完成，而不考虑结果中第一个位的位置。还公开了执行这些指令的执行单元，具有执行这种指令的处理器的计算机系统以及存储这种指令的机器可读介质。

8. 发明申请

US20110153983A1 Gathering and Scattering Multiple Data Elements 有权
标题翻译：收集和散布多个数据元素
公开(公告)号：US20110153983A1
公开(公告)日：2011-06-23
申请号：US12644440
申请日：2009-12-22
申请人： Christopher J. Hughes , Yen-Kuang (Y.K.) Chen , Mayank Bomb , Jason W. Brandt , Mark J. Buxton , Mark J. Charney , Srinivas Chennupaty , Jesus Corbal , Martin G. Dixon , Milind B. Girkar , Jonathan C. Hall , Hideki (Saito) Ido , Peter Lachner , Gilbert Neiger , Chris J. Newburn , Rajesh S. Parthasarathy , Bret L. Toll , Robert Valentine , Jeffrey G. Wiedemeier
发明人： Christopher J. Hughes , Yen-Kuang (Y.K.) Chen , Mayank Bomb , Jason W. Brandt , Mark J. Buxton , Mark J. Charney , Srinivas Chennupaty , Jesus Corbal , Martin G. Dixon , Milind B. Girkar , Jonathan C. Hall , Hideki (Saito) Ido , Peter Lachner , Gilbert Neiger , Chris J. Newburn , Rajesh S. Parthasarathy , Bret L. Toll , Robert Valentine , Jeffrey G. Wiedemeier
IPC分类号： G06F9/38 , G06F15/76 , G06F9/06 , G06F12/08
CPC分类号： G06F9/30018 , G06F9/30032 , G06F9/30036 , G06F9/30043 , G06F9/30109 , G06F9/3865
摘要： According to a first aspect, efficient data transfer operations can be achieved by: decoding by a processor device, a single instruction specifying a transfer operation for a plurality of data elements between a first storage location and a second storage location; issuing the single instruction for execution by an execution unit in the processor; detecting an occurrence of an exception during execution of the single instruction; and in response to the exception, delivering pending traps or interrupts to an exception handler prior to delivering the exception.
摘要翻译：根据第一方面，可以通过以下方式来实现有效的数据传送操作：通过处理器设备解码指定在第一存储位置和第二存储位置之间的多个数据元素的传送操作的单个指令; 发出用于由处理器中的执行单元执行的单个指令; 在单个指令的执行期间检测异常的发生; 并且响应于异常，在传递异常之前将异常陷阱或中断传递给异常处理程序。

9. 发明申请

US20140344553A1 Gathering and Scattering Multiple Data Elements 审中-公开
标题翻译：收集和散布多个数据元素
公开(公告)号：US20140344553A1
公开(公告)日：2014-11-20
申请号：US13898189
申请日：2013-05-20
申请人： Christopher J. Hughes , Yen-Kuang (Y.K.) Chen , Mayank Bomb , Jason W. Brandt , Mark J. Buxton , Mark J. Charney , Srinivas Chennupaty , Jesus Corbal , Martin G. Dixon , Milind B. Girkar , Jonathan C. Hall , Hideki (Saito) Ido , Peter Lachner , Gilbert Neiger , Chris J. Newburn , Rajesh S. Parthasarathy , Bret L. Toll , Robert Valentine , Jeffrey G. Wiedemeier
发明人： Christopher J. Hughes , Yen-Kuang (Y.K.) Chen , Mayank Bomb , Jason W. Brandt , Mark J. Buxton , Mark J. Charney , Srinivas Chennupaty , Jesus Corbal , Martin G. Dixon , Milind B. Girkar , Jonathan C. Hall , Hideki (Saito) Ido , Peter Lachner , Gilbert Neiger , Chris J. Newburn , Rajesh S. Parthasarathy , Bret L. Toll , Robert Valentine , Jeffrey G. Wiedemeier
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3861 , G06F9/30036 , G06F9/30043 , G06F9/30145 , G06F9/345
摘要： According to a first aspect, efficient data transfer operations can be achieved by: decoding by a processor device, a single instruction specifying a transfer operation for a plurality of data elements between a first storage location and a second storage location; issuing the single instruction for execution by an execution unit in the processor; detecting an occurrence of an exception during execution of the single instruction; and in response to the exception, delivering pending traps or interrupts to an exception handler prior to delivering the exception.
摘要翻译：根据第一方面，可以通过以下方式来实现有效的数据传送操作：通过处理器设备解码指定在第一存储位置和第二存储位置之间的多个数据元素的传送操作的单个指令; 发出用于由处理器中的执行单元执行的单个指令; 在单个指令的执行期间检测异常的发生; 并且响应于异常，在传递异常之前将异常陷阱或中断传递给异常处理程序。

10. 发明授权

US08549264B2 Add instructions to add three source operands 有权
标题翻译：添加指令以添加三个源操作数
公开(公告)号：US08549264B2
公开(公告)日：2013-10-01
申请号：US12645334
申请日：2009-12-22
申请人： Vinodh Gopal , James D. Guilford , Gilbert M. Wolrich , Wajdi K. Feghali , Erdinc Ozturk , Martin G. Dixon , Sean P. Mirkes , Bret L. Toll , Maxim Loktyukhin , Mark C. Davis , Alexandre J. Farcy
发明人： Vinodh Gopal , James D. Guilford , Gilbert M. Wolrich , Wajdi K. Feghali , Erdinc Ozturk , Martin G. Dixon , Sean P. Mirkes , Bret L. Toll , Maxim Loktyukhin , Mark C. Davis , Alexandre J. Farcy
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44 , G06F15/00
CPC分类号： G06F9/3001 , G06F9/30094
摘要： A method in one aspect may include receiving an add instruction. The add instruction may indicate a first source operand, a second source operand, and a third source operand. A sum of the first, second, and third source operands may be stored as a result of the add instruction. The sum may be stored partly in a destination operand indicated by the add instruction and partly a plurality of flags. Other methods are also disclosed, as are apparatus, systems, and instructions on machine-readable medium.
摘要翻译：一方面的方法可以包括接收添加指令。加法指令可以指示第一源操作数，第二源操作数和第三源操作数。作为加法指令的结果，可以存储第一，第二和第三源操作数的总和。该和可以部分地存储在由加法指令指示的目的地操作数中，部分地存储在多个标志中。还公开了其它方法，以及机器可读介质上的装置，系统和指令。

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