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1. 发明授权

US08929840B2 Local oscillator buffer and mixer having adjustable size 有权
标题翻译：具有可调大小的本地振荡器缓冲器和混频器
公开(公告)号：US08929840B2
公开(公告)日：2015-01-06
申请号：US12209164
申请日：2008-09-11
申请人： Sankaran Aniruddhan , Chiewcharn Narathong , Sriramgopal Sridhara , Ravi Sridhara , Gurkanwal Singh Sahota , Frederic Bossu , Ojas M. Choksi
发明人： Sankaran Aniruddhan , Chiewcharn Narathong , Sriramgopal Sridhara , Ravi Sridhara , Gurkanwal Singh Sahota , Frederic Bossu , Ojas M. Choksi
IPC分类号： H04B1/02 , H04B1/06 , H04B7/00 , H04B1/26 , H03D7/16 , H03D7/14 , H03G3/30
CPC分类号： H03D7/166 , H03D7/1441 , H03D7/1483 , H03D7/165 , H03D2200/0025 , H03G3/3052
摘要： Selectable sizes for a local oscillator (LO) buffer and mixer are disclosed. In an exemplary embodiment, LO buffer and/or mixer size may be increased when a receiver or transmitter operates in a high gain mode, while LO buffer and/or mixer size may be decreased when the receiver or transmitter operates in a low gain mode. In an exemplary embodiment, LO buffer and mixer sizes are increased and decreased in lock step. Circuit topologies and control schemes for specific exemplary embodiments of LO buffers and mixers having adjustable size are disclosed.
摘要翻译：公开了本地振荡器（LO）缓冲器和混频器的可选尺寸。在示例性实施例中，当接收机或发射机以高增益模式工作时，可以增加LO缓冲器和/或混频器大小，而当接收机或发射机以低增益模式工作时，LO缓冲器和/或混频器大小可能会减小。在示例性实施例中，锁定步骤中LO缓冲器和混合器尺寸增加和减小。公开了具有可调节尺寸的LO缓冲器和混合器的具体示例性实施例的电路拓扑和控制方案。

2. 发明申请

US20090075620A1 LOCAL OSCILLATOR BUFFER AND MIXER HAVING ADJUSTABLE SIZE 有权
标题翻译：本地振荡器缓冲器和具有可调整尺寸的混频器
公开(公告)号：US20090075620A1
公开(公告)日：2009-03-19
申请号：US12209164
申请日：2008-09-11
申请人： Sankaran Aniruddhan , Chiewcharn Narathong , Sriramgopal Sridhara , Ravi Sridhara , Gurkanwal Singh Sahota , Frederic Bossu , Ojas M. Choksi
发明人： Sankaran Aniruddhan , Chiewcharn Narathong , Sriramgopal Sridhara , Ravi Sridhara , Gurkanwal Singh Sahota , Frederic Bossu , Ojas M. Choksi
IPC分类号： H04B1/26
CPC分类号： H03D7/166 , H03D7/1441 , H03D7/1483 , H03D7/165 , H03D2200/0025 , H03G3/3052
摘要： Selectable sizes for a local oscillator (LO) buffer and mixer are disclosed. In an exemplary embodiment, LO buffer and/or mixer size may be increased when a receiver or transmitter operates in a high gain mode, while LO buffer and/or mixer size may be decreased when the receiver or transmitter operates in a low gain mode. In an exemplary embodiment, LO buffer and mixer sizes are increased and decreased in lock step. Circuit topologies and control schemes for specific exemplary embodiments of LO buffers and mixers having adjustable size are disclosed.
摘要翻译：公开了本地振荡器（LO）缓冲器和混频器的可选尺寸。在示例性实施例中，当接收机或发射机以高增益模式工作时，可以增加LO缓冲器和/或混频器大小，而当接收机或发射机以低增益模式工作时，LO缓冲器和/或混频器大小可能会减小。在示例性实施例中，锁定步骤中LO缓冲器和混合器尺寸增加和减小。公开了具有可调节尺寸的LO缓冲器和混合器的具体示例性实施例的电路拓扑和控制方案。

3. 发明申请

US20090111414A1 LOCAL OSCILLATOR BUFFER AND MIXER HAVING ADJUSTABLE SIZE 有权
标题翻译：本地振荡器缓冲器和具有可调整尺寸的混频器
公开(公告)号：US20090111414A1
公开(公告)日：2009-04-30
申请号：US11955201
申请日：2007-12-12
申请人： Gurkanwal Singh Sahota , Frederic Bossu , Ojas M. Choksi
发明人： Gurkanwal Singh Sahota , Frederic Bossu , Ojas M. Choksi
IPC分类号： H04B1/16
CPC分类号： H03D7/1441 , H03D7/165 , H03D7/166 , H03D2200/0084 , H03D2200/009
摘要： Selectable sizes for a local oscillator (LO) buffer and mixer are disclosed. In an embodiment, LO buffer and/or mixer size may be increased when a receiver operates in a high gain mode, while LO buffer and/or mixer size may be decreased when the receiver operates in a low gain mode. In an embodiment, LO buffer and mixer sizes are increased and decreased in lock step. Circuit topologies and control schemes for specific embodiments of LO buffers and mixers having adjustable size are disclosed.
摘要翻译：公开了本地振荡器（LO）缓冲器和混频器的可选尺寸。在一个实施例中，当接收机以高增益模式工作时，可以增加LO缓冲器和/或混频器的大小，而当接收器以低增益模式工作时，可以减小LO缓冲器和/或混频器的大小。在一个实施例中，LO缓冲器和混合器尺寸在锁定步骤中增加和减小。公开了具有可调节尺寸的LO缓冲器和混合器的具体实施例的电路拓扑和控制方案。

4. 发明授权

US08019310B2 Local oscillator buffer and mixer having adjustable size 有权
标题翻译：具有可调大小的本地振荡器缓冲器和混频器
公开(公告)号：US08019310B2
公开(公告)日：2011-09-13
申请号：US11955201
申请日：2007-12-12
申请人： Gurkanwal Singh Sahota , Frederic Bossu , Ojas M. Choksi
发明人： Gurkanwal Singh Sahota , Frederic Bossu , Ojas M. Choksi
IPC分类号： H04B1/26 , H04B7/00 , H04B15/00
CPC分类号： H03D7/1441 , H03D7/165 , H03D7/166 , H03D2200/0084 , H03D2200/009
摘要： Selectable sizes for a local oscillator (LO) buffer and mixer are disclosed. In an embodiment, LO buffer and/or mixer size may be increased when a receiver operates in a high gain mode, while LO buffer and/or mixer size may be decreased when the receiver operates in a low gain mode. In an embodiment, LO buffer and mixer sizes are increased and decreased in lock step. Circuit topologies and control schemes for specific embodiments of LO buffers and mixers having adjustable size are disclosed.
摘要翻译：公开了本地振荡器（LO）缓冲器和混频器的可选尺寸。在一个实施例中，当接收机以高增益模式工作时，可以增加LO缓冲器和/或混频器的大小，而当接收器以低增益模式工作时，可以减小LO缓冲器和/或混频器的大小。在一个实施例中，LO缓冲器和混合器尺寸在锁定步骤中增加和减小。公开了具有可调节尺寸的LO缓冲器和混合器的具体实施例的电路拓扑和控制方案。

5. 发明授权

US08615205B2 I-Q mismatch calibration and method 失效
标题翻译： I-Q不匹配校准和方法
公开(公告)号：US08615205B2
公开(公告)日：2013-12-24
申请号：US12259178
申请日：2008-10-27
申请人： Ojas M. Choksi , Frederic Bossu
发明人： Ojas M. Choksi , Frederic Bossu
IPC分类号： H03C1/62
CPC分类号： H04L5/1461 , H03D3/009 , H03M1/1019 , H03M1/66 , H04L27/0014 , H04L2027/0016 , H04L2027/0018 , H04L2027/0024
摘要： Techniques are provided for reducing mismatch between the in-phase (I) and quadrature (Q) channels of a communications transmitter or receiver. In an exemplary embodiment, separate voltages are applied to bias the gates or bulks of the transistors in a mixer of the I channel versus a mixer of the Q channel. In another exemplary embodiment, separate voltages are applied to bias the common-mode reference voltage of a transimpedance amplifier associated with each channel. Techniques are further provided for deriving bias voltages to minimize a measured residual sideband in a received or transmitted signal, or to optimize other parameters of the received or transmitted signal. Techniques for generating separate bias voltages using a bidirectional and unidirectional current digital-to-analog converter (DAC) are also disclosed.
摘要翻译：提供了用于减少通信发射机或接收机的同相（I）和正交（Q）信道之间的失配的技术。在示例性实施例中，施加单独的电压以在I通道的混频器中与Q通道的混频器偏置晶体管的栅极或体积。在另一个示例性实施例中，施加单独的电压以偏置与每个通道相关联的跨阻抗放大器的共模参考电压。还提供了用于导出偏置电压以最小化接收或发射信号中测量的残留边带或者优化接收或发射信号的其它参数的技术。还公开了使用双向和单向电流数模转换器（DAC）产生单独偏置电压的技术。

6. 发明申请

US20090154595A1 I-Q MISMATCH CALIBRATION AND METHOD 失效
标题翻译： I-Q MISMATCH校准和方法
公开(公告)号：US20090154595A1
公开(公告)日：2009-06-18
申请号：US12259178
申请日：2008-10-27
申请人： Ojas M. Choksi , Frederic Bossu
发明人： Ojas M. Choksi , Frederic Bossu
IPC分类号： H04L27/00
CPC分类号： H04L5/1461 , H03D3/009 , H03M1/1019 , H03M1/66 , H04L27/0014 , H04L2027/0016 , H04L2027/0018 , H04L2027/0024
摘要： Techniques are provided for reducing mismatch between the in-phase (I) and quadrature (Q) channels of a communications transmitter or receiver. In an exemplary embodiment, separate voltages are applied to bias the gates or bulks of the transistors in a mixer of the I channel versus a mixer of the Q channel. In another exemplary embodiment, separate voltages are applied to bias the common-mode reference voltage of a transimpedance amplifier associated with each channel. Techniques are further provided for deriving bias voltages to minimize a measured residual sideband in a received or transmitted signal, or to optimize other parameters of the received or transmitted signal. Techniques for generating separate bias voltages using a bidirectional and unidirectional current digital-to-analog converter (DAC) are also disclosed.
摘要翻译：提供了用于减少通信发射机或接收机的同相（I）和正交（Q）信道之间的失配的技术。在示例性实施例中，施加单独的电压以在I通道的混频器中与Q通道的混频器偏置晶体管的栅极或体积。在另一个示例性实施例中，施加单独的电压以偏置与每个通道相关联的跨阻抗放大器的共模参考电压。还提供了用于导出偏置电压以最小化接收或发射信号中测量的残留边带或者优化接收或发射信号的其它参数的技术。还公开了使用双向和单向电流数模转换器（DAC）产生单独偏置电压的技术。

7. 发明授权

US08432211B2 Mixer-transconductance interface 有权
标题翻译：混频器 - 跨导接口
公开(公告)号：US08432211B2
公开(公告)日：2013-04-30
申请号：US12763458
申请日：2010-04-20
申请人： Ojas M. Choksi , Mahim Ranjan
发明人： Ojas M. Choksi , Mahim Ranjan
IPC分类号： G06G7/12
CPC分类号： H03D7/165
摘要： Techniques for providing an efficient interface between a mixer block and a transconductance (Gm) block. In an exemplary embodiment, the output currents of at least two unit cells of the transconductance block are conductively coupled together, and coupled to the mixer block using a single conductive path. For a differential signal, the conductive path may include two conductive leads. Within the mixer block, the single conductive path may be fanned out to at least two unit cells of the mixer block. At least one Gm unit cell may be selectively enabled or disabled to control the gain setting of the mixer-transconductance block. The techniques may further be applied to transceiver architectures supporting in-phase and quadrature mixing, as well as multi-mode and/or multi-band operation.
摘要翻译：在混合器块和跨导（Gm）块之间提供有效接口的技术。在示例性实施例中，跨导块的至少两个单位单元的输出电流被导电耦合在一起，并且使用单个导电路径耦合到混频器块。对于差分信号，导电路径可以包括两个导电引线。在混合器块内，单个导电路径可以扇形到混合器块的至少两个单元电池。可以选择性地使能或禁用至少一个Gm单位单元来控制混频器 - 跨导块的增益设置。这些技术可以进一步应用于支持同相和正交混合以及多模式和/或多频带操作的收发器架构。

8. 发明申请

US20110001539A1 MIXER-TRANSCONDUCTANCE INTERFACE 有权
标题翻译：混合器 - 交叉接口
公开(公告)号：US20110001539A1
公开(公告)日：2011-01-06
申请号：US12763458
申请日：2010-04-20
申请人： Ojas M. Choksi , Mahim Ranjan
发明人： Ojas M. Choksi , Mahim Ranjan
IPC分类号： G06G7/12
CPC分类号： H03D7/165
摘要： Techniques for providing an efficient interface between a mixer block and a transconductance (Gm) block. In an exemplary embodiment, the output currents of at least two unit cells of the transconductance block are conductively coupled together, and coupled to the mixer block using a single conductive path. For a differential signal, the conductive path may include two conductive leads. Within the mixer block, the single conductive path may be fanned out to at least two unit cells of the mixer block. At least one Gm unit cell may be selectively enabled or disabled to control the gain setting of the mixer-transconductance block. The techniques may further be applied to transceiver architectures supporting in-phase and quadrature mixing, as well as multi-mode and/or multi-band operation.
摘要翻译：在混合器块和跨导（Gm）块之间提供有效接口的技术。在示例性实施例中，跨导块的至少两个单位单元的输出电流被导电耦合在一起，并且使用单个导电路径耦合到混频器块。对于差分信号，导电路径可以包括两个导电引线。在混合器块内，单个导电路径可以扇形到混合器块的至少两个单元电池。可以选择性地使能或禁用至少一个Gm单位单元来控制混频器 - 跨导块的增益设置。这些技术可以进一步应用于支持同相和正交混合以及多模式和/或多频带操作的收发器架构。

9. 发明授权

US08975966B2 Shared bypass capacitor matching network 有权
标题翻译：共享旁路电容匹配网络
公开(公告)号：US08975966B2
公开(公告)日：2015-03-10
申请号：US13413897
申请日：2012-03-07
申请人： Prasad Srinivasa Siva Gudem , Ojas M. Choksi
发明人： Prasad Srinivasa Siva Gudem , Ojas M. Choksi
IPC分类号： H03F3/191
CPC分类号： H04B1/18
摘要： A receiver is described. The receiver includes a first amplifier on an integrated circuit. The receiver also includes a second amplifier on the integrated circuit. The receiver further includes a first inductor coupled to the first amplifier. The receiver also includes a second inductor coupled to the second amplifier. The receiver further includes a first capacitor coupled to the first inductor, the second inductor, and to ground. The first capacitor is shared between a first matching network for the first amplifier and a second matching network for the second amplifier.
摘要翻译：描述接收机。接收机包括集成电路上的第一放大器。接收器还包括集成电路上的第二放大器。接收器还包括耦合到第一放大器的第一电感器。接收器还包括耦合到第二放大器的第二电感器。接收器还包括耦合到第一电感器，第二电感器和接地的第一电容器。第一电容器在用于第一放大器的第一匹配网络和用于第二放大器的第二匹配网络之间共享。

10. 发明申请

US20100321137A1 PROGRAMMABLE VARACTOR AND METHODS OF OPERATION THEREOF 有权
标题翻译：可编程变量及其操作方法
公开(公告)号：US20100321137A1
公开(公告)日：2010-12-23
申请号：US12821071
申请日：2010-06-22
申请人： Rajagopalan Rangarajan , Ojas M. Choksi
发明人： Rajagopalan Rangarajan , Ojas M. Choksi
IPC分类号： H03H5/12
CPC分类号： H03J3/18 , H03H5/12 , H03J2200/36
摘要： Exemplary embodiments are directed to a programmable varactor device. A varactor device may include an input device configured to receive a tuning voltage and generate a bias voltage at least partially dependent on the tuning voltage. The varactor device may also include a varactor pair coupled to the input device and having a first variable capacitor and a second variable capacitor, wherein each of the first variable capacitor and a second variable capacitor are configured for operable coupling to each of the bias voltage and the tuning voltage.
摘要翻译：示例性实施例涉及可编程变容二极管装置。变容二极管器件可以包括被配置为接收调谐电压并且至少部分地依赖于调谐电压产生偏置电压的输入器件。可变电抗器装置还可以包括耦合到输入装置并具有第一可变电容器和第二可变电容器的变容二极管对，其中第一可变电容器和第二可变电容器中的每一个被配置为可操作地耦合到每个偏置电压和调谐电压。

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