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1. 发明授权

US08929840B2 Local oscillator buffer and mixer having adjustable size 有权
标题翻译：具有可调大小的本地振荡器缓冲器和混频器
公开(公告)号：US08929840B2
公开(公告)日：2015-01-06
申请号：US12209164
申请日：2008-09-11
申请人： Sankaran Aniruddhan , Chiewcharn Narathong , Sriramgopal Sridhara , Ravi Sridhara , Gurkanwal Singh Sahota , Frederic Bossu , Ojas M. Choksi
发明人： Sankaran Aniruddhan , Chiewcharn Narathong , Sriramgopal Sridhara , Ravi Sridhara , Gurkanwal Singh Sahota , Frederic Bossu , Ojas M. Choksi
IPC分类号： H04B1/02 , H04B1/06 , H04B7/00 , H04B1/26 , H03D7/16 , H03D7/14 , H03G3/30
CPC分类号： H03D7/166 , H03D7/1441 , H03D7/1483 , H03D7/165 , H03D2200/0025 , H03G3/3052
摘要： Selectable sizes for a local oscillator (LO) buffer and mixer are disclosed. In an exemplary embodiment, LO buffer and/or mixer size may be increased when a receiver or transmitter operates in a high gain mode, while LO buffer and/or mixer size may be decreased when the receiver or transmitter operates in a low gain mode. In an exemplary embodiment, LO buffer and mixer sizes are increased and decreased in lock step. Circuit topologies and control schemes for specific exemplary embodiments of LO buffers and mixers having adjustable size are disclosed.
摘要翻译：公开了本地振荡器（LO）缓冲器和混频器的可选尺寸。在示例性实施例中，当接收机或发射机以高增益模式工作时，可以增加LO缓冲器和/或混频器大小，而当接收机或发射机以低增益模式工作时，LO缓冲器和/或混频器大小可能会减小。在示例性实施例中，锁定步骤中LO缓冲器和混合器尺寸增加和减小。公开了具有可调节尺寸的LO缓冲器和混合器的具体示例性实施例的电路拓扑和控制方案。

2. 发明申请

US20090075620A1 LOCAL OSCILLATOR BUFFER AND MIXER HAVING ADJUSTABLE SIZE 有权
标题翻译：本地振荡器缓冲器和具有可调整尺寸的混频器
公开(公告)号：US20090075620A1
公开(公告)日：2009-03-19
申请号：US12209164
申请日：2008-09-11
申请人： Sankaran Aniruddhan , Chiewcharn Narathong , Sriramgopal Sridhara , Ravi Sridhara , Gurkanwal Singh Sahota , Frederic Bossu , Ojas M. Choksi
发明人： Sankaran Aniruddhan , Chiewcharn Narathong , Sriramgopal Sridhara , Ravi Sridhara , Gurkanwal Singh Sahota , Frederic Bossu , Ojas M. Choksi
IPC分类号： H04B1/26
CPC分类号： H03D7/166 , H03D7/1441 , H03D7/1483 , H03D7/165 , H03D2200/0025 , H03G3/3052
摘要： Selectable sizes for a local oscillator (LO) buffer and mixer are disclosed. In an exemplary embodiment, LO buffer and/or mixer size may be increased when a receiver or transmitter operates in a high gain mode, while LO buffer and/or mixer size may be decreased when the receiver or transmitter operates in a low gain mode. In an exemplary embodiment, LO buffer and mixer sizes are increased and decreased in lock step. Circuit topologies and control schemes for specific exemplary embodiments of LO buffers and mixers having adjustable size are disclosed.
摘要翻译：公开了本地振荡器（LO）缓冲器和混频器的可选尺寸。在示例性实施例中，当接收机或发射机以高增益模式工作时，可以增加LO缓冲器和/或混频器大小，而当接收机或发射机以低增益模式工作时，LO缓冲器和/或混频器大小可能会减小。在示例性实施例中，锁定步骤中LO缓冲器和混合器尺寸增加和减小。公开了具有可调节尺寸的LO缓冲器和混合器的具体示例性实施例的电路拓扑和控制方案。

3. 发明授权

US07965111B2 Method and apparatus for divider unit synchronization 有权
标题翻译：分频器单元同步的方法和装置
公开(公告)号：US07965111B2
公开(公告)日：2011-06-21
申请号：US12111561
申请日：2008-04-29
申请人： Bo Sun , Sankaran Aniruddhan , Sriramgopal Sridhara
发明人： Bo Sun , Sankaran Aniruddhan , Sriramgopal Sridhara
IPC分类号： H03L7/00
CPC分类号： G06F1/12 , G06F1/3203 , G06F1/3287 , Y02D10/171
摘要： A method an apparatus for synchronizing phases of one or more divider units comprise powering on a master divider unit to provide a reference signal. A phase of a slave divider unit is synchronized to the reference signal from the master divider unit by providing a power on pulse at the slave divider unit, synchronizing the phase of the slave divider unit to the reference signal using a digitally controlled oscillator, and powering on the slave divider unit after a first predetermined delay period following a rising edge of the power on pulse. By synchronizing a slave divider unit to the reference signal from the master divider unit, any number of slave divider units may be powered on and in-phase with each other.
摘要翻译：一种用于同步一个或多个除法器单元的相位的装置的方法包括在主分频器单元上供电以提供参考信号。从分频器单元的相位通过在从分频器单元处提供通电脉冲而与来自主分频器单元的参考信号同步，使用数字控制的振荡器将从分频器单元的相位与参考信号同步，在通电脉冲的上升沿之后的第一预定延迟时段之后的从分频器单元上。通过将从属分频器单元与来自主分频器单元的参考信号同步，任何数量的从分频器单元可以通电并且彼此同相。

4. 发明申请

US20090267657A1 METHOD AND APPARATUS FOR DIVIDER UNIT SYNCHRONIZATION 有权
标题翻译：用于分流器单元同步的方法和装置
公开(公告)号：US20090267657A1
公开(公告)日：2009-10-29
申请号：US12111561
申请日：2008-04-29
申请人： Bo Sun , Sankaran Aniruddhan , Sriramgopal Sridhara
发明人： Bo Sun , Sankaran Aniruddhan , Sriramgopal Sridhara
IPC分类号： H03L7/00
CPC分类号： G06F1/12 , G06F1/3203 , G06F1/3287 , Y02D10/171
摘要： A method an apparatus for synchronizing phases of one or more divider units comprise powering on a master divider unit to provide a reference signal. A phase of a slave divider unit is synchronized to the reference signal from the master divider unit by providing a power on pulse at the slave divider unit, synchronizing the phase of the slave divider unit to the reference signal using a digitally controlled oscillator, and powering on the slave divider unit after a first predetermined delay period following a rising edge of the power on pulse. By synchronizing a slave divider unit to the reference signal from the master divider unit, any number of slave divider units may be powered on and in-phase with each other.
摘要翻译：一种用于同步一个或多个除法器单元的相位的装置的方法包括在主分频器单元上供电以提供参考信号。从分频器单元的相位通过在从分频器单元处提供通电脉冲而与来自主分频器单元的参考信号同步，使用数字控制的振荡器将从分频器单元的相位与参考信号同步，在通电脉冲的上升沿之后的第一预定延迟时段之后的从分频器单元上。通过将从属分频器单元与来自主分频器单元的参考信号同步，任何数量的从分频器单元可以通电并且彼此同相。

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