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1. 发明授权

US08929840B2 Local oscillator buffer and mixer having adjustable size 有权
标题翻译：具有可调大小的本地振荡器缓冲器和混频器
公开(公告)号：US08929840B2
公开(公告)日：2015-01-06
申请号：US12209164
申请日：2008-09-11
申请人： Sankaran Aniruddhan , Chiewcharn Narathong , Sriramgopal Sridhara , Ravi Sridhara , Gurkanwal Singh Sahota , Frederic Bossu , Ojas M. Choksi
发明人： Sankaran Aniruddhan , Chiewcharn Narathong , Sriramgopal Sridhara , Ravi Sridhara , Gurkanwal Singh Sahota , Frederic Bossu , Ojas M. Choksi
IPC分类号： H04B1/02 , H04B1/06 , H04B7/00 , H04B1/26 , H03D7/16 , H03D7/14 , H03G3/30
CPC分类号： H03D7/166 , H03D7/1441 , H03D7/1483 , H03D7/165 , H03D2200/0025 , H03G3/3052
摘要： Selectable sizes for a local oscillator (LO) buffer and mixer are disclosed. In an exemplary embodiment, LO buffer and/or mixer size may be increased when a receiver or transmitter operates in a high gain mode, while LO buffer and/or mixer size may be decreased when the receiver or transmitter operates in a low gain mode. In an exemplary embodiment, LO buffer and mixer sizes are increased and decreased in lock step. Circuit topologies and control schemes for specific exemplary embodiments of LO buffers and mixers having adjustable size are disclosed.
摘要翻译：公开了本地振荡器（LO）缓冲器和混频器的可选尺寸。在示例性实施例中，当接收机或发射机以高增益模式工作时，可以增加LO缓冲器和/或混频器大小，而当接收机或发射机以低增益模式工作时，LO缓冲器和/或混频器大小可能会减小。在示例性实施例中，锁定步骤中LO缓冲器和混合器尺寸增加和减小。公开了具有可调节尺寸的LO缓冲器和混合器的具体示例性实施例的电路拓扑和控制方案。

2. 发明申请

US20090075620A1 LOCAL OSCILLATOR BUFFER AND MIXER HAVING ADJUSTABLE SIZE 有权
标题翻译：本地振荡器缓冲器和具有可调整尺寸的混频器
公开(公告)号：US20090075620A1
公开(公告)日：2009-03-19
申请号：US12209164
申请日：2008-09-11
申请人： Sankaran Aniruddhan , Chiewcharn Narathong , Sriramgopal Sridhara , Ravi Sridhara , Gurkanwal Singh Sahota , Frederic Bossu , Ojas M. Choksi
发明人： Sankaran Aniruddhan , Chiewcharn Narathong , Sriramgopal Sridhara , Ravi Sridhara , Gurkanwal Singh Sahota , Frederic Bossu , Ojas M. Choksi
IPC分类号： H04B1/26
CPC分类号： H03D7/166 , H03D7/1441 , H03D7/1483 , H03D7/165 , H03D2200/0025 , H03G3/3052
摘要： Selectable sizes for a local oscillator (LO) buffer and mixer are disclosed. In an exemplary embodiment, LO buffer and/or mixer size may be increased when a receiver or transmitter operates in a high gain mode, while LO buffer and/or mixer size may be decreased when the receiver or transmitter operates in a low gain mode. In an exemplary embodiment, LO buffer and mixer sizes are increased and decreased in lock step. Circuit topologies and control schemes for specific exemplary embodiments of LO buffers and mixers having adjustable size are disclosed.
摘要翻译：公开了本地振荡器（LO）缓冲器和混频器的可选尺寸。在示例性实施例中，当接收机或发射机以高增益模式工作时，可以增加LO缓冲器和/或混频器大小，而当接收机或发射机以低增益模式工作时，LO缓冲器和/或混频器大小可能会减小。在示例性实施例中，锁定步骤中LO缓冲器和混合器尺寸增加和减小。公开了具有可调节尺寸的LO缓冲器和混合器的具体示例性实施例的电路拓扑和控制方案。

3. 发明授权

US08599938B2 Linear and polar dual mode transmitter circuit 有权
标题翻译：线性和极性双模发射电路
公开(公告)号：US08599938B2
公开(公告)日：2013-12-03
申请号：US12277913
申请日：2008-11-25
申请人： Sankaran Aniruddhan , Chiewcharn Narathong , Ravi Sridhara , Babak Nejati
发明人： Sankaran Aniruddhan , Chiewcharn Narathong , Ravi Sridhara , Babak Nejati
IPC分类号： H04L27/00
CPC分类号： H03C5/00 , H03C3/40 , H03D7/1441 , H03D7/1458 , H03D7/1483 , H03D7/1491 , H03D7/165 , H03D7/166 , H03D2200/0023 , H03D2200/0084 , H03G3/3042 , H04L27/34 , H04L27/36 , H04L27/361 , H04L27/362 , H04L27/38 , H04L27/389
摘要： Method and apparatus for configuring a transmitter circuit to support linear or polar mode. In the linear mode, a baseband signal is specified by adjusting the amplitudes of in-phase (I) and quadrature (Q) signals, while in the polar mode, the information signal is specified by adjusting the phase of a local oscillator (LO) signal and the amplitude of either an I or a Q signal. In an exemplary embodiment, two mixers are provided for both linear and polar mode, with a set of switches selecting the appropriate input signals provided to one of the mixers based on whether the device is operating in linear or polar mode. In an exemplary embodiment, each mixer may be implemented using a scalable architecture that efficiently adjusts mixer size based on required transmit power.
摘要翻译：用于配置发射机电路以支持线性或极坐标模式的方法和装置。在线性模式中，通过调整同相（I）和正交（Q）信号的幅度来指定基带信号，而在极坐标模式中，通过调整本地振荡器（LO）的相位来指定信息信号，信号和I或Q信号的振幅。在示例性实施例中，为线性模式和极坐标模式提供两个混合器，一组开关基于装置是以线性模式还是极坐标模式选择提供给混合器之一的适当输入信号。在示例性实施例中，可以使用可升级架构来实现每个混合器，该架构可以基于所需的发射功率有效地调整混频器的大小。

4. 发明申请

US20090190692A1 LINEAR AND POLAR DUAL MODE TRANSMITTER CIRCUIT 有权
标题翻译：线性和极性双模发射机电路
公开(公告)号：US20090190692A1
公开(公告)日：2009-07-30
申请号：US12277913
申请日：2008-11-25
申请人： Sankaran Aniruddhan , Chiewcharn Narathong , Ravi Sridhara , Babak Nejati
发明人： Sankaran Aniruddhan , Chiewcharn Narathong , Ravi Sridhara , Babak Nejati
IPC分类号： H04B1/04 , H04L27/00
CPC分类号： H03C5/00 , H03C3/40 , H03D7/1441 , H03D7/1458 , H03D7/1483 , H03D7/1491 , H03D7/165 , H03D7/166 , H03D2200/0023 , H03D2200/0084 , H03G3/3042 , H04L27/34 , H04L27/36 , H04L27/361 , H04L27/362 , H04L27/38 , H04L27/389
摘要： Method and apparatus for configuring a transmitter circuit to support linear or polar mode. In the linear mode, a baseband signal is specified by adjusting the amplitudes of in-phase (I) and quadrature (Q) signals, while in the polar mode, the information signal is specified by adjusting the phase of a local oscillator (LO) signal and the amplitude of either an I or a Q signal. In an exemplary embodiment, two mixers are provided for both linear and polar mode, with a set of switches selecting the appropriate input signals provided to one of the mixers based on whether the device is operating in linear or polar mode. In an exemplary embodiment, each mixer may be implemented using a scalable architecture that efficiently adjusts mixer size based on required transmit power.
摘要翻译：用于配置发射机电路以支持线性或极坐标模式的方法和装置。在线性模式中，通过调整同相（I）和正交（Q）信号的幅度来指定基带信号，而在极坐标模式中，通过调整本地振荡器（LO）的相位来指定信息信号，信号和I或Q信号的振幅。在示例性实施例中，为线性模式和极坐标模式提供两个混合器，一组开关基于装置是以线性模式还是极坐标模式选择提供给混合器之一的适当输入信号。在示例性实施例中，可以使用可升级架构来实现每个混合器，该架构可以基于所需的发射功率有效地调整混频器的大小。

5. 发明申请

US20090075689A1 MIXER WITH HIGH OUTPUT POWER ACCURACY AND LOW LOCAL OSCILLATOR LEAKAGE 有权
标题翻译：混合器具有高输出功率精度和低的局部振荡器泄漏
公开(公告)号：US20090075689A1
公开(公告)日：2009-03-19
申请号：US11855997
申请日：2007-09-14
申请人： Sankaran Aniruddhan , Bo Sun , Arun Jayaraman , Gurkanwal Singh Sahota
发明人： Sankaran Aniruddhan , Bo Sun , Arun Jayaraman , Gurkanwal Singh Sahota
IPC分类号： H04B1/04 , H03B21/02 , H04M1/00
CPC分类号： H03D7/165 , H04B1/0483 , H04B2001/0416 , H04B2001/0491
摘要： A circuit receives a first signal (for example, a baseband signal) and mixes it with a local oscillator (LO) signal, and outputs a second signal (for example, an RFOUT signal). The circuit includes multiple identical Mixer and Frequency Divider Pair (MFDP) circuits. Each MFDP can be enabled separately. Each MFDP includes a mixer and a frequency divider that provides the mixer with a local version of the LO signal. The MFDP outputs are coupled together so that the output power of the second signal (RFOUT) is the combined output powers of the various MFDPs. By controlling the number of enabled MFDPs, the output power of the second signal is controlled. Because the MFDPs all have identical layouts, accuracy of output power step size is improved. Because LO signal power within the circuit automatically changes in proportion to the number of enabled MFDPs, local oscillator leakage problems are avoided.
摘要翻译：电路接收第一信号（例如，基带信号）并将其与本地振荡器（LO）信号混合，并输出第二信号（例如，RFOUT信号）。该电路包括多个相同的混频器和分频器对（MFDP）电路。每个MFDP可以单独启用。每个MFDP包括混频器和分频器，为混频器提供本地版本的LO信号。 MFDP输出耦合在一起，使得第二信号（RFOUT）的输出功率是各种MFDP的组合输出功率。通过控制使能的MFDP的数量，控制第二信号的输出功率。由于MFDP都具有相同的布局，因此输出功率步长的精度提高。由于电路内的LO信号功率与启用MFDP的数量成比例地自动变化，因此避免了本地振荡器泄漏问题。

6. 发明授权

US07941115B2 Mixer with high output power accuracy and low local oscillator leakage 有权
标题翻译：混频器具有高输出功率精度和低本地振荡器泄漏
公开(公告)号：US07941115B2
公开(公告)日：2011-05-10
申请号：US11855997
申请日：2007-09-14
申请人： Sankaran Aniruddhan , Bo Sun , Arun Jayaraman , Gurkanwal Singh Sahota
发明人： Sankaran Aniruddhan , Bo Sun , Arun Jayaraman , Gurkanwal Singh Sahota
IPC分类号： H04B7/00
CPC分类号： H03D7/165 , H04B1/0483 , H04B2001/0416 , H04B2001/0491
摘要： A circuit receives a first signal (for example, a baseband signal) and mixes it with a local oscillator (LO) signal, and outputs a second signal (for example, an RFOUT signal). The circuit includes multiple identical Mixer and Frequency Divider Pair (MFDP) circuits. Each MFDP can be enabled separately. Each MFDP includes a mixer and a frequency divider that provides the mixer with a local version of the LO signal. The MFDP outputs are coupled together so that the output power of the second signal (RFOUT) is the combined output powers of the various MFDPs. By controlling the number of enabled MFDPs, the output power of the second signal is controlled. Because the MFDPs all have identical layouts, accuracy of output power step size is improved. Because LO signal power within the circuit automatically changes in proportion to the number of enabled MFDPs, local oscillator leakage problems are avoided.
摘要翻译：电路接收第一信号（例如，基带信号）并将其与本地振荡器（LO）信号混合，并输出第二信号（例如，RFOUT信号）。该电路包括多个相同的混频器和分频器对（MFDP）电路。每个MFDP可以单独启用。每个MFDP包括混频器和分频器，为混频器提供本地版本的LO信号。 MFDP输出耦合在一起，使得第二信号（RFOUT）的输出功率是各种MFDP的组合输出功率。通过控制使能的MFDP的数量，控制第二信号的输出功率。由于MFDP都具有相同的布局，因此输出功率步长的精度提高。由于电路内的LO信号功率与启用MFDP的数量成比例地自动变化，因此避免了本地振荡器泄漏问题。

7. 发明授权

US07965111B2 Method and apparatus for divider unit synchronization 有权
标题翻译：分频器单元同步的方法和装置
公开(公告)号：US07965111B2
公开(公告)日：2011-06-21
申请号：US12111561
申请日：2008-04-29
申请人： Bo Sun , Sankaran Aniruddhan , Sriramgopal Sridhara
发明人： Bo Sun , Sankaran Aniruddhan , Sriramgopal Sridhara
IPC分类号： H03L7/00
CPC分类号： G06F1/12 , G06F1/3203 , G06F1/3287 , Y02D10/171
摘要： A method an apparatus for synchronizing phases of one or more divider units comprise powering on a master divider unit to provide a reference signal. A phase of a slave divider unit is synchronized to the reference signal from the master divider unit by providing a power on pulse at the slave divider unit, synchronizing the phase of the slave divider unit to the reference signal using a digitally controlled oscillator, and powering on the slave divider unit after a first predetermined delay period following a rising edge of the power on pulse. By synchronizing a slave divider unit to the reference signal from the master divider unit, any number of slave divider units may be powered on and in-phase with each other.
摘要翻译：一种用于同步一个或多个除法器单元的相位的装置的方法包括在主分频器单元上供电以提供参考信号。从分频器单元的相位通过在从分频器单元处提供通电脉冲而与来自主分频器单元的参考信号同步，使用数字控制的振荡器将从分频器单元的相位与参考信号同步，在通电脉冲的上升沿之后的第一预定延迟时段之后的从分频器单元上。通过将从属分频器单元与来自主分频器单元的参考信号同步，任何数量的从分频器单元可以通电并且彼此同相。

8. 发明申请

US20090315621A1 AMPLIFIER WITH GAIN EXPANSION STAGE 有权
标题翻译：具增益放大器的放大器
公开(公告)号：US20090315621A1
公开(公告)日：2009-12-24
申请号：US12143669
申请日：2008-06-20
申请人： Chiewcharn Narathong , Sankaran Aniruddhan , Wenjun Su
发明人： Chiewcharn Narathong , Sankaran Aniruddhan , Wenjun Su
IPC分类号： H03F1/14 , H03F3/68
CPC分类号： H03F1/3276 , H03F1/301 , H03F1/308 , H03F1/3241 , H03F3/245 , H03F3/3022 , H03F2200/336 , H03F2200/451 , H03F2200/453 , H03F2203/30099 , H03F2203/30132 , H03F2203/7231
摘要： Techniques are disclosed for extending an amplifier's linear operating range by concatenating an amplifier exhibiting gain compression with a gain expansion stage. In an exemplary embodiment, a gain expansion stage incorporates a Class-B stage, a Class-AB stage, or a combination of the two. In an exemplary embodiment, both the gain compression stage and gain expansion stage are provided with a replica current biasing scheme to ensure stable biasing current over variations in temperature, process, and/or supply voltage. Further disclosed is an output voltage biasing scheme to set the DC output voltage to ensure maximum linear operating range.
摘要翻译：公开了通过将展现增益压缩的放大器与增益扩展级相连接来扩展放大器的线性工作范围的技术。在示例性实施例中，增益扩展阶段包括B类阶段，AB类阶段或两者的组合。在示例性实施例中，增益压缩级和增益扩展级均被提供有复制电流偏置方案，以确保温度，过程和/或电源电压变化的稳定的偏置电流。进一步公开了一种用于设置直流输出电压以确保最大线性工作范围的输出电压偏置方案。

9. 发明申请

US20090267657A1 METHOD AND APPARATUS FOR DIVIDER UNIT SYNCHRONIZATION 有权
标题翻译：用于分流器单元同步的方法和装置
公开(公告)号：US20090267657A1
公开(公告)日：2009-10-29
申请号：US12111561
申请日：2008-04-29
申请人： Bo Sun , Sankaran Aniruddhan , Sriramgopal Sridhara
发明人： Bo Sun , Sankaran Aniruddhan , Sriramgopal Sridhara
IPC分类号： H03L7/00
CPC分类号： G06F1/12 , G06F1/3203 , G06F1/3287 , Y02D10/171
摘要： A method an apparatus for synchronizing phases of one or more divider units comprise powering on a master divider unit to provide a reference signal. A phase of a slave divider unit is synchronized to the reference signal from the master divider unit by providing a power on pulse at the slave divider unit, synchronizing the phase of the slave divider unit to the reference signal using a digitally controlled oscillator, and powering on the slave divider unit after a first predetermined delay period following a rising edge of the power on pulse. By synchronizing a slave divider unit to the reference signal from the master divider unit, any number of slave divider units may be powered on and in-phase with each other.
摘要翻译：一种用于同步一个或多个除法器单元的相位的装置的方法包括在主分频器单元上供电以提供参考信号。从分频器单元的相位通过在从分频器单元处提供通电脉冲而与来自主分频器单元的参考信号同步，使用数字控制的振荡器将从分频器单元的相位与参考信号同步，在通电脉冲的上升沿之后的第一预定延迟时段之后的从分频器单元上。通过将从属分频器单元与来自主分频器单元的参考信号同步，任何数量的从分频器单元可以通电并且彼此同相。

10. 发明授权

US08099127B2 Multi-mode configurable transmitter circuit 有权
标题翻译：多模式可配置发射机电路
公开(公告)号：US08099127B2
公开(公告)日：2012-01-17
申请号：US12184341
申请日：2008-08-01
申请人： Chiewcharn Narathong , Sankaran Aniruddhan
发明人： Chiewcharn Narathong , Sankaran Aniruddhan
IPC分类号： H04M1/00 , H04B1/04
CPC分类号： H04B1/0483 , H03F1/02 , H03F1/0277 , H03F3/195 , H03F3/211 , H03F3/24 , H03F3/245 , H03F3/68 , H03F3/72 , H03F2200/18 , H03F2200/27 , H03F2200/336 , H03F2200/411 , H03F2200/534 , H03F2203/21136 , H03F2203/7206 , H03F2203/7215 , H03F2203/7236 , H04B2001/045
摘要： Method and apparatus for configuring a transmitter circuit to support multiple modes and/or frequency bands. In an embodiment, a pre-driver amplifier (pDA) in a transmit (TX) signal path is selectively bypassed by a controllable switch. The switch can be controlled based on a mode of operation of the transmitter circuit. Further techniques are disclosed for selectively coupling the output of a driver amplifier (DA) to at least one of a plurality of off-chip connections, each connection coupling the DA output to a set of off-chip components.
摘要翻译：用于配置发射机电路以支持多个模式和/或频带的方法和装置。在一个实施例中，发射（TX）信号路径中的预驱动放大器（pDA）由可控开关选择性旁路。可以基于发射机电路的操作模式来控制开关。公开了用于选择性地将驱动器放大器（DA）的输出耦合到多个片外连接中的至少一个的其它技术，每个连接将DA输出耦合到一组片外部件。

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