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1. 发明申请

US20210103403A1 END-TO-END DATA PLANE OFFLOADING FOR DISTRIBUTED STORAGE USING PROTOCOL HARDWARE AND PISA DEVICES 有权
公开(公告)号：US20210103403A1
公开(公告)日：2021-04-08
申请号：US17092640
申请日：2020-11-09
申请人： Shaopeng He , Yadong Li , Ziye Yang , Changpeng Liu , Haitao Kang , Cunming Liang , Gang Cao , Scott Peterson , Sujoy Sen , Yi Zou , Arun Raghunath
发明人： Shaopeng He , Yadong Li , Ziye Yang , Changpeng Liu , Haitao Kang , Cunming Liang , Gang Cao , Scott Peterson , Sujoy Sen , Yi Zou , Arun Raghunath
IPC分类号： G06F3/06
摘要： Methods and apparatus for end-to-end data plane offloading for distributed storage using protocol hardware and Protocol Independent Switch Architecture (PISA) devices. Hardware-based data plane forwarding is implemented in compute and storage switches that comprise smart server switches running software executing in a kernel and user space. The compute switch is coupled to one or more compute servers/nodes and the storage server is coupled to one or more storage servers or storage arrays. The hardware-based data plane forwarding facilitates an end-to-end data plane between the computer server(s) and storage server(s)/array(s) that is offloaded to hardware. In one example the software comprises Ceph components used to implement control plane operations in connection with hardware offloaded data plane operations, and storage traffic employs the NVMe-oF protocol and the kernels include NVMe-oF modules. In one aspect the hardware-based data plane forwarding is implemented using programmable P4switch chips. In one aspect the storage and server switches are Top of Rack (ToR) switches.

2. 发明申请

US20190325227A1 TRANSMISSION, CACHING, AND SEARCHING OF VIDEO STREAMS BASED ON FRAME DEPENDENCIES AND CONTENT 审中-公开
公开(公告)号：US20190325227A1
公开(公告)日：2019-10-24
申请号：US16457818
申请日：2019-06-28
申请人： Ned M. Smith , Yi Zou , Shao-Wen Yang , Gang Shen
发明人： Ned M. Smith , Yi Zou , Shao-Wen Yang , Gang Shen
IPC分类号： G06K9/00 , G06F16/738
摘要： In one embodiment, an apparatus comprises processing circuitry to: receive, via a network interface, a video stream comprising a plurality of video frames; identify a plurality of dependencies among the plurality of video frames; identify, based on the plurality of dependencies, a first subset of video frames to be transmitted using a first transmission method and a second subset of video frames to be transmitted using a second transmission method, wherein the first subset of video frames and the second subset of video frames are identified from the plurality of video frames, and wherein the first transmission method provides a higher quality of service than the second transmission method; transmit, via the network interface, the first subset of video frames to a corresponding destination using the first transmission method; and transmit, via the network interface, the second subset of video frames to the corresponding destination using the second transmission method.

3. 发明授权

US09122160B2 Method and apparatus for performing optical proximity and photomask correction 有权
标题翻译：用于执行光学接近和光掩模校正的方法和装置
公开(公告)号：US09122160B2
公开(公告)日：2015-09-01
申请号：US13832557
申请日：2013-03-15
申请人： Gek Soon Chua , Yi Zou , Wei-Long Wang , Byoung Il Choi
发明人： Gek Soon Chua , Yi Zou , Wei-Long Wang , Byoung Il Choi
IPC分类号： G06F17/50 , G03F1/00
CPC分类号： G03F1/144 , G03F1/36 , G06F17/5081 , G06F2217/12 , Y02P90/265 , Y02T10/82
摘要： An approach is provided for enabling simulation of photomask contour shapes, performing verification on the simulated photomask shapes, and correcting errors in OPC correction or bad fracturing methods to perform photomask proximity correction in real time before physically writing of the photomask. Embodiments include performing optical proximity correction of a photomask of a semiconductor layout to generate a corrected photomask, simulating the corrected photomask to generate one or more simulated contour shapes within a simulated photomask, verifying the simulated contour shapes to determine errors associated with the simulated photomask, and correcting the errors in the simulated contour shapes of the simulated photomask to generate a final photomask.
摘要翻译：提供了一种方法，用于实现光掩模轮廓形状的模拟，对模拟的光掩模形状进行验证，以及校正OPC校正中的错误或不良压裂方法，以在物理写入光掩模之前实时执行光掩模接近校正。实施例包括执行半导体布局的光掩模的光学邻近校正以产生校正的光掩模，模拟校正的光掩模以在模拟光掩模内生成一个或多个模拟轮廓形状，验证模拟轮廓形状以确定与模拟光掩模相关联的误差，并且校正模拟光掩模的模拟轮廓形状中的误差以产生最终的光掩模。

4. 发明授权

US08555215B2 Methods for decomposing circuit design layouts and for fabricating semiconductor devices using decomposed patterns 有权
标题翻译：分解电路设计布局和使用分解模式制造半导体器件的方法
公开(公告)号：US08555215B2
公开(公告)日：2013-10-08
申请号：US13400445
申请日：2012-02-20
申请人： Yi Zou , Swamy Maddu , Lynn T. Wang , Vito Dai , Luigi Capodieci , Peng Xie
发明人： Yi Zou , Swamy Maddu , Lynn T. Wang , Vito Dai , Luigi Capodieci , Peng Xie
IPC分类号： G06F17/50
CPC分类号： G03F1/70
摘要： Methods for fabricating semiconductor devices are provided. In an embodiment, a method of fabricating a semiconductor device includes scanning a circuit design layout and proposing patterns for decomposed layouts. The proposed patterns are then compared with a library of prior patterns including a category of forbidden patterns and a category of preferred patterns. If a selected proposed pattern matches a forbidden pattern, the selected proposed pattern is eliminated. If the selected proposed pattern matches a preferred pattern, then the selected proposed pattern is identified for use in the decomposed layouts. Decomposed layouts are generated from the identified patterns. A plurality of masks is fabricated based on the decomposed layouts. Then a multiple patterning lithographic technique is performed with the plurality of masks on a semiconductor substrate.
摘要翻译：提供制造半导体器件的方法。在一个实施例中，制造半导体器件的方法包括扫描电路设计布局并提出用于分解布局的图案。然后将所提出的模式与包括禁止模式类别和优选模式类别的先前模式的库进行比较。如果所选择的提议模式匹配禁止模式，则删除所选择的提议模式。如果所选择的提出的模式匹配优选模式，则所选择的提出的模式被识别用于分解的布局。分辨的布局是从识别的图案生成的。基于分解的布局制造多个掩模。然后用半导体衬底上的多个掩模进行多重图形化光刻技术。

5. 发明申请

US20090193369A1 PROCESS FOR DESIGN OF SEMICONDUCTOR CIRCUITS 有权
标题翻译：半导体电路设计工艺
公开(公告)号：US20090193369A1
公开(公告)日：2009-07-30
申请号：US12022860
申请日：2008-01-30
申请人： Darin A. Chan , Yi Zou , Yuansheng Ma , Marilyn Wright , Mark Michael , Donna Michael
发明人： Darin A. Chan , Yi Zou , Yuansheng Ma , Marilyn Wright , Mark Michael , Donna Michael
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/10
摘要： The present invention generates model scenarios of semiconductor chip design and uses interpolation and Monte Carlo, with random number generation inputs, techniques to iteratively assess the models for a more comprehensive and accurate assessment of design space, and evaluation under projected manufacturing conditions. This evaluation information is then incorporated into design rules in order to improve yield.
摘要翻译：本发明生成半导体芯片设计的模型场景，并使用插值和蒙特卡罗随机数生成输入，迭代评估模型，以更全面，准确地评估设计空间，并在预计制造条件下进行评估。然后将该评估信息并入设计规则以提高产量。

6. 发明授权

US08103979B2 System for generating and optimizing mask assist features based on hybrid (model and rules) methodology 有权
标题翻译：基于混合（模型和规则）方法生成和优化掩模辅助功能的系统
公开(公告)号：US08103979B2
公开(公告)日：2012-01-24
申请号：US12254172
申请日：2008-10-20
申请人： Yi Zou , Luigi Capodieci
发明人： Yi Zou , Luigi Capodieci
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： An optimal assist feature rules set for an integrated circuit design layout is created using inverse lithography. The full chip layout is lithographically simulated, and printability failure areas are determined. The features are analyzed for feature layout patterns, and inverse lithography is performed on the unique feature layouts to form assist features. The resulting layout of assist features is analyzed to create an assist feature rules set. The rules can then be applied to a photomask patterned with the integrated circuit design layout to print optimal assist features. The resulting photomask may be used to form an integrated circuit on a semiconductor substrate.
摘要翻译：使用反光刻法创建集成电路设计布局的最佳辅助特征规则集。全芯片布局被光刻仿真，并确定了可印刷性故障区域。对特征布局图案进行特征分析，并对独特特征布局进行反光刻以形成辅助特征。分析所得到的辅助特征布局以创建辅助特征规则集。然后可以将规则应用于利用集成电路设计布局图案化的光掩模，以打印最佳辅助特征。所得到的光掩模可用于在半导体衬底上形成集成电路。

7. 发明授权

US09102782B2 Transparent copolyester, preparing method thereof and articles made from the same 有权
标题翻译：透明共聚聚酯，其制备方法和由其制成的制品
公开(公告)号：US09102782B2
公开(公告)日：2015-08-11
申请号：US13571317
申请日：2012-08-09
申请人： Ning Xu , Guixiang Zhu , Wei Zhang , Ling Han , Yi Zou , Wenxi Ji
发明人： Ning Xu , Guixiang Zhu , Wei Zhang , Ling Han , Yi Zou , Wenxi Ji
IPC分类号： C08G18/42 , C08G63/60 , C08G63/91 , C08G18/73 , C08G18/34
CPC分类号： C08G18/4216 , C08G18/348 , C08G18/73 , C08G63/60 , C08G63/91
摘要： The present invention relates to a transparent copolyester, wherein the transparent copolyester comprises an aliphatic-aromatic copolyester segment A, a segment B having repeating units —O—CH(CH3)—C(O)—, and structural units C derived from polyisocyanate(s), wherein the weight ratio for the segment A, segment B and structural unit C is 100:(100-2000):(0.1-10) and wherein the weight-average molecular weight Mw of the transparent copolyester is from 50,000 to 1,000,000. The present invention further relates to a preparation method for a transparent copolyester, including polymerizing lactide, a hydroxyl-terminated aliphatic-aromatic copolyester and a polyisocyanate in the presence of a catalyst; wherein the weight ratio for the aliphatic-aromatic copolyester, lactide and polyisocyanate is 100:(100-2000):(0.1-10). The present invention further relates to a transparent copolyester prepared by said method and an article made from the transparent copolyester according to present invention.
摘要翻译：本发明涉及一种透明共聚酯，其中该透明共聚聚酯包括脂肪族 - 芳族共聚酯链段A，具有重复单元-O-CH（CH 3）-C（O）的链段B和衍生自多异氰酸酯的结构单元C s），其中段A，段B和结构单元C的重量比为100：（100-2000）：（0.1-10），并且其中透明共聚酯的重均分子量Mw为50,000至1,000,000 。本发明还涉及一种透明共聚酯的制备方法，包括在催化剂存在下聚合丙交酯，羟基封端的脂族 - 芳族共聚酯和多异氰酸酯; 其中脂族 - 芳族共聚酯，丙交酯和多异氰酸酯的重量比为100：（100-2000）：（0.1-10）。本发明还涉及通过所述方法制备的透明共聚酯和由根据本发明的透明共聚酯制成的制品。

8. 发明授权

US08859690B2 Biodegradable composite, the preparation process thereof, and a disposable article made therefrom 有权
标题翻译：可生物降解复合材料，其制备方法和由其制成的一次性制品
公开(公告)号：US08859690B2
公开(公告)日：2014-10-14
申请号：US13531292
申请日：2012-06-22
申请人： Guixiang Zhu , Wei Zhang , Ling Han , Ning Xu , Yi Zou , Wenxi Ji
发明人： Guixiang Zhu , Wei Zhang , Ling Han , Ning Xu , Yi Zou , Wenxi Ji
IPC分类号： C08G63/91 , C08L67/02 , C08L67/04 , C08K5/14
CPC分类号： C08L67/02 , C08K5/14 , C08L67/04 , C08L2205/02 , C08L2205/03
摘要： The present invention relates to a biodegradable composite and its preparation process, which composite is prepared by mixing feed stocks comprising a polylactic acid, an aliphatic-aromatic copolyester A, an aliphatic-aromatic copolyester B and an organic peroxide at a temperature between about 100 and about 200° C. The present invention also relates to a disposable article, which is prepared from said biodegradable composite.
摘要翻译：本发明涉及可生物降解的复合材料及其制备方法，该复合材料通过将包含聚乳酸，脂族 - 芳族共聚酯A，脂族 - 芳族共聚酯B和有机过氧化物B的原料在约100℃和约200℃。本发明还涉及由所述可生物降解的复合材料制备的一次性制品。

9. 发明申请

US20140282299A1 METHOD AND APPARATUS FOR PERFORMING OPTICAL PROXIMITY AND PHOTOMASK CORRECTION 有权
标题翻译：用于执行光学近似和光电子校正的方法和装置
公开(公告)号：US20140282299A1
公开(公告)日：2014-09-18
申请号：US13832557
申请日：2013-03-15
申请人： Gek Soon CHUA , Yi Zou , Wei-Long Wang , Byoung IL Choi
发明人： Gek Soon CHUA , Yi Zou , Wei-Long Wang , Byoung IL Choi
IPC分类号： G03F1/00 , G06F17/50
CPC分类号： G03F1/144 , G03F1/36 , G06F17/5081 , G06F2217/12 , Y02P90/265 , Y02T10/82
摘要： An approach is provided for enabling simulation of photomask contour shapes, performing verification on the simulated photomask shapes, and correcting errors in OPC correction or bad fracturing methods to perform photomask proximity correction in real time before physically writing of the photomask. Embodiments include performing optical proximity correction of a photomask of a semiconductor layout to generate a corrected photomask, simulating the corrected photomask to generate one or more simulated contour shapes within a simulated photomask, verifying the simulated contour shapes to determine errors associated with the simulated photomask, and correcting the errors in the simulated contour shapes of the simulated photomask to generate a final photomask.
摘要翻译：提供了一种方法，用于实现光掩模轮廓形状的模拟，对模拟的光掩模形状进行验证，以及校正OPC校正中的错误或不良压裂方法，以在物理写入光掩模之前实时执行光掩模接近校正。实施例包括执行半导体布局的光掩模的光学邻近校正以产生校正的光掩模，模拟校正的光掩模以在模拟光掩模内生成一个或多个模拟轮廓形状，验证模拟轮廓形状以确定与模拟光掩模相关联的误差，并且校正模拟光掩模的模拟轮廓形状中的误差以产生最终的光掩模。

10. 发明申请

US20130219347A1 METHODS FOR DECOMPOSING CIRCUIT DESIGN LAYOUTS AND FOR FABRICATING SEMICONDUCTOR DEVICES USING DECOMPOSED PATTERNS 有权
标题翻译：用于分解电路设计层和使用分解图案制作半导体器件的方法
公开(公告)号：US20130219347A1
公开(公告)日：2013-08-22
申请号：US13400445
申请日：2012-02-20
申请人： Yi Zou , Swamy Muddu , Lynn T. Wang , Vito Dai , Luigi Capodieci , Peng Xie
发明人： Yi Zou , Swamy Muddu , Lynn T. Wang , Vito Dai , Luigi Capodieci , Peng Xie
IPC分类号： G06F17/50
CPC分类号： G03F1/70
摘要： Methods for fabricating semiconductor devices are provided. In an embodiment, a method of fabricating a semiconductor device includes scanning a circuit design layout and proposing patterns for decomposed layouts. The proposed patterns are then compared with a library of prior patterns including a category of forbidden patterns and a category of preferred patterns. If a selected proposed pattern matches a forbidden pattern, the selected proposed pattern is eliminated. If the selected proposed pattern matches a preferred pattern, then the selected proposed pattern is identified for use in the decomposed layouts. Decomposed layouts are generated from the identified patterns. A plurality of masks is fabricated based on the decomposed layouts. Then a multiple patterning lithographic technique is performed with the plurality of masks on a semiconductor substrate.
摘要翻译：提供制造半导体器件的方法。在一个实施例中，制造半导体器件的方法包括扫描电路设计布局并提出用于分解布局的图案。然后将所提出的模式与包括禁止模式类别和优选模式类别的先前模式的库进行比较。如果所选择的提议模式匹配禁止模式，则删除所选择的提议模式。如果所选择的提出的模式匹配优选模式，则所选择的提出的模式被识别用于分解的布局。分辨的布局是从识别的图案生成的。基于分解的布局制造多个掩模。然后用半导体衬底上的多个掩模进行多重图形化光刻技术。

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