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1. 发明申请

US20080235457A1 Dynamic quality of service (QoS) for a shared cache 有权
标题翻译：共享缓存的动态服务质量（QoS）
公开(公告)号：US20080235457A1
公开(公告)日：2008-09-25
申请号：US11726238
申请日：2007-03-21
申请人： William C. Hasenplaugh , Li Zhao , Ravishankar Iyer , Ramesh Illikkal , Srihari Makineni , Donald Newell , Aamer Jaleel , Simon C. Steely
发明人： William C. Hasenplaugh , Li Zhao , Ravishankar Iyer , Ramesh Illikkal , Srihari Makineni , Donald Newell , Aamer Jaleel , Simon C. Steely
IPC分类号： G06F12/00
CPC分类号： G06F12/084 , G06F12/0842
摘要： In one embodiment, the present invention includes a method for associating a first priority indicator with data stored in a first entry of a shared cache memory by a core to indicate a priority level of a first thread, and associating a second priority indicator with data stored in a second entry of the shared cache memory by a graphics engine to indicate a priority level of a second thread. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于将第一优先级指示符与存储在共享高速缓冲存储器的第一条目中的数据相关联以指示第一线程的优先级，并且将第二优先级指示符与存储的数据相关联的方法在图形引擎的共享高速缓冲存储器的第二条目中指示第二线程的优先级。描述和要求保护其他实施例。

2. 发明授权

US07725657B2 Dynamic quality of service (QoS) for a shared cache 有权
标题翻译：共享缓存的动态服务质量（QoS）
公开(公告)号：US07725657B2
公开(公告)日：2010-05-25
申请号：US11726238
申请日：2007-03-21
申请人： William C. Hasenplaugh , Li Zhao , Ravishankar Iyer , Ramesh Illikkal , Srihari Makineni , Donald Newell , Aamer Jaleel , Simon C. Steely, Jr.
发明人： William C. Hasenplaugh , Li Zhao , Ravishankar Iyer , Ramesh Illikkal , Srihari Makineni , Donald Newell , Aamer Jaleel , Simon C. Steely, Jr.
IPC分类号： G06F12/06
CPC分类号： G06F12/084 , G06F12/0842
摘要： In one embodiment, the present invention includes a method for associating a first priority indicator with data stored in a first entry of a shared cache memory by a core to indicate a priority level of a first thread, and associating a second priority indicator with data stored in a second entry of the shared cache memory by a graphics engine to indicate a priority level of a second thread. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于将第一优先级指示符与存储在共享高速缓冲存储器的第一条目中的数据相关联以指示第一线程的优先级，并且将第二优先级指示符与存储的数据相关联的方法在图形引擎的共享高速缓冲存储器的第二条目中指示第二线程的优先级。描述和要求保护其他实施例。

3. 发明授权

US08407421B2 Cache spill management techniques using cache spill prediction 失效
标题翻译：缓存溢出管理技术使用缓存溢出预测
公开(公告)号：US08407421B2
公开(公告)日：2013-03-26
申请号：US12639214
申请日：2009-12-16
申请人： Simon C. Steely, Jr. , William C. Hasenplaugh , Aamer Jaleel , George Z. Chrysos
发明人： Simon C. Steely, Jr. , William C. Hasenplaugh , Aamer Jaleel , George Z. Chrysos
IPC分类号： G06F12/00
CPC分类号： G06F12/0806 , G06F12/12
摘要： An apparatus and method is described herein for intelligently spilling cache lines. Usefulness of cache lines previously spilled from a source cache is learned, such that later evictions of useful cache lines from a source cache are intelligently selected for spill. Furthermore, another learning mechanism—cache spill prediction—may be implemented separately or in conjunction with usefulness prediction. The cache spill prediction is capable of learning the effectiveness of remote caches at holding spilled cache lines for the source cache. As a result, cache lines are capable of being intelligently selected for spill and intelligently distributed among remote caches based on the effectiveness of each remote cache in holding spilled cache lines for the source cache.
摘要翻译：这里描述了用于智能地溢出高速缓存行的装置和方法。了解先前从源缓存溢出的高速缓存行的有用性，从而智能地选择来自源缓存的随后驱逐的溢出。此外，另一种学习机制 - 缓存溢出预测 - 可以单独实施或结合有用性预测来实现。高速缓存溢出预测能够学习在为源缓存保留溢出的高速缓存行时远程高速缓存的有效性。因此，基于每个远程高速缓存在保存用于源高速缓存的溢出高速缓存行的有效性的情况下，高速缓存行能够被智能地选择为溢出并且智能地分布在远程高速缓存中。

4. 发明申请

US20110145501A1 CACHE SPILL MANAGEMENT TECHNIQUES 失效
标题翻译：缓存溢出管理技术
公开(公告)号：US20110145501A1
公开(公告)日：2011-06-16
申请号：US12639214
申请日：2009-12-16
申请人： Simon C. Steely, JR. , William C. Hasenplaugh , Aamer Jaleel , George Z. Chrysos
发明人： Simon C. Steely, JR. , William C. Hasenplaugh , Aamer Jaleel , George Z. Chrysos
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0806 , G06F12/12
摘要： An apparatus and method is described herein for intelligently spilling cache lines. Usefulness of cache lines previously spilled from a source cache is learned, such that later evictions of useful cache lines from a source cache are intelligently selected for spill. Furthermore, another learning mechanism—cache spill prediction—may be implemented separately or in conjunction with usefulness prediction. The cache spill prediction is capable of learning the effectiveness of remote caches at holding spilled cache lines for the source cache. As a result, cache lines are capable of being intelligently selected for spill and intelligently distributed among remote caches based on the effectiveness of each remote cache in holding spilled cache lines for the source cache.
摘要翻译：这里描述了用于智能地溢出高速缓存行的装置和方法。了解先前从源缓存溢出的高速缓存行的有用性，从而智能地选择来自源缓存的随后驱逐的溢出。此外，另一种学习机制 - 缓存溢出预测 - 可以单独实施或结合有用性预测来实现。高速缓存溢出预测能够学习在为源缓存保留溢出的高速缓存行时远程高速缓存的有效性。因此，基于每个远程高速缓存在保存用于源高速缓存的溢出高速缓存行的有效性的情况下，高速缓存行能够被智能地选择为溢出并且智能地分布在远程高速缓存中。

5. 发明授权

US09262327B2 Signature based hit-predicting cache 有权
标题翻译：基于签名的命中预测缓存
公开(公告)号：US09262327B2
公开(公告)日：2016-02-16
申请号：US13538390
申请日：2012-06-29
申请人： Simon C. Steely, Jr. , William C. Hasenplaugh , Aamer Jaleel , Joel S. Emer , Carole-Jean Wu
发明人： Simon C. Steely, Jr. , William C. Hasenplaugh , Aamer Jaleel , Joel S. Emer , Carole-Jean Wu
IPC分类号： G06F12/08
CPC分类号： G06F12/0862
摘要： An apparatus may comprise a cache file having a plurality of cache lines and a hit predictor. The hit predictor may contain a table of counter values indexed with signatures that are associated with the plurality of cache lines. The apparatus may fill cache lines into the cache file with either low or high priority. Low priority lines may be chosen to be replaced by a replacement algorithm before high priority lines. In this way, the cache naturally may contain more high priority lines than low priority ones. This priority filling process may improve the performance of most replacement schemes including the best known schemes which are already doing better than LRU.
摘要翻译：装置可以包括具有多个高速缓存行和命中预测器的高速缓存文件。命中预测器可以包含用与多个高速缓存行相关联的签名索引的计数器值的表。该装置可以以低优先级或高优先级将高速缓存行填充到高速缓存文件中。低优先级行可以被选择为在高优先级行之前由替换算法代替。以这种方式，高速缓存当然可以包含比优先级更高的优先级更高的行。该优先填充过程可以改善大多数替换方案的性能，包括已经比LRU更好的已知方案。

6. 发明授权

US08769209B2 Method and apparatus for achieving non-inclusive cache performance with inclusive caches 有权
标题翻译：用于通过包含缓存实现非包容性缓存性能的方法和装置
公开(公告)号：US08769209B2
公开(公告)日：2014-07-01
申请号：US12973051
申请日：2010-12-20
申请人： Aamer Jaleel , Simon C. Steely, Jr. , Eric R. Borch , Malini K. Bhandaru , Joel S. Emer
发明人： Aamer Jaleel , Simon C. Steely, Jr. , Eric R. Borch , Malini K. Bhandaru , Joel S. Emer
IPC分类号： G06F12/12
CPC分类号： G06F12/0813 , G06F12/128
摘要： An apparatus and method for improving cache performance in a computer system having a multi-level cache hierarchy. For example, one embodiment of a method comprises: selecting a first line in a cache at level N for potential eviction; querying a cache at level M in the hierarchy to determine whether the first cache line is resident in the cache at level M, wherein M
摘要翻译：一种用于在具有多级高速缓存层级的计算机系统中提高高速缓存性能的装置和方法。例如，方法的一个实施例包括：在级别N的高速缓存中选择潜在驱逐的第一行; 查询层级中的级别M的高速缓存，以确定第一高速缓存行是否驻留在级别M的高速缓存中，其中M

7. 发明申请

US20120084497A1 Instruction Prefetching Using Cache Line History 有权
标题翻译：使用缓存线历史记录进行指令预取
公开(公告)号：US20120084497A1
公开(公告)日：2012-04-05
申请号：US12895387
申请日：2010-09-30
申请人： Samantika Subramaniam , Aamer Jaleel , Simon C. Steely, JR.
发明人： Samantika Subramaniam , Aamer Jaleel , Simon C. Steely, JR.
IPC分类号： G06F12/06 , G06F12/08
CPC分类号： G06F12/0862 , G06F9/3816 , G06F2212/452 , G06F2212/6024 , Y02D10/13
摘要： An apparatus of an aspect includes a prefetch cache line address predictor to receive a cache line address and to predict a next cache line address to be prefetched. The next cache line address may indicate a cache line having at least 64-bytes of instructions. The prefetch cache line address predictor may have a cache line target history storage to store a cache line target history for each of multiple most recent corresponding cache lines. Each cache line target history may indicate whether the corresponding cache line had a sequential cache line target or a non-sequential cache line target. The cache line address predictor may also have a cache line target history predictor. The cache line target history predictor may predict whether the next cache line address is a sequential cache line address or a non-sequential cache line address, based on the cache line target history for the most recent cache lines.
摘要翻译：一方面的装置包括预取高速缓存行地址预测器，用于接收高速缓存行地址并预测要预取的下一个高速缓存行地址。下一个高速缓存行地址可以指示具有至少64字节指令的高速缓存行。预取高速缓存线地址预测器可以具有高速缓存行目标历史存储器，以存储多个最新对应的高速缓存行中的每一个的高速缓存行目标历史。每个高速缓存行目标历史可以指示对应的高速缓存线是否具有顺序高速缓存行目标或非顺序高速缓存行目标。高速缓存行地址预测器也可以具有高速缓存行目标历史预测器。高速缓存行目标历史预测器可以基于最近的高速缓存行的高速缓存行目标历史来预测下一个高速缓存行地址是顺序高速缓存行地址还是非顺序高速缓存行地址。

8. 发明授权

US08533422B2 Instruction prefetching using cache line history 有权
标题翻译：指令预取使用高速缓存行历史记录
公开(公告)号：US08533422B2
公开(公告)日：2013-09-10
申请号：US12895387
申请日：2010-09-30
申请人： Samantika Subramaniam , Aamer Jaleel , Simon C. Steely, Jr.
发明人： Samantika Subramaniam , Aamer Jaleel , Simon C. Steely, Jr.
IPC分类号： G06F12/06 , G06F12/08
CPC分类号： G06F12/0862 , G06F9/3816 , G06F2212/452 , G06F2212/6024 , Y02D10/13
摘要： An apparatus of an aspect includes a prefetch cache line address predictor to receive a cache line address and to predict a next cache line address to be prefetched. The next cache line address may indicate a cache line having at least 64-bytes of instructions. The prefetch cache line address predictor may have a cache line target history storage to store a cache line target history for each of multiple most recent corresponding cache lines. Each cache line target history may indicate whether the corresponding cache line had a sequential cache line target or a non-sequential cache line target. The cache line address predictor may also have a cache line target history predictor. The cache line target history predictor may predict whether the next cache line address is a sequential cache line address or a non-sequential cache line address, based on the cache line target history for the most recent cache lines.
摘要翻译：一方面的装置包括预取高速缓存行地址预测器，用于接收高速缓存行地址并预测要预取的下一个高速缓存行地址。下一个高速缓存行地址可以指示具有至少64字节指令的高速缓存行。预取高速缓存线地址预测器可以具有高速缓存行目标历史存储器，以存储多个最新对应的高速缓存行中的每一个的高速缓存行目标历史。每个高速缓存行目标历史可以指示对应的高速缓存线是否具有顺序高速缓存行目标或非顺序高速缓存行目标。高速缓存行地址预测器也可以具有高速缓存行目标历史预测器。高速缓存行目标历史预测器可以基于最近的高速缓存行的高速缓存行目标历史来预测下一个高速缓存行地址是顺序高速缓存行地址还是非顺序高速缓存行地址。

9. 发明申请

US20120159073A1 METHOD AND APPARATUS FOR ACHIEVING NON-INCLUSIVE CACHE PERFORMANCE WITH INCLUSIVE CACHES 有权
标题翻译：用于实现包含缓存的非特定缓存性能的方法和设备
公开(公告)号：US20120159073A1
公开(公告)日：2012-06-21
申请号：US12973051
申请日：2010-12-20
申请人： Aamer Jaleel , Simon C. Steely, JR. , Eric R. Borch , Malini K. Bhandaru , Joel S. Emer
发明人： Aamer Jaleel , Simon C. Steely, JR. , Eric R. Borch , Malini K. Bhandaru , Joel S. Emer
IPC分类号： G06F12/08
CPC分类号： G06F12/0813 , G06F12/128
摘要： An apparatus and method for improving cache performance in a computer system having a multi-level cache hierarchy. For example, one embodiment of a method comprises: selecting a first line in a cache at level N for potential eviction; querying a cache at level M in the hierarchy to determine whether the first cache line is resident in the cache at level M, wherein M
摘要翻译：一种用于在具有多级高速缓存层级的计算机系统中提高高速缓存性能的装置和方法。例如，方法的一个实施例包括：在级别N的高速缓存中选择潜在驱逐的第一行; 查询层级中的级别M的高速缓存，以确定第一高速缓存行是否驻留在级别M的高速缓存中，其中M

10. 发明申请

US20210004328A1 HARDWARE/SOFTWARE CO-OPTIMIZATION TO IMPROVE PERFORMANCE AND ENERGY FOR INTER-VM COMMUNICATION FOR NFVS AND OTHER PRODUCER-CONSUMER WORKLOADS 有权
公开(公告)号：US20210004328A1
公开(公告)日：2021-01-07
申请号：US17027248
申请日：2020-09-21
申请人： Ren Wang , Andrew J. Herdrich , Yen-cheng Liu , Herbert H. Hum , Jong Soo Park , Christopher J. Hughes , Namakkal N. Venkatesan , Adrian C. Moga , Aamer Jaleel , Zeshan A. Chishti , Mesut A. Ergin , Jr-shian Tsai , Alexander W. Min , Tsung-yuan C. Tai , Christian Maciocco , Rajesh Sankaran
发明人： Ren Wang , Andrew J. Herdrich , Yen-cheng Liu , Herbert H. Hum , Jong Soo Park , Christopher J. Hughes , Namakkal N. Venkatesan , Adrian C. Moga , Aamer Jaleel , Zeshan A. Chishti , Mesut A. Ergin , Jr-shian Tsai , Alexander W. Min , Tsung-yuan C. Tai , Christian Maciocco , Rajesh Sankaran
IPC分类号： G06F12/0842 , G06F12/0831 , G06F12/0893 , G06F12/109 , G06F12/0813 , G06F9/455
摘要： Methods and apparatus implementing Hardware/Software co-optimization to improve performance and energy for inter-VM communication for NFVs and other producer-consumer workloads. The apparatus include multi-core processors with multi-level cache hierarchies including and L1 and L2 cache for each core and a shared last-level cache (LLC). One or more machine-level instructions are provided for proactively demoting cachelines from lower cache levels to higher cache levels, including demoting cachelines from L1/L2 caches to an LLC. Techniques are also provided for implementing hardware/software co-optimization in multi-socket NUMA architecture system, wherein cachelines may be selectively demoted and pushed to an LLC in a remote socket. In addition, techniques are disclosure for implementing early snooping in multi-socket systems to reduce latency when accessing cachelines on remote sockets.

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