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1. 发明授权

US07725657B2 Dynamic quality of service (QoS) for a shared cache 有权
标题翻译：共享缓存的动态服务质量（QoS）
公开(公告)号：US07725657B2
公开(公告)日：2010-05-25
申请号：US11726238
申请日：2007-03-21
申请人： William C. Hasenplaugh , Li Zhao , Ravishankar Iyer , Ramesh Illikkal , Srihari Makineni , Donald Newell , Aamer Jaleel , Simon C. Steely, Jr.
发明人： William C. Hasenplaugh , Li Zhao , Ravishankar Iyer , Ramesh Illikkal , Srihari Makineni , Donald Newell , Aamer Jaleel , Simon C. Steely, Jr.
IPC分类号： G06F12/06
CPC分类号： G06F12/084 , G06F12/0842
摘要： In one embodiment, the present invention includes a method for associating a first priority indicator with data stored in a first entry of a shared cache memory by a core to indicate a priority level of a first thread, and associating a second priority indicator with data stored in a second entry of the shared cache memory by a graphics engine to indicate a priority level of a second thread. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于将第一优先级指示符与存储在共享高速缓冲存储器的第一条目中的数据相关联以指示第一线程的优先级，并且将第二优先级指示符与存储的数据相关联的方法在图形引擎的共享高速缓冲存储器的第二条目中指示第二线程的优先级。描述和要求保护其他实施例。

2. 发明申请

US20080235457A1 Dynamic quality of service (QoS) for a shared cache 有权
标题翻译：共享缓存的动态服务质量（QoS）
公开(公告)号：US20080235457A1
公开(公告)日：2008-09-25
申请号：US11726238
申请日：2007-03-21
申请人： William C. Hasenplaugh , Li Zhao , Ravishankar Iyer , Ramesh Illikkal , Srihari Makineni , Donald Newell , Aamer Jaleel , Simon C. Steely
发明人： William C. Hasenplaugh , Li Zhao , Ravishankar Iyer , Ramesh Illikkal , Srihari Makineni , Donald Newell , Aamer Jaleel , Simon C. Steely
IPC分类号： G06F12/00
CPC分类号： G06F12/084 , G06F12/0842
摘要： In one embodiment, the present invention includes a method for associating a first priority indicator with data stored in a first entry of a shared cache memory by a core to indicate a priority level of a first thread, and associating a second priority indicator with data stored in a second entry of the shared cache memory by a graphics engine to indicate a priority level of a second thread. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于将第一优先级指示符与存储在共享高速缓冲存储器的第一条目中的数据相关联以指示第一线程的优先级，并且将第二优先级指示符与存储的数据相关联的方法在图形引擎的共享高速缓冲存储器的第二条目中指示第二线程的优先级。描述和要求保护其他实施例。

3. 发明授权

US08407421B2 Cache spill management techniques using cache spill prediction 失效
标题翻译：缓存溢出管理技术使用缓存溢出预测
公开(公告)号：US08407421B2
公开(公告)日：2013-03-26
申请号：US12639214
申请日：2009-12-16
申请人： Simon C. Steely, Jr. , William C. Hasenplaugh , Aamer Jaleel , George Z. Chrysos
发明人： Simon C. Steely, Jr. , William C. Hasenplaugh , Aamer Jaleel , George Z. Chrysos
IPC分类号： G06F12/00
CPC分类号： G06F12/0806 , G06F12/12
摘要： An apparatus and method is described herein for intelligently spilling cache lines. Usefulness of cache lines previously spilled from a source cache is learned, such that later evictions of useful cache lines from a source cache are intelligently selected for spill. Furthermore, another learning mechanism—cache spill prediction—may be implemented separately or in conjunction with usefulness prediction. The cache spill prediction is capable of learning the effectiveness of remote caches at holding spilled cache lines for the source cache. As a result, cache lines are capable of being intelligently selected for spill and intelligently distributed among remote caches based on the effectiveness of each remote cache in holding spilled cache lines for the source cache.
摘要翻译：这里描述了用于智能地溢出高速缓存行的装置和方法。了解先前从源缓存溢出的高速缓存行的有用性，从而智能地选择来自源缓存的随后驱逐的溢出。此外，另一种学习机制 - 缓存溢出预测 - 可以单独实施或结合有用性预测来实现。高速缓存溢出预测能够学习在为源缓存保留溢出的高速缓存行时远程高速缓存的有效性。因此，基于每个远程高速缓存在保存用于源高速缓存的溢出高速缓存行的有效性的情况下，高速缓存行能够被智能地选择为溢出并且智能地分布在远程高速缓存中。

4. 发明申请

US20110145501A1 CACHE SPILL MANAGEMENT TECHNIQUES 失效
标题翻译：缓存溢出管理技术
公开(公告)号：US20110145501A1
公开(公告)日：2011-06-16
申请号：US12639214
申请日：2009-12-16
申请人： Simon C. Steely, JR. , William C. Hasenplaugh , Aamer Jaleel , George Z. Chrysos
发明人： Simon C. Steely, JR. , William C. Hasenplaugh , Aamer Jaleel , George Z. Chrysos
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0806 , G06F12/12
摘要： An apparatus and method is described herein for intelligently spilling cache lines. Usefulness of cache lines previously spilled from a source cache is learned, such that later evictions of useful cache lines from a source cache are intelligently selected for spill. Furthermore, another learning mechanism—cache spill prediction—may be implemented separately or in conjunction with usefulness prediction. The cache spill prediction is capable of learning the effectiveness of remote caches at holding spilled cache lines for the source cache. As a result, cache lines are capable of being intelligently selected for spill and intelligently distributed among remote caches based on the effectiveness of each remote cache in holding spilled cache lines for the source cache.
摘要翻译：这里描述了用于智能地溢出高速缓存行的装置和方法。了解先前从源缓存溢出的高速缓存行的有用性，从而智能地选择来自源缓存的随后驱逐的溢出。此外，另一种学习机制 - 缓存溢出预测 - 可以单独实施或结合有用性预测来实现。高速缓存溢出预测能够学习在为源缓存保留溢出的高速缓存行时远程高速缓存的有效性。因此，基于每个远程高速缓存在保存用于源高速缓存的溢出高速缓存行的有效性的情况下，高速缓存行能够被智能地选择为溢出并且智能地分布在远程高速缓存中。

5. 发明授权

US09262327B2 Signature based hit-predicting cache 有权
标题翻译：基于签名的命中预测缓存
公开(公告)号：US09262327B2
公开(公告)日：2016-02-16
申请号：US13538390
申请日：2012-06-29
申请人： Simon C. Steely, Jr. , William C. Hasenplaugh , Aamer Jaleel , Joel S. Emer , Carole-Jean Wu
发明人： Simon C. Steely, Jr. , William C. Hasenplaugh , Aamer Jaleel , Joel S. Emer , Carole-Jean Wu
IPC分类号： G06F12/08
CPC分类号： G06F12/0862
摘要： An apparatus may comprise a cache file having a plurality of cache lines and a hit predictor. The hit predictor may contain a table of counter values indexed with signatures that are associated with the plurality of cache lines. The apparatus may fill cache lines into the cache file with either low or high priority. Low priority lines may be chosen to be replaced by a replacement algorithm before high priority lines. In this way, the cache naturally may contain more high priority lines than low priority ones. This priority filling process may improve the performance of most replacement schemes including the best known schemes which are already doing better than LRU.
摘要翻译：装置可以包括具有多个高速缓存行和命中预测器的高速缓存文件。命中预测器可以包含用与多个高速缓存行相关联的签名索引的计数器值的表。该装置可以以低优先级或高优先级将高速缓存行填充到高速缓存文件中。低优先级行可以被选择为在高优先级行之前由替换算法代替。以这种方式，高速缓存当然可以包含比优先级更高的优先级更高的行。该优先填充过程可以改善大多数替换方案的性能，包括已经比LRU更好的已知方案。

6. 发明申请

US20130326147A1 SHORT CIRCUIT OF PROBES IN A CHAIN 有权
标题翻译：链中探针的短路
公开(公告)号：US20130326147A1
公开(公告)日：2013-12-05
申请号：US13996012
申请日：2011-12-29
申请人： Simon C. Steely, JR. , Samantika Subramaniam , William C. Hasenplaugh , Joel S. Emer
发明人： Simon C. Steely, JR. , Samantika Subramaniam , William C. Hasenplaugh , Joel S. Emer
IPC分类号： G06F12/08
CPC分类号： G06F12/084 , G06F12/082
摘要： A multi-core processing apparatus may provide a cache probe and data retrieval method. The method may comprise sending a memory request from a requester to a record keeping structure. The memory request may have a memory address of a memory that stores requested data. The method may further comprise determining that a local last accessor of the memory address may have a copy of the requested data up to date with the memory. The local last accessor may be within a local domain that the requester belongs to. The method may further comprise sending a cache probe to the local last accessor and retrieving a latest value of the requested data from the local last accessor to the requester.
摘要翻译：多核处理装置可以提供高速缓存探针和数据检索方法。该方法可以包括将请求者的存储器请求发送到记录保存结构。存储器请求可以具有存储请求的数据的存储器的存储器地址。该方法还可以包括确定存储器地址的本地最后访问器可以具有与存储器一起的所请求数据的副本。本地最后一个访问者可能在请求者所属的本地域内。该方法还可以包括向本地最后一个访问器发送高速缓存探测器，并且从本地最后一个访问器检索所请求的数据的最新值到请求者。

7. 发明授权

US10102124B2 High bandwidth full-block write commands 有权
公开(公告)号：US10102124B2
公开(公告)日：2018-10-16
申请号：US13993716
申请日：2011-12-28
申请人： Simon C. Steely, Jr. , William C. Hasenplaugh , Joel S. Emer , Samantika Subramaniam
发明人： Simon C. Steely, Jr. , William C. Hasenplaugh , Joel S. Emer , Samantika Subramaniam
IPC分类号： G06F13/00 , G06F12/0808 , G06F13/28
摘要： A micro-architecture may provide a hardware and software of a high bandwidth write command. The micro-architecture may invoke a method to perform the high bandwidth write command. The method may comprise sending a write request from a requester to a record keeping structure. The write request may have a memory address of a memory that stores requested data. The method may further determine copies of the requested data being present in a distributed cache system outside the memory, sending invalidation requests to elements holding copies of the requested data in the distributed cache system, sending a notification to the requester to inform presence of copies of the requested data and sending a write response message after a latest value of the requested data and all invalidation acknowledgements have been received.

8. 发明授权

US09418016B2 Method and apparatus for optimizing the usage of cache memories 有权
标题翻译：用于优化高速缓存存储器的使用的方法和装置
公开(公告)号：US09418016B2
公开(公告)日：2016-08-16
申请号：US12974907
申请日：2010-12-21
申请人： Simon C. Steely, Jr. , Joel S. Emer , William C. Hasenplaugh
发明人： Simon C. Steely, Jr. , Joel S. Emer , William C. Hasenplaugh
IPC分类号： G06F12/02 , G06F12/08
CPC分类号： G06F12/0891 , G06F12/0804 , G06F12/0815 , G06F2212/1028 , Y02D10/13
摘要： A method and apparatus to reduce unnecessary write backs of cached data to a main memory and to optimize the usage of a cache memory tag directory. In one embodiment of the invention, the power consumption of a processor can be saved by eliminating write backs of cache memory lines that has information that has reached its end-of-life. In one embodiment of the invention, when a processing unit is required to clear one or more cache memory lines, it uses a write-zero command to clear the one or more cache memory lines. The processing unit does not perform a write operation to move or pass data values of zero to the one or more cache memory lines. By doing so, it reduces the power consumption of the processing unit.
摘要翻译：一种减少对主存储器的缓存数据的不必要的回写并优化高速缓存存储器标签目录的使用的方法和装置。在本发明的一个实施例中，通过消除具有已经达到其使用寿命的信息的高速缓冲存储器线的写回，可以节省处理器的功耗。在本发明的一个实施例中，当需要处理单元来清除一个或多个高速缓存存储器线时，它使用写入零命令来清除一个或多个高速缓存存储器线。处理单元不执行写入操作以将数据值0移动或传递给一个或多个高速缓存存储器线。通过这样做，它降低了处理单元的功耗。

9. 发明申请

US20140052920A1 DOMAIN STATE 有权
标题翻译：域名
公开(公告)号：US20140052920A1
公开(公告)日：2014-02-20
申请号：US13995991
申请日：2011-12-29
申请人： Simon C. Steely, JR. , William C. Hasenplaugh , Joel S. Emer
发明人： Simon C. Steely, JR. , William C. Hasenplaugh , Joel S. Emer
IPC分类号： G06F12/08
CPC分类号： G06F12/0802 , G06F12/0811 , G06F12/0817 , G06F13/00
摘要： Method and apparatus to efficiently maintain cache coherency by reading/writing a domain state field associated with a tag entry within a cache tag directory. A value may be assigned to a domain state field of a tag entry in a cache tag directory. The cache tag directory may belong to a hierarchy of cache tag directories.Each tag entry may be associated with a cache line from a cache belonging to a first domain. The first domain may contain multiple caches. The value of the domain state field may indicate whether its associated cache line can be read or changed.
摘要翻译：通过读/写与缓存标签目录中的标签条目相关联的域状态字段来有效地维持高速缓存一致性的方法和装置。可以将值分配给缓存标签目录中的标签条目的域状态字段。缓存标签目录可能属于高速缓存标签目录的层次结构。每个标签条目可以与来自属于第一域的高速缓存行相关联。第一个域可能包含多个缓存。域状态字段的值可以指示其相关联的高速缓存行是否可以被读取或改变。

10. 发明申请

US20120079208A1 PROBE SPECULATIVE ADDRESS FILE 失效
标题翻译：探测器地址文件
公开(公告)号：US20120079208A1
公开(公告)日：2012-03-29
申请号：US12892476
申请日：2010-09-28
申请人： Simon C. Steely, JR. , William C. Hasenplaugh
发明人： Simon C. Steely, JR. , William C. Hasenplaugh
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0815 , G06F2212/507
摘要： An apparatus to resolve cache coherency is presented. In one embodiment, the apparatus includes a microprocessor comprising one or more processing cores. The apparatus also includes a probe speculative address file unit, coupled to a cache memory, comprising a plurality of entries. Each entry includes a timer and a tag associated with a memory line. The apparatus further includes control logic to determine whether to service an incoming probe based at least in part on a timer value.
摘要翻译：提出了一种解决高速缓存一致性的设备。在一个实施例中，该装置包括具有一个或多个处理核心的微处理器。该装置还包括耦合到高速缓冲存储器的探测推测地址文件单元，包括多个条目。每个条目包括定时器和与存储器线相关联的标签。该装置还包括至少部分地基于定时器值来确定是否对入站探测器进行服务的控制逻辑。

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