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1. 发明授权

US10705961B2 Scalably mechanism to implement an instruction that monitors for writes to an address 有权
公开(公告)号：US10705961B2
公开(公告)日：2020-07-07
申请号：US14040375
申请日：2013-09-27
申请人： Yen-Cheng Liu , Bahaa Fahim , Erik G. Hallnor , Jeffrey D. Chamberlain , Stephen R. Van Doren , Antonio Juan
发明人： Yen-Cheng Liu , Bahaa Fahim , Erik G. Hallnor , Jeffrey D. Chamberlain , Stephen R. Van Doren , Antonio Juan
IPC分类号： G06F12/08 , G06F12/084 , G06F12/0831 , G06F12/0846 , G06F12/0811 , G06F9/00
摘要： A processor includes a cache-side address monitor unit corresponding to a first cache portion of a distributed cache that has a total number of cache-side address monitor storage locations less than a total number of logical processors of the processor. Each cache-side address monitor storage location is to store an address to be monitored. A core-side address monitor unit corresponds to a first core and has a same number of core-side address monitor storage locations as a number of logical processors of the first core. Each core-side address monitor storage location is to store an address, and a monitor state for a different corresponding logical processor of the first core. A cache-side address monitor storage overflow unit corresponds to the first cache portion, and is to enforce an address monitor storage overflow policy when no unused cache-side address monitor storage location is available to store an address to be monitored.

2. 发明申请

US20150186275A1 Inclusive/Non Inclusive Tracking of Local Cache Lines To Avoid Near Memory Reads On Cache Line Memory Writes Into A Two Level System Memory 有权
标题翻译：包含/非包含性跟踪本地缓存线以避免缓存行内存上的近内存读取写入两级系统内存
公开(公告)号：US20150186275A1
公开(公告)日：2015-07-02
申请号：US14142045
申请日：2013-12-27
申请人： Adrian C. Moga , Vedaraman Geetha , Bahaa Fahim , Robert G. Blankenship , Yen-Cheng Liu , Jeffrey D. Chamberlain , Stephen R. Van Doren
发明人： Adrian C. Moga , Vedaraman Geetha , Bahaa Fahim , Robert G. Blankenship , Yen-Cheng Liu , Jeffrey D. Chamberlain , Stephen R. Van Doren
IPC分类号： G06F12/08
CPC分类号： G06F12/0811 , G06F12/0888
摘要： A processor is described that includes one or more processing cores. The processing core includes a memory controller to interface with a system memory having a near memory and a far memory. The processing core includes a plurality of caching levels above the memory controller. The processor includes logic circuitry to track state information of a cache line that is cached in one of the caching levels. The state information including a selected one of an inclusive state and a non inclusive state. The inclusive state indicates that a copy or version of the cache line exists in near memory. The non inclusive states indicates that a copy or version of the cache line does not exist in the near memory. The logic circuitry is to cause the memory controller to handle a write request that requests a direct write into the near memory without a read of the near memory beforehand if a system memory write request generated within the processor targets the cache line when the cache line is in the inclusive state.
摘要翻译：描述了包括一个或多个处理核心的处理器。处理核心包括与具有近存储器和远存储器的系统存储器接口的存储器控制器。处理核心包括存储器控制器上方的多个缓存级别。处理器包括用于跟踪高速缓存行的状态信息的逻辑电路，该高速缓存行被缓存在缓存级之一中。所述状态信息包括包含状态和不包含状态中的所选择的状态。包含状态表示在内存中存在高速缓存行的副本或版本。不包含状态表示高速缓存行的副本或版本不存在于近端存储器中。逻辑电路是使存储器控制器处理写入请求，如果在处理器内部产生的系统存储器写入请求在高速缓存线为在包容性状态。

3. 发明申请

US20170192921A1 MULTI-CORE COMMUNICATION ACCELERATION USING HARDWARE QUEUE DEVICE 审中-公开
公开(公告)号：US20170192921A1
公开(公告)日：2017-07-06
申请号：US14987676
申请日：2016-01-04
申请人： Ren Wang , Yipeng Wang , Andrew J. Herdrich , Jr-Shian Tsai , Tsung-Yuan C. Tai , Niall D. McDonnell , Hugh Wilkinson , Bradley A. Burres , Bruce Richardson , Namakkal N. Venkatesan , Debra Bernstein , Edwin Verplanke , Stephen R. Van Doren , An Yan , Andrew Cunningham , David Sonnier , Gage Eads , James T. Clee , Jamison D. Whitesell , Jerry Pirog , Jonathan Kenny , Joseph R. Hasting , Narender Vangati , Stephen Miller , Te K. Ma , William Burroughs
发明人： Ren Wang , Yipeng Wang , Andrew J. Herdrich , Jr-Shian Tsai , Tsung-Yuan C. Tai , Niall D. McDonnell , Hugh Wilkinson , Bradley A. Burres , Bruce Richardson , Namakkal N. Venkatesan , Debra Bernstein , Edwin Verplanke , Stephen R. Van Doren , An Yan , Andrew Cunningham , David Sonnier , Gage Eads , James T. Clee , Jamison D. Whitesell , Jerry Pirog , Jonathan Kenny , Joseph R. Hasting , Narender Vangati , Stephen Miller , Te K. Ma , William Burroughs
IPC分类号： G06F13/37 , G06F13/16 , G06F12/08
CPC分类号： G06F13/37 , G06F9/3004 , G06F9/46 , G06F12/04 , G06F12/0811 , G06F12/0868 , G06F13/1642 , G06F13/1673 , G06F2212/283 , G06F2212/6046
摘要： Apparatus and methods implementing a hardware queue management device for reducing inter-core data transfer overhead by offloading request management and data coherency tasks from the CPU cores. The apparatus include multi-core processors, a shared L3 or last-level cache (“LLC”), and a hardware queue management device to receive, store, and process inter-core data transfer requests. The hardware queue management device further comprises a resource management system to control the rate in which the cores may submit requests to reduce core stalls and dropped requests. Additionally, software instructions are introduced to optimize communication between the cores and the queue management device.

4. 发明申请

US20100332762A1 DIRECTORY CACHE ALLOCATION BASED ON SNOOP RESPONSE INFORMATION 审中-公开
标题翻译：基于SNOOP响应信息的目录高速缓存分配
公开(公告)号：US20100332762A1
公开(公告)日：2010-12-30
申请号：US12495722
申请日：2009-06-30
申请人： Adrian C. Moga , Malcolm H. Mandviwalla , Stephen R. Van Doren
发明人： Adrian C. Moga , Malcolm H. Mandviwalla , Stephen R. Van Doren
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/082
摘要： Methods and apparatus relating to directory cache allocation that is based on snoop response information are described. In one embodiment, an entry in a directory cache may be allocated for an address in response to a determination that another caching agent has a copy of the data corresponding to the address. Other embodiments are also disclosed.
摘要翻译：描述了基于窥探响应信息的与目录高速缓存分配有关的方法和装置。在一个实施例中，响应于确定另一高速缓存代理具有与该地址对应的数据的副本，可以为地址分配目录高速缓存中的条目。还公开了其他实施例。

5. 发明授权

US07203775B2 System and method for avoiding deadlock 有权
标题翻译：避免死锁的系统和方法
公开(公告)号：US07203775B2
公开(公告)日：2007-04-10
申请号：US10337833
申请日：2003-01-07
申请人： Stephen R. Van Doren , Gregory E. Tierney
发明人： Stephen R. Van Doren , Gregory E. Tierney
IPC分类号： G06F3/00
CPC分类号： G06F9/524
摘要： A system and method avoids deadlock, such as circular routing deadlock, in a computer system by providing a virtual buffer at main memory. The computer system has an interconnection network that couples a plurality of processors having access to main memory. The interconnection network includes one or more routing agents each having at least one buffer for storing packets that are to be forwarded. When the routing agent's buffer becomes full, thereby preventing it from accepting any additional packets, the routing agent transfers at least one packet into the virtual buffer. By transferring a packet out of the buffer, the routing agent frees up space allowing it to accept a new packet. If the newly accepted packet also results in the buffer becoming full, another packet is transferred into the virtual buffer. This process is repeated until the deadlock condition is resolved. Packets are then retrieved from the virtual buffer.
摘要翻译：系统和方法通过在主存储器中提供虚拟缓冲区来避免计算机系统中的死循环，例如循环路由死锁。计算机系统具有将具有访问主存储器的多个处理器耦合的互连网络。互连网络包括一个或多个路由代理，每个路由代理具有至少一个用于存储要转发的分组的缓冲器。当路由代理的缓冲区变满时，路由代理将至少一个数据包传输到虚拟缓冲区中。通过将数据包从缓冲区传送出去，路由代理释放了允许它接受新数据包的空间。如果新接受的分组也导致缓冲区变满，则另一分组被传送到虚拟缓冲器中。重复该过程，直到死锁状态得到解决。然后从虚拟缓冲区中检索数据包。

6. 发明授权

US06286090B1 Mechanism for selectively imposing interference order between page-table fetches and corresponding data fetches 失效
标题翻译：选择性地强制页表提取之间的干扰顺序和相应数据提取的机制
公开(公告)号：US06286090B1
公开(公告)日：2001-09-04
申请号：US09084621
申请日：1998-05-26
申请人： Simon C. Steely, Jr. , Madhumitra Sharma , Stephen R. Van Doren , Kourosh Gharachorloo
发明人： Simon C. Steely, Jr. , Madhumitra Sharma , Stephen R. Van Doren , Kourosh Gharachorloo
IPC分类号： G06F1200
CPC分类号： G06F12/1054 , G06F12/0813
摘要： A technique selectively imposes inter-reference ordering between memory reference operations issued by a processor of a multiprocessor system to addresses within a page pertaining to a page table entry (PTE) that is affected by a translation buffer (TB) miss flow routine. The TB miss flow is used to retrieve information contained in the PTE for mapping a virtual address to a physical address and, subsequently, to allow retrieval of data at the mapped physical address. The PTE that is retrieved in response to a memory reference (read) operation is not loaded into the TB until a commit-signal associated with that read operation is returned to the processor. Once the PTE and associated commit-signal are returned, the processor loads the PTE into the TB so that it can be used for a subsequent read operation directed to the data at the physical address.
摘要翻译：一种技术选择性地将由多处理器系统的处理器发出的存储器参考操作之间的参考间排序施加于与由翻译缓冲器（TB）错过流程程影响的页表项（PTE）相关的页面内的地址。 TB错误流被用于检索包含在PTE中的信息，用于将虚拟地址映射到物理地址，并且随后允许在映射的物理地址处检索数据。响应于存储器引用（读取）操作检索的PTE不会被加载到TB中，直到与该读取操作相关联的提交信号返回到处理器。一旦返回了PTE和相关联的提交信号，处理器将PTE加载到TB中，以便它可以用于针对物理地址的数据的后续读取操作。

7. 发明授权

US07856534B2 Transaction references for requests in a multi-processor network 失效
标题翻译：多处理器网络中的请求的事务引用
公开(公告)号：US07856534B2
公开(公告)日：2010-12-21
申请号：US10758352
申请日：2004-01-15
申请人： Stephen R. Van Doren , Simon C. Steely, Jr. , Gregory Edward Tierney
发明人： Stephen R. Van Doren , Simon C. Steely, Jr. , Gregory Edward Tierney
IPC分类号： G06F12/00
CPC分类号： G06F12/0828 , G06F12/0831
摘要： One disclosed embodiment may comprise a system that includes a home node that provides a transaction reference to a requester in response to a request from the requester. The requester provides an acknowledgement message to the home node in response to the transaction reference, the transaction reference enabling the requester to determine an order of requests at the home node relative to the request from the requester.
摘要翻译：一个公开的实施例可以包括系统，其包括家庭节点，其响应于来自请求者的请求向请求者提供事务参考。请求者响应于事务参考向家庭节点提供确认消息，事务参考使得请求者能够相对于来自请求者的请求确定家庭节点处的请求的顺序。

8. 发明授权

US07143245B2 System and method for read migratory optimization in a cache coherency protocol 失效
标题翻译：缓存一致性协议中读取迁移优化的系统和方法
公开(公告)号：US07143245B2
公开(公告)日：2006-11-28
申请号：US10761044
申请日：2004-01-20
申请人： Gregory Edward Tierney , Stephen R. Van Doren , Simon C. Steely, Jr.
发明人： Gregory Edward Tierney , Stephen R. Van Doren , Simon C. Steely, Jr.
IPC分类号： G06F12/00
CPC分类号： G06F12/0831 , G06F12/0813 , G06F12/0828 , G06F2212/2542
摘要： A system comprises a first node including data having an associated D-state and a second node operative to provide a source broadcast requesting the data. The first node is operative in response to the source broadcast to provide the data to the second node and transition the state associated with the data at the first node from the D-state to an O-state without concurrently updating memory. An S-state is associated with the data at the second node.
摘要翻译：系统包括包括具有相关D状态的数据的第一节点和用于提供请求数据的源广播的第二节点。第一节点响应于源广播而操作以向第二节点提供数据，并将与第一节点处的数据相关联的状态从D状态转换到O状态，而不同时更新存储器。 S状态与第二节点处的数据相关联。

9. 发明授权

US07000080B2 Channel-based late race resolution mechanism for a computer system 有权
标题翻译：基于通道的晚期种族解决机制的计算机系统
公开(公告)号：US07000080B2
公开(公告)日：2006-02-14
申请号：US10263836
申请日：2002-10-03
申请人： Stephen R. Van Doren , Gregory E. Tierney
发明人： Stephen R. Van Doren , Gregory E. Tierney
IPC分类号： G06F12/00
CPC分类号： G06F12/0828 , G06F12/0813 , G06F12/082
摘要： A channel-based mechanism resolves race conditions in a computer system between a first processor writing modified data back to memory and a second processor trying to obtain a copy of the modified data. In addition to a Q0 channel for carrying requests for data, a Q1 channel for carrying probes in response to Q0 requests, and a Q2 channel for carrying responses to Q0 requests, a new channel, the QWB channel, which has a higher priority than Q1 but lower than Q2, is also defined. When a forwarded Read command from the second processor results in a miss at the first processor's cache, because the requested memory block was written back to memory, a Loop command is issued to memory by the first processor on the QWB virtual channel. In response to the Loop command, memory sends the written back version of the memory block to the second processor.
摘要翻译：基于频道的机制解决计算机系统中的第一处理器将修改后的数据写回存储器和尝试获得修改的数据的副本的第二处理器之间的竞争条件。除了用于携带对数据的请求的Q 0信道之外，还具有用于响应于Q 0请求携带探针的Q 1信道和用于对Q 0请求进行响应的Q 2信道，具有优先于Q 1但低于Q 2的优先级也被定义。当来自第二处理器的转发的Read命令导致第一处理器的高速缓存中的未命中时，由于所请求的存储器块被写回存储器，所以QWB虚拟通道上的第一处理器向存储器发出一个循环命令。响应于循环命令，存储器将存储器块的写回版本发送到第二处理器。

10. 发明授权

US08090914B2 System and method for creating ordering points 有权
标题翻译：用于创建订购点的系统和方法
公开(公告)号：US08090914B2
公开(公告)日：2012-01-03
申请号：US10760652
申请日：2004-01-20
申请人： Gregory Edward Tierney , Stephen R. Van Doren , Simon C. Steely, Jr.
发明人： Gregory Edward Tierney , Stephen R. Van Doren , Simon C. Steely, Jr.
IPC分类号： G06F12/00
CPC分类号： G06F12/0831 , G06F12/0828 , G06F2212/2542
摘要： A system comprises a first node operative to provide a source broadcast requesting data. The first node associates an F-state with a copy of the data in response to receiving the copy of the data from memory and receiving non-data responses from other nodes in the system. The non-data responses include an indication that at least a second node includes a shared copy of the data. The F-state enabling the first node to serve as an ordering point in the system capable of responding to requests from other nodes in the system with a shared copy of the data.
摘要翻译：系统包括用于提供源广播请求数据的第一节点。响应于从存储器接收数据的副本并从系统中的其他节点接收非数据响应，第一节点将F状态与数据的副本相关联。非数据响应包括至少第二节点包括数据的共享副本的指示。 F状态使得第一节点能够用作系统中能够利用数据的共享副本响应来自系统中其他节点的请求的系统中的订购点。

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