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1. 发明授权

US09542980B1 Sense amplifier with mini-gap architecture and parallel interconnect 有权
标题翻译：具有微型间隙架构和并行互连的感应放大器
公开(公告)号：US09542980B1
公开(公告)日：2017-01-10
申请号：US15083303
申请日：2016-03-29
申请人： NANYA TECHNOLOGY CORP.
发明人： Adam Saleh El-Mansouri , Adrian Jay Drexler , Ryan Martin Hofstetter
IPC分类号： G11C7/10 , G11C7/06 , G11C7/22
CPC分类号： G11C7/06 , G11C7/18
摘要： A memory array structure includes: a plurality of array sections and a plurality of mini-gaps, wherein each mini-gap is disposed between two array sections of the plurality of array sections. Each mini-gap includes: a local write device, for providing a data signal in response to a write enable signal and a write data signal, the data signal for performing a write operation on a memory cell of an array section; and a local sensor, for outputting a data signal in response to an activation command and a read enable signal. The memory array further includes a control logic for providing the write enable and read enable signals, and at least one main sense amplifier, for providing the write data signal to the local write device, receiving the data signal from the local sensor, and amplifying the received data signal for providing a read data signal to output data lines.
摘要翻译：存储器阵列结构包括：多个阵列部分和多个微型间隙，其中每个微小间隙设置在多个阵列部分的两个阵列部分之间。每个小间隙包括：本地写装置，用于响应于写使能信号和写数据信号提供数据信号，用于对阵列部分的存储单元执行写操作的数据信号; 以及本地传感器，用于响应于激活命令和读使能信号而输出数据信号。存储器阵列还包括用于提供写入使能和读取使能信号的控制逻辑，以及至少一个主读出放大器，用于将写入数据信号提供给本地写入器件，从本地传感器接收数据信号，以及放大接收的数据信号用于提供读取数据信号以输出数据线。

2. 发明授权

US09343547B2 Method for fabricating a recessed channel access transistor device 有权
标题翻译：凹陷通道存取晶体管器件的制造方法
公开(公告)号：US09343547B2
公开(公告)日：2016-05-17
申请号：US14616750
申请日：2015-02-09
申请人： NANYA TECHNOLOGY CORP.
发明人： Tieh-Chiang Wu , Wei-Ming Liao
IPC分类号： H01L29/66 , H01L29/76 , H01L21/265 , H01L21/28 , H01L27/108 , H01L29/423
CPC分类号： H01L29/66666 , H01L21/265 , H01L21/28008 , H01L27/10823 , H01L27/10844 , H01L27/10855 , H01L27/10876 , H01L29/4236 , H01L29/66621 , H01L29/66659 , H01L29/76
摘要： A trench extends from a main surface of a semiconductor substrate to a predetermined depth. A gate oxide layer is formed in the trench. A buried gate electrode is formed at a lower portion of the trench. The buried gate electrode is capped with a dielectric layer. A pad layer and hard mask layer are formed on the semiconductor substrate. A recess through the pad layer and hard mask layer and into the semiconductor substrate is formed on one side of the trench. A portion of the dielectric layer is revealed within the recess. The hard mask layer is then removed. An ion implantation process is performed to implant dopants on both sides of the trench, thereby forming a source doping region and a drain doping region. The source doping region has a junction depth that is deeper than that of the drain doping region.
摘要翻译：沟槽从半导体衬底的主表面延伸到预定深度。在沟槽中形成栅极氧化层。掩埋栅电极形成在沟槽的下部。掩埋栅极电极被覆盖有介电层。衬底层和硬掩模层形成在半导体衬底上。通过焊盘层和硬掩模层并进入半导体衬底的凹陷形成在沟槽的一侧。介电层的一部分露出在凹槽内。然后去除硬掩模层。执行离子注入工艺以在沟槽的两侧上注入掺杂剂，由此形成源极掺杂区域和漏极掺杂区域。源极掺杂区域具有比漏极掺杂区域深的结深度。

3. 发明授权

US09287221B2 Method for forming crack stop structure 有权
标题翻译：破裂结构形成方法
公开(公告)号：US09287221B2
公开(公告)日：2016-03-15
申请号：US14591010
申请日：2015-01-07
申请人： NANYA TECHNOLOGY CORP.
发明人： Tse-Yao Huang , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L23/00 , H01L23/31 , H01L21/78 , H01L21/311 , H01L21/762 , H01L21/56
CPC分类号： H01L23/562 , H01L21/311 , H01L21/561 , H01L21/76224 , H01L21/78 , H01L23/3178 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure includes a matrix, an integrated circuit and a scribe line. The matrix includes a scribe line region and a circuit region. The integrated circuit is disposed within the circuit region. The scribe line is disposed within the scribe line region and includes a crack stop trench which is disposed in the matrix and adjacent to the circuit region. The crack stop trench is parallel with one side of the circuit region and filled with a composite material in a form of a grid to form a crack stop structure.
摘要翻译：半导体结构包括矩阵，集成电路和划线。矩阵包括划线区域和电路区域。集成电路设置在电路区域内。划痕线设置在划线区域内并且包括设置在矩阵中并且邻近电路区域的裂缝停止沟槽。裂缝停止沟槽与电路区域的一侧平行，并填充有格栅形式的复合材料以形成裂纹停止结构。

4. 发明授权

US09230966B2 Capacitor and method of manufacturing the same 有权
标题翻译：电容器及其制造方法
公开(公告)号：US09230966B2
公开(公告)日：2016-01-05
申请号：US14249340
申请日：2014-04-09
申请人： NANYA TECHNOLOGY CORP.
发明人： Sanjeev Sapra , Brett W. Busch , Jian Li , Chad Patrick Blessing , Greg Allen Funston
IPC分类号： H01L21/00 , H01L27/108 , H01L49/02 , H01L21/02
CPC分类号： H01L27/10805 , H01L21/02046 , H01L21/02052 , H01L21/32134 , H01L21/32139 , H01L27/1085 , H01L27/10861 , H01L28/40 , H01L28/75 , H01L28/90
摘要： A capacitor includes a substrate, a multilayer over the substrate, a plurality of container-shaped storage node structures on the semiconductor substrate and surrounded by the multilayer, the storage node structure has a sidewall extending upwardly from the base to the top, where the sidewall includes an upper segment and a lower segment thinner than the upper segment, a capacitor dielectric material along a surface of each storage node structure, and a capacitor electrode material over the capacitor dielectric material.
摘要翻译：电容器包括衬底，衬底上的多层，半导体衬底上的多个容器形存储节点结构，并被多层包围，存储节点结构具有从底部向上延伸到顶部的侧壁，其中侧壁包括比上段更薄的上部段和下部段，沿着每个存储节点结构的表面的电容器电介质材料，以及电容器电介质材料上的电容器电极材料。

5. 发明授权

US09230613B2 Power up detecting system 有权
标题翻译：上电检测系统
公开(公告)号：US09230613B2
公开(公告)日：2016-01-05
申请号：US13448323
申请日：2012-04-16
申请人： Wayne A. Batt
发明人： Wayne A. Batt
IPC分类号： G01R21/06 , G01R31/02 , G11C13/00 , G11C5/14 , G11C29/12
CPC分类号： G01R31/02 , G01R19/165 , G11C5/143 , G11C5/148 , G11C29/12005
摘要： A power up detecting system for generating one of a first power up detecting signal and a second power up detecting signal as the final power up detecting signal, according to power provided by a power supplier. The power up detecting system comprises: a power up detecting module, controlled by a control signal to generate the first power up detecting signal in a first mode and to generate the second power up detecting signal in a second mode, wherein a voltage level of the first power up detecting signal is transited when the power reaches a first predetermined voltage value, and the voltage level of the second power up detecting signal is transited when the power reaches a second predetermined voltage value; where the first predetermined voltage value is higher than the second predetermined voltage value.
摘要翻译：一种上电检测系统，用于根据电源提供的电力产生第一上电检测信号和第二上电检测信号中的一个作为最终上电检测信号。上电检测系统包括：上电检测模块，由控制信号控制，以在第一模式中产生第一上电检测信号，并在第二模式中产生第二上电检测信号，其中，当功率达到第一预定电压值时，第一上电检测信号被转换，并且当电力达到第二预定电压值时第二上电检测信号的电压电平被转换; 其中第一预定电压值高于第二预定电压值。

6. 发明申请

US20150294971A1 CAPACITOR AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：电容器及其制造方法
公开(公告)号：US20150294971A1
公开(公告)日：2015-10-15
申请号：US14249340
申请日：2014-04-09
申请人： NANYA TECHNOLOGY CORP.
发明人： Sanjeev Sapra , Brett W. Busch , Jian Li , Chad Patrick Blessing , Greg Allen Funston
IPC分类号： H01L27/108 , H01L21/02 , H01L49/02
CPC分类号： H01L27/10805 , H01L21/02046 , H01L21/02052 , H01L21/32134 , H01L21/32139 , H01L27/1085 , H01L27/10861 , H01L28/40 , H01L28/75 , H01L28/90
摘要： A capacitor includes a substrate, a multilayer over the substrate, a plurality of container-shaped storage node structures on the semiconductor substrate and surrounded by the multilayer, the storage node structure has a sidewall extending upwardly from the base to the top, where the sidewall includes an upper segment and a lower segment thinner than the upper segment, a capacitor dielectric material along a surface of each storage node structure, and a capacitor electrode material over the capacitor dielectric material.
摘要翻译：电容器包括衬底，衬底上的多层，半导体衬底上的多个容器形存储节点结构，并被多层包围，存储节点结构具有从底部向上延伸到顶部的侧壁，其中侧壁包括比上段更薄的上部段和下部段，沿着每个存储节点结构的表面的电容器电介质材料，以及电容器电介质材料上的电容器电极材料。

7. 发明申请

US20150206575A1 COUNTER BASED DESIGN FOR TEMPERATURE CONTROLLED REFRESH 有权
标题翻译：基于计数器的温度控制刷新设计
公开(公告)号：US20150206575A1
公开(公告)日：2015-07-23
申请号：US14161655
申请日：2014-01-22
申请人： NANYA TECHNOLOGY CORP.
发明人： Donald Martin Morgan
IPC分类号： G11C11/406
CPC分类号： G11C11/40626 , G11C11/40611
摘要： A DRAM includes: a temperature sensor for monitoring a temperature operating condition of the DRAM; and a binary counter coupled to the temperature sensor, for receiving external commands to perform a refresh operation, and incrementing a count upon each received external command, wherein the refresh operation will be selectively skipped according to a value of the binary counter. The binary counter is activated to a first mode when the temperature sensor determines the temperature operating condition of the DRAM goes below a first threshold and activated to a second mode when the temperature sensor determines the temperature operating condition of the DRAM goes below a second threshold lower than the first threshold.
摘要翻译： DRAM包括：用于监视DRAM的温度操作状态的温度传感器; 以及耦合到所述温度传感器的二进制计数器，用于接收执行刷新操作的外部命令，以及在每个所接收的外部命令时递增计数，其中根据二进制计数器的值选择性地跳过刷新操作。当温度传感器确定DRAM的温度操作条件低于第一阈值时，二进制计数器被激活到第一模式，并且当温度传感器确定DRAM的温度操作条件低于第二阈值时激活到第二模式比第一个门槛。

8. 发明申请

US20150123280A1 SILICON BURIED DIGIT LINE ACCESS DEVICE AND METHOD OF FORMING THE SAME 有权
标题翻译：硅掩模数字线路访问装置及其形成方法
公开(公告)号：US20150123280A1
公开(公告)日：2015-05-07
申请号：US14069396
申请日：2013-11-01
申请人： NANYA TECHNOLOGY CORP.
发明人： Shyam Surthi , Lars Heineck
IPC分类号： H01L27/108 , H01L23/535
CPC分类号： H01L27/10891 , H01L23/5222 , H01L27/10885 , H01L2924/0002 , H01L2924/00
摘要： An access device includes a plurality of first digit lines (DL) trenches extending along a first direction, buried digit lines between each DL trench, second and third trenches separating the digit lines, a filling material filling the digit line trenches comprising airgaps in each second trench, a plurality of word line (WL) trenches extending along a second direction, metal word lines deposited on the walls of the word line trenches, a filling material filling the word line trenches.
摘要翻译：访问装置包括沿着第一方向延伸的多个第一数字线（DL）沟槽，每个DL沟槽之间的掩埋数字线，分隔数字线的第二和第三沟槽，填充数字线沟槽的填充材料，其包括在每一秒的气隙沟槽，沿着第二方向延伸的多个字线（WL）沟槽，沉积在字线沟槽的壁上的金属字线，填充字线沟槽的填充材料。

9. 发明授权

US09012330B2 Method for semiconductor cross pitch doubled patterning process 有权
标题翻译：半导体交叉螺距双重图案化方法
公开(公告)号：US09012330B2
公开(公告)日：2015-04-21
申请号：US13974032
申请日：2013-08-22
申请人： Nanya Technology Corp.
发明人： Vinay Nair , Lars Heineck
IPC分类号： H01L21/308
CPC分类号： H01L21/3088 , H01L21/0337
摘要： The present invention provides a method of cross double pitch patterning for forming a contact printing mask. First, a first, a second and a third layer a successively deposited; a photoresist is deposited on the third layer, and then trimmed into a first pre-pattern, on which an oxide layer is deposited. The oxide layer is etched into spacers forming a first pattern that is then etched into the third layer. A second cross pattern is formed the same way on the third layer. Finally the first and second layers are etched with selectivity both patterns.
摘要翻译：本发明提供一种用于形成接触印刷掩模的交叉双间距图案化方法。首先，连续沉积第一层，第二层和第三层; 光致抗蚀剂沉积在第三层上，然后被修整成第一预图案，其上沉积有氧化物层。将氧化物层蚀刻成形成第一图案的间隔物，然后将其蚀刻到第三层中。在第三层上以相同的方式形成第二十字图案。最后，选择性地蚀刻第一层和第二层两种图案。

10. 发明授权

US08911558B2 Post-tungsten CMP cleaning solution and method of using the same 有权
标题翻译：钨后CMP清洗液及其使用方法
公开(公告)号：US08911558B2
公开(公告)日：2014-12-16
申请号：US13069408
申请日：2011-03-23
申请人： Hongqi Li , Anurag Jindal , Jin Lu
发明人： Hongqi Li , Anurag Jindal , Jin Lu
IPC分类号： B08B3/12 , B08B6/00 , B08B7/00 , B08B7/02 , C25C1/00 , C25F3/30 , C25F5/00 , C11D11/00 , C11D7/26 , H01L21/02
CPC分类号： C11D11/0047 , C11D7/265 , H01L21/02074
摘要： A post-W CMP cleaning solution consists of carboxylic acid and deionized water. The carboxylic acid may be selected from the group consisting of (1) monocarboxylic acids; (2) dicarboxylic acids; (3) tricarboxylic acids; (4) polycarboxylic acids; (5) hydroxycarboxylic acids; (6) salts of the above-described carboxylic acids; and (7) any combination thereof. The post-W CMP cleaning solution can work well without adding any other chemical additives such as surfactants, corrosion inhibitors, pH adjusting agents or chelating agents.
摘要翻译： CMP后清洁溶液由羧酸和去离子水组成。羧酸可以选自（1）一元羧酸; （2）二羧酸; （3）三羧酸; （4）多元羧酸; （5）羟基羧酸; （6）上述羧酸的盐; 和（7）其任何组合。后CMP扫描溶液可以很好的工作，而不需要添加任何其他化学添加剂，如表面活性剂，腐蚀抑制剂，pH调节剂或螯合剂。

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