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1. 再颁专利

USRE49803E1 Method of manufacturing semiconductor device, and semiconductor device 有权
公开(公告)号：USRE49803E1
公开(公告)日：2024-01-16
申请号：US16184766
申请日：2018-11-08
申请人： Sony Corporation
发明人： Yuki Miyanami
IPC分类号： H01L21/337 , H01L21/8234 , H01L21/8238 , H01L29/78 , H01L29/165 , H01L29/66
CPC分类号： H01L29/7848 , H01L29/165 , H01L29/66628 , H01L29/66636 , H01L29/7834
摘要： A method of manufacturing a semiconductor device includes: the first step of forming a gate electrode over a silicon substrate, with a gate insulating film; and the second step of digging down a surface layer of the silicon substrate by etching conducted with the gate electrode as a mask. The method of manufacturing the semiconductor device further includes the third step of epitaxially growing, on the surface of the dug-down portion of the silicon substrate, a mixed crystal layer including silicon and atoms different in lattice constant from silicon so that the mixed crystal layer contains an impurity with such a concentration gradient that the impurity concentration increases along the direction from the silicon substrate side toward the surface of the mixed crystal layer.

2. 发明授权

US10181512B2 JFET and method for fabricating the same 有权
公开(公告)号：US10181512B2
公开(公告)日：2019-01-15
申请号：US15866583
申请日：2018-01-10
申请人： Vanguard International Semiconductor Corporation
发明人： Wen-Hsin Lin , Shin-Cheng Lin , Cheng-Tsung Wu , Yu-Hao Ho
IPC分类号： H01L21/337 , H01L29/10 , H01L29/808 , H01L29/66 , H01L21/265 , H01L21/324 , H01L21/225
摘要： A junction field effect transistor includes a substrate and a gate region having a first conductive type in the substrate. Source/drain regions of a second conductive type opposite to the first conductive type are disposed in the substrate on opposite sides of the gate region. A pair of high-voltage well regions of the second conductive type are disposed beneath the source/drain regions. A channel region is provided beneath the gate region and between the pair of high-voltage well regions. The channel region is of the second conductive type and has a dopant concentration lower than that of the pair of high-voltage well regions.

3. 发明授权

US10157845B2 Method for fabricating a local interconnect in a semiconductor device 有权
公开(公告)号：US10157845B2
公开(公告)日：2018-12-18
申请号：US15851640
申请日：2017-12-21
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
发明人： Jui-Yao Lai , Sai-Hooi Yeong , Ying-Yan Chen
IPC分类号： H01L29/80 , H01L29/76 , H01L21/00 , H01L21/337 , H01L23/535 , H01L21/8238 , H01L27/092 , H01L29/08 , H01L29/16 , H01L29/161 , H01L29/165 , H01L29/24 , H01L29/66 , H01L29/78 , H01L21/768
摘要： A semiconductor device includes a first transistor having a first gate, a first source and a first drain, a second transistor having a second gate, a second source and a second drain, an isolation region separating the first transistor from the second transistor, and a local interconnect connecting at least one of the first source and the first drain to at least the second source and the second drain. The local interconnect is in contact with a surface of the at least one of the first source and the first drain, a surface of the at least the second source and the second drain and a surface of a part of the isolation region.

4. 发明授权

US10121907B2 Planar triple-implanted JFET 有权
公开(公告)号：US10121907B2
公开(公告)日：2018-11-06
申请号：US15267177
申请日：2016-09-16
申请人： United Silicon Carbide, Inc.
发明人： Anup Bhalla , Zhongda Li
IPC分类号： H01L21/337 , H01L29/808 , H01L21/266 , H01L21/265 , H01L29/10 , H01L29/16 , H01L29/66 , H01L21/04 , H01L29/08 , H01L29/423 , H01L29/06
摘要： A JFET is formed with vertical and horizontal elements made from a high band-gap semiconductor material such as silicon carbide via triple implantation of a substrate comprising an upper drift region and a lower drain region, the triple implantation forming a lower gate, a horizontal channel, and an upper gate, in a portion of the drift region. A source region may be formed through a portion of the top gate, and the top and bottom gates are connected. A vertical channel region is formed adjacent to the planar JFET region and extending through the top gate, horizontal channel, and bottom gate to connect to the drift, such that the lower gate modulates the vertical channel as well as the horizontal channel, and current from the sources flows first through the horizontal channel and then through the vertical channel into the drift.

5. 发明授权

US10026814B2 P-doping of group-III-nitride buffer layer structure on a heterosubstrate 有权
公开(公告)号：US10026814B2
公开(公告)日：2018-07-17
申请号：US15700289
申请日：2017-09-11
申请人： AZURSPACE Solar Power GmbH
发明人： Stephan Lutgen , Saad Murad , Ashay Chitnis
IPC分类号： H01L29/12 , H01L31/072 , H01L23/48 , H01L21/338 , H01L21/337 , H01L21/3205 , H01L29/205 , H01L29/15 , H01L21/02 , H01L29/872 , H01L29/778 , H01L29/36 , H01L29/10 , H01L29/207 , H01L29/20 , H01L33/00
摘要： An epitaxial group-ill-nitride buffer-layer structure is provided on a heterosubstrate, wherein the buffer-layer structure has at least one stress-management layer sequence including an interlayer structure arranged between and adjacent to a first and a second group-ill-nitride layer, wherein the interlayer structure comprises a group-ill-nitride interlayer material having a larger band gap than the materials of the first and second group-ill-nitride layers, and wherein a p-type-dopant-concentration profile drops, starting from at least 1×1018 cm−3, by at least a factor of two in transition from the interlayer structure to the first and second group-ill-nitride layers.

6. 发明授权

US09960155B2 Laterally diffused metal oxide semiconductor device integrated with vertical field effect transistor 有权
公开(公告)号：US09960155B2
公开(公告)日：2018-05-01
申请号：US15637261
申请日：2017-06-29
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Brent A. Anderson , Alain Loiseau
IPC分类号： H01L29/74 , H01L29/80 , H01L29/76 , H01L21/00 , H01L21/337 , H01L21/8238 , H01L27/06 , H01L29/78 , H01L21/8234 , H01L29/10
CPC分类号： H01L27/0617 , H01L21/823412 , H01L21/823418 , H01L21/823462 , H01L21/823468 , H01L21/823475 , H01L21/823487 , H01L21/823821 , H01L21/823871 , H01L21/823878 , H01L21/823885 , H01L27/088 , H01L27/0886 , H01L29/0649 , H01L29/1095 , H01L29/66666 , H01L29/7816 , H01L29/7827 , H01L29/785 , H01L29/7851
摘要： An electrical device that in some embodiments includes a substrate including a lateral device region and a vertical device region. A lateral diffusion metal oxide semiconductor (LDMOS) device may be present in the lateral device region, wherein a drift region of the LDMOS device has a length that is parallel to an upper surface of the substrate in which the LDMOS device is formed. A vertical field effect transistor (VFET) device may be present in the vertical device region, wherein a vertical channel of the VFET has a length that is perpendicular to said upper surface of the substrate, the VFET including a gate structure that is positioned around the vertical channel.

7. 发明授权

US09728466B1 Vertical field effect transistors with metallic source/drain regions 有权
公开(公告)号：US09728466B1
公开(公告)日：2017-08-08
申请号：US15140763
申请日：2016-04-28
申请人： International Business Machines Corporation
发明人： Hari V. Mallela , Robert R. Robison , Reinaldo Vega , Rajasekhar Venigalla
IPC分类号： H01L21/00 , H01L21/338 , H01L21/337 , H01L21/8238 , H01L21/336 , H01L29/80 , H01L29/94 , H01L21/285 , H01L27/092 , H01L29/06 , H01L29/161 , H01L29/16 , H01L29/165 , H01L29/786 , H01L29/423
CPC分类号： H01L29/41741 , H01L21/28518 , H01L21/823814 , H01L21/823828 , H01L21/823871 , H01L21/823885 , H01L23/485 , H01L27/092 , H01L29/0676 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/41791 , H01L29/42392 , H01L29/66666 , H01L29/7827 , H01L29/785 , H01L29/78618 , H01L29/78642 , H01L29/78687 , H01L29/78696
摘要： Semiconductor devices having vertical FET (field effect transistor) devices with metallic source/drain regions are provided, as well as methods for fabricating such vertical FET devices. For example, a semiconductor device includes a first source/drain region formed on a semiconductor substrate, a vertical semiconductor fin formed on the first source/drain region, a second source/drain region formed on an upper surface of the vertical semiconductor fin, a gate structure formed on a sidewall surface of the vertical semiconductor fin, and an insulating material that encapsulates the vertical semiconductor fin and the gate structure. The first source/drain region comprises a metallic layer and at least a first epitaxial semiconductor layer. For example, the metallic layer of the first source/drain region comprises a metal-semiconductor alloy such as silicide.

8. 发明授权

US09601383B1 FinFET fabrication by forming isolation trenches prior to fin formation 有权
公开(公告)号：US09601383B1
公开(公告)日：2017-03-21
申请号：US14941885
申请日：2015-11-16
申请人： GLOBALFOUNDRIES Inc.
发明人： Murat Kerem Akarvardar
IPC分类号： H01L21/337 , H01L21/8234 , H01L21/762 , H01L21/308 , H01L21/3105 , H01L21/02 , H01L27/088 , H01L29/161 , H01L29/06
CPC分类号： H01L21/823431 , H01L21/308 , H01L21/31051 , H01L21/76224 , H01L21/823481 , H01L27/0886 , H01L29/0649 , H01L29/161 , H01L29/785
摘要： A semiconductor structure for a FinFET in fabrication is provided, the structure including a bulk semiconductor substrate initially with a hard mask over the substrate. Isolation trenches between regions of the structure where the fins will be are formed prior to the fins, and filled with selectively removable sacrificial isolation material. Remains of the hard mask are removed and another hard mask formed over the structure with filled isolation trenches. Fins are then formed throughout the structure, including the regions of sacrificial isolation material, which is thereafter selectively removed.

9. 发明授权

US09472418B2 Method for forming a split-gate device 有权
标题翻译：形成分闸装置的方法
公开(公告)号：US09472418B2
公开(公告)日：2016-10-18
申请号：US14228672
申请日：2014-03-28
申请人： Mark D. Hall , Mehul D. Shroff
发明人： Mark D. Hall , Mehul D. Shroff
IPC分类号： H01L21/337 , H01L21/3213 , H01L29/66 , H01L29/423 , H01L29/788 , H01L27/115
CPC分类号： H01L21/32133 , H01L27/11534 , H01L29/42328 , H01L29/42332 , H01L29/66545 , H01L29/66825 , H01L29/7881
摘要： A method of forming a semiconductor device in an NVM region and in a logic region uses a semiconductor substrate and includes forming a gate region fill material over the NVM region and the logic region. The gate region fill material is patterned over the NVM region to leave a first patterned gate region fill material over the NVM region. An interlayer dielectric is formed around the first patterned gate region fill material. A first portion of the first patterned gate region fill material is removed to form a first opening and leaving a second portion of the first patterned gate region fill material. The first opening is laterally adjacent to the second portion. The first opening is filled with a charge storage layer and a conductive material that includes metal overlying the charge storage layer.
摘要翻译：在NVM区域和逻辑区域中形成半导体器件的方法使用半导体衬底，并且包括在NVM区域和逻辑区域上形成栅极区域填充材料。栅极区域填充材料在NVM区域上被图案化以在NVM区域上留下第一图案化栅极区域填充材料。在第一图案化栅区填充材料周围形成层间电介质。去除第一图案化栅区填充材料的第一部分以形成第一开口并留下第一图案化栅区填充材料的第二部分。第一开口横向邻近第二部分。第一开口填充有电荷存储层和包含覆盖电荷存储层的金属的导电材料。

10. 发明授权

US09396928B2 Method for fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US09396928B2
公开(公告)日：2016-07-19
申请号：US14989462
申请日：2016-01-06
申请人： SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
发明人： Tsutomu Komatani
IPC分类号： H01L21/337 , H01L21/02 , H01L29/66
CPC分类号： H01L21/0217 , H01L21/02164 , H01L21/02178 , H01L21/0228 , H01L29/42316 , H01L29/475 , H01L29/66462 , H01L29/66924 , H01L29/7787
摘要： A method for fabricating a semiconductor device includes: forming a first film on a nitride semiconductor layer so as to contact the nitride semiconductor layer and have a thickness equal to or larger than 1 nm and equal to or smaller than 5 nm, the first film being made of silicon nitride having a composition ratio of silicon to nitrogen larger than 0.75, silicon oxide having a composition ratio of silicon to oxygen larger than 0.5, or aluminum; and forming a source electrode, a gate electrode and a drain electrode on the nitride semiconductor layer.
摘要翻译：一种制造半导体器件的方法包括：在氮化物半导体层上形成第一膜以接触氮化物半导体层，其厚度等于或大于1nm且等于或小于5nm，第一膜为由硅与氮的组成比大于0.75的氮化硅制成，硅与氧的组成比大于0.5的氧化硅或铝; 以及在所述氮化物半导体层上形成源电极，栅电极和漏电极。

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