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91. 发明申请

US20090257537A1 DATA RECOVERY CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS THAT MINIMIZES JITTER DURING DATA TRANSMISSION 审中-公开
标题翻译：在数据传输期间最小化抖动的半导体存储器的数据恢复电路
公开(公告)号：US20090257537A1
公开(公告)日：2009-10-15
申请号：US12344736
申请日：2008-12-29
申请人： Yong-Ju KIM , Hae-Rang CHOI , Oh-Kyong KWON , Jun-Yong SONG , Min-Seok SHIN
发明人： Yong-Ju KIM , Hae-Rang CHOI , Oh-Kyong KWON , Jun-Yong SONG , Min-Seok SHIN
IPC分类号： H04L7/00
CPC分类号： H04L7/0338 , G11C7/1012 , G11C7/1051 , G11C7/1066 , G11C7/222 , H03K5/135
摘要： A data recovery circuit that minimizes jitter during data transmission is presented. The data recovery circuit includes a data dividing unit, a data sampling unit, a data selecting unit, and a data recovery unit. The data dividing unit is for dividing external data to generate multiple-division data. The data sampling unit is for sampling the multiple-division data at a first time and a second time to generate sampling data. The data selecting unit is for selecting one of the data sampled at the first time or the second time from the sampling data in accordance to whether the sampling data is transited to output the selected one as selection data. The data recovery unit is for recovering the selection data to internal data in the same logic level as the logic level of the external data.
摘要翻译：呈现数据传输中抖动最小化的数据恢复电路。数据恢复电路包括数据分割单元，数据采样单元，数据选择单元和数据恢复单元。数据分割单元用于分割外部数据以产生多分割数据。数据采样单元用于在第一时间和第二时间对多分割数据进行采样以产生采样数据。数据选择单元用于根据抽样数据是否被转换以输出所选择的数据作为选择数据，用于从采样数据中选择在第一时间或第二时间采样的数据中的一个。数据恢复单元用于将选择数据恢复到与外部数据的逻辑电平相同的逻辑电平的内部数据。

92. 发明申请

US20090231007A1 SEMICONDUCTOR INTEGRATED CIRCUIT CAPABLE OF OVERCOMING CLOCK SIGNAL JITTER 失效
标题翻译：半导体集成电路可以覆盖时钟信号抖动
公开(公告)号：US20090231007A1
公开(公告)日：2009-09-17
申请号：US12330287
申请日：2008-12-08
申请人： Ic Su Oh , Yong Ju Kim , Sung Woo Han , Hee Woong Song , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee , Jae Min Jang , Chang Kun Park
发明人： Ic Su Oh , Yong Ju Kim , Sung Woo Han , Hee Woong Song , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee , Jae Min Jang , Chang Kun Park
IPC分类号： H03K7/02
CPC分类号： H03K5/133 , H03K5/003 , H03K5/156
摘要： A semiconductor integrated circuit includes a voltage supplying unit that supplies a first regulated voltage and a second regulated voltage by using a first reference voltage and a second reference voltage, respectively, and a clock buffer unit that supplies an output clock clocking within a range of the first regulated voltage and the second regulated voltage.
摘要翻译：一种半导体集成电路包括分别通过使用第一参考电压和第二参考电压来提供第一调节电压和第二调节电压的电压提供单元，以及时钟缓冲器单元，其提供在第一调节电压和第二调节电压。

93. 发明申请

US20090206900A1 DUTY CYCLE CORRECTION CIRCUIT AND METHOD FOR CORRECTING DUTY CYCLE 审中-公开
标题翻译：占空比校正电路和校正周期的方法
公开(公告)号：US20090206900A1
公开(公告)日：2009-08-20
申请号：US12168560
申请日：2008-07-07
申请人： Hee Woong Song , Yong Ju Kim , Sung Woo Han , Jae Min Jang , Hyung Soo Kim , Ji Wang Lee , Chang Kun Park , Ic Su Oh , Hae Rang Choi , Tae Jin Hwang
发明人： Hee Woong Song , Yong Ju Kim , Sung Woo Han , Jae Min Jang , Hyung Soo Kim , Ji Wang Lee , Chang Kun Park , Ic Su Oh , Hae Rang Choi , Tae Jin Hwang
IPC分类号： H03K3/017
CPC分类号： G11C8/04 , H03K5/1565 , H03K2217/0018
摘要： A duty cycle correction circuit capable of reducing current consumption and that includes a back-bias voltage supply circuit for supplying back-bias voltages, wherein a duty cycle of an input clock is reflected on the back-bias voltages; and a buffer for adjusting the duty cycle of the input clock and configured to receive the back-bias voltages.
摘要翻译：一种能够降低电流消耗的占空比校正电路，包括用于提供反向偏置电压的反向偏置电压供给电路，其中输入时钟的占空比反映在反向偏置电压上; 以及用于调整输入时钟的占空比并被配置为接收反偏压的缓冲器。

94. 发明申请

US20090128214A1 DATA RECEIVER OF SEMICONDUCTOR INTEGRATED CIRCUIT 审中-公开
标题翻译：半导体集成电路的数据接收器
公开(公告)号：US20090128214A1
公开(公告)日：2009-05-21
申请号：US12177023
申请日：2008-07-21
申请人： Hyung Soo Kim , Kun Woo Park , Yong Ju Kim , Hee Woong Song , Ic Su Oh , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee
发明人： Hyung Soo Kim , Kun Woo Park , Yong Ju Kim , Hee Woong Song , Ic Su Oh , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee
IPC分类号： H03L5/00
CPC分类号： G11C7/1078 , G11C7/1084 , G11C7/1087
摘要： A data receiver includes a plurality of amplifiers for receiving data in response to clock signals having a predetermined phase difference, and amplifying the received data by performing an equalization function based on feedback data, thereby outputting amplification signals, and a plurality of latches for latching output of the amplifiers, respectively. One amplifier receives the amplification signal, as feedback data, from another amplifier receiving a clock signal having a phase more advanced than a phase of a clock signal received in the one amplifier.
摘要翻译：数据接收机包括响应于具有预定相位差的时钟信号而接收数据的多个放大器，并且通过基于反馈数据执行均衡功能来放大接收数据，从而输出放大信号，以及多个锁存器用于锁存输出的放大器。一个放大器接收作为反馈数据的放大信号，来自另一个放大器接收时钟信号，该时钟信号的相位比在一个放大器中接收的时钟信号的相位更先进。

95. 发明申请

US20090128200A1 RECEIVER CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS 失效
标题翻译：半导体存储器接收器电路
公开(公告)号：US20090128200A1
公开(公告)日：2009-05-21
申请号：US12175224
申请日：2008-07-17
申请人： Tae-Jin Hwang , Kun-Woo Park , Yong-Ju Kim , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Hae-Rang Choi , Ji-Wang Lee
发明人： Tae-Jin Hwang , Kun-Woo Park , Yong-Ju Kim , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Hae-Rang Choi , Ji-Wang Lee
IPC分类号： H03L7/00 , H03L5/00
CPC分类号： G11C7/1078 , G11C7/1084 , G11C7/1087
摘要： A receiver circuit capable of controlling setup/hold time includes a first phase transmission unit configured to generate a first output signal by detecting input data according to plural detection levels while being synchronized with a first clock signal, and controlling setup/hold time of the first output signal based on a level of a first offset voltage, a level converter configured to control a voltage level of the first output signal according to a first code, and a second phase transmission unit configured to receive an output signal of the level converter for as a second offset voltage while being synchronized with a second clock signal, to generate a second output signal by detecting the input data according to the detection levels, and to control setup/hold time of the second output signal.
摘要翻译：能够控制建立/保持时间的接收机电路包括：第一相位发送单元，被配置为通过在与第一时钟信号同步的同时根据多个检测电平检测输入数据来生成第一输出信号，以及控制第一输入信号的建立/保持时间基于第一偏移电压的电平的输出信号，被配置为根据第一代码来控制第一输出信号的电压电平的电平转换器;以及第二相位发送单元，被配置为接收电平转换器的输出信号作为第二偏移电压，同时与第二时钟信号同步，通过根据检测电平检测输入数据产生第二输出信号，并控制第二输出信号的建立/保持时间。

96. 发明申请

US20090116596A1 LOW POWER, HIGH SPEED RECEIVER CIRCUIT FOR USE IN A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
标题翻译：低功率，高速接收电路，用于半导体集成电路
公开(公告)号：US20090116596A1
公开(公告)日：2009-05-07
申请号：US12170254
申请日：2008-07-09
申请人： Ic Su Oh , Kun Woo Park , Yong Ju Kim , Hee Woong Song , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee
发明人： Ic Su Oh , Kun Woo Park , Yong Ju Kim , Hee Woong Song , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee
IPC分类号： H04L7/00
CPC分类号： G11C7/1051 , G11C7/062 , G11C7/1069 , G11C11/56 , G11C27/026 , G11C2211/5634 , G11C2211/5642 , H04L25/0272 , H04L25/061 , H04L25/4919
摘要： A receiver circuit according to the invention includes a first phase transmission unit that is synchronized with a first clock, detects input data according to a plurality of detection levels, and transmits a first output signal, a first discharging control unit that controls a second phase transmission unit in response to the first output signal and adjusts the transmission speed of the second phase transmission unit by changing a node potential where an output of the second phase transmission is determined, and the second phase transmission unit that is synchronized with a second clock, detects the input data according to an output of the first discharging control unit, and transmits a second output signal.
摘要翻译：根据本发明的接收机电路包括与第一时钟同步的第一相位传输单元，根据多个检测电平检测输入数据，并发送第一输出信号;第一放电控制单元，其控制第二相位传输单元，响应于第一输出信号，并且通过改变确定第二相位传输的输出的节点电位来调整第二相位传输单元的传输速度，并且与第二时钟同步的第二相位传输单元检测所述输入数据根据所述第一放电控制单元的输出，并发送第二输出信号。

97. 发明申请

US20090059703A1 RECEIVER CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS 失效
标题翻译：半导体存储器接收器电路
公开(公告)号：US20090059703A1
公开(公告)日：2009-03-05
申请号：US12172108
申请日：2008-07-11
申请人： Tae Jin Hwang , Yong Ju Kim , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Hae Rang Choi , Ji Wang Lee
发明人： Tae Jin Hwang , Yong Ju Kim , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Hae Rang Choi , Ji Wang Lee
IPC分类号： G11C7/00
CPC分类号： G11C7/1078 , G11C7/1084 , G11C7/1087 , G11C7/1093 , G11C7/22 , G11C7/222
摘要： A receiver circuit is described herein, comprising a first data determining unit configured to detect and amplify a voltage level difference between first and second external data and generate first and second sense signals and to generate first internal data in response to the first and second sense signals, a first offset control unit configured to generate first and second offset signals in response to the first and second sense signals, the first and second offset signals swinging between a maximum voltage level and a minimum voltage level determined based on a first code, a second data determining unit configured to detect and amplify the voltage level difference between the first and second external data to generate third and fourth sense signals and to generate second internal data in response to the third and fourth sense signals; and a second offset control unit for generating third and fourth offset signals in response to the third and fourth sense signals, the third and fourth offset signals swinging between a maximum voltage level and a minimum voltage level determined based on a second code, wherein the first data determining unit is configured to determine setup time and hold time of the first internal data in response to the third and fourth offset signals, and wherein the second data determining unit is configured to determine setup time and hold time of the second internal data in response to the first and second offset signals.
摘要翻译：本文描述了一种接收器电路，包括：第一数据确定单元，被配置为检测和放大第一和第二外部数据之间的电压电平差，并产生第一和第二感测信号，并响应于第一和第二感测信号产生第一内部数据第一偏移控制单元，被配置为响应于第一和第二感测信号产生第一和第二偏移信号，第一和第二偏移信号在基于第一代码确定的最大电压电平和最小电压电平之间摆动，第二偏移控制单元数据确定单元，被配置为检测和放大第一和第二外部数据之间的电压电平差，以产生第三和第四感测信号，并响应于第三和第四感测信号产生第二内部数据; 以及第二偏移控制单元，用于响应于第三和第四感测信号产生第三和第四偏移信号，第三和第四偏移信号在基于第二代码确定的最大电压电平和最小电压电平之间摆动，其中第一和第二偏移信号数据确定单元被配置为响应于第三和第四偏移信号来确定第一内部数据的建立时间和保持时间，并且其中第二数据确定单元被配置为响应于确定第二内部数据的建立时间和保持时间到第一和第二偏移信号。

98. 发明授权

US08610475B2 Integrated circuit 有权
标题翻译：集成电路
公开(公告)号：US08610475B2
公开(公告)日：2013-12-17
申请号：US12981764
申请日：2010-12-30
申请人： Yong-Ju Kim , Seong-Jun Lee , Hae-Rang Choi , Jae-Min Jang
发明人： Yong-Ju Kim , Seong-Jun Lee , Hae-Rang Choi , Jae-Min Jang
IPC分类号： H03L7/06
CPC分类号： H03L7/0816
摘要： An integrated circuit includes a delay locked loop configured to delay a reference clock signal by a delay time for delay locking and generate a delay locked clock signal, a clock transmission circuit configured to transmit the delay locked clock signal in response to a clock transmission signal, a duty correction circuit configured to perform duty correction operation on an output clock signal of the clock transmission circuit, and a clock transmission signal generation circuit configured to generate the clock transmission signal in response to a command and burst length information.
摘要翻译：一种集成电路包括：延迟锁定环路，被配置为延迟参考时钟信号延迟锁定的延迟时间，并产生延迟锁定时钟信号;时钟传输电路，被配置为响应于时钟传输信号传输延迟锁定时钟信号; 配置为对时钟发送电路的输出时钟信号进行占空比校正操作的占空比校正电路，以及响应于命令和突发长度信息而生成时钟发送信号的时钟发送信号生成电路。

99. 发明授权

US08373456B2 Domain crossing circuit of a semiconductor memory apparatus 有权
标题翻译：半导体存储装置的域交叉电路
公开(公告)号：US08373456B2
公开(公告)日：2013-02-12
申请号：US12486281
申请日：2009-06-17
申请人： Hae Rang Choi , Yong Ju Kim , Sung Woo Han , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Ji Wang Lee , Jae Min Jang , Chang Kun Park
发明人： Hae Rang Choi , Yong Ju Kim , Sung Woo Han , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Ji Wang Lee , Jae Min Jang , Chang Kun Park
IPC分类号： H03L7/00
CPC分类号： H04L7/0338 , G11C7/1078 , G11C7/1087 , G11C7/1093 , G11C7/22 , G11C7/222 , H04L7/0045
摘要： The domain crossing circuit of a semiconductor memory apparatus for improving a timing margin includes a sampler that provides a sampling internal signal generated by delaying an internal input signal by a predetermined time in response to a clock and an edge information signal that defines an output timing of the sampling internal signal and an output stage that allows the sampling internal signal to be synchronized with the clock in response to the edge information signal to be output as a final output signal.
摘要翻译：用于提高定时裕度的半导体存储装置的域交叉电路包括：采样器，其通过响应于时钟和内部输入信号产生的采样内部信号，边缘信息信号定义为输出定时采样内部信号和输出级，其允许采样内部信号与时钟同步，以响应于作为最终输出信号输出的边缘信息信号。

100. 发明授权

US08319535B2 Delay locked loop 有权
标题翻译：延迟锁定环路
公开(公告)号：US08319535B2
公开(公告)日：2012-11-27
申请号：US13111568
申请日：2011-05-19
申请人： Jae-Min Jang , Yong-Ju Kim , Hae-Rang Choi
发明人： Jae-Min Jang , Yong-Ju Kim , Hae-Rang Choi
IPC分类号： H03L7/06
CPC分类号： H03L7/087 , G11C7/222 , H03L7/0814 , H03L7/0816
摘要： A DLL circuit includes a common delay line configured to generate a delay locked clock by selectively delaying a source clock by one or more unit delays in response to a first delay control code or a second delay control code, a clock cycle detector configured to compare a phase of the source clock with a phase of the delay locked clock in a cycle detection mode and generate the first delay control code corresponding to a delay amount of a cycle of the source clock based on a result of comparing the phases of the source and delay locked clocks, a feedback delay configured to delay the delay locked clock and output a feedback clock, and a delay amount controller configured to compare the phase of the source clock with a phase of the feedback clock in a delay locking mode and change the second delay control code based on a result of comparing the source and feedback clocks.
摘要翻译： DLL电路包括公共延迟线，其配置为通过响应于第一延迟控制代码或第二延迟控制代码选择性地将源时钟延迟一个或多个单位延迟来产生延迟锁定时钟，时钟周期检测器被配置为源时钟的相位以延迟锁定时钟的相位处于周期检测模式，并且基于比较源极和延迟的相位的结果生成与源时钟的周期的延迟量相对应的第一延迟控制代码锁定时钟，被配置为延迟延迟锁定时钟并输出反馈时钟的反馈延迟，以及延迟量控制器，被配置为将延迟锁定模式中的源时钟的相位与反馈时钟的相位进行比较，并且改变第二延迟基于比较源和反馈时钟的结果的控制代码。

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