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91. 发明申请

US20100025549A1 Structure for fixing reducer for sprinkler in side wall 有权
标题翻译：侧壁喷淋头固定减速机结构
公开(公告)号：US20100025549A1
公开(公告)日：2010-02-04
申请号：US12460549
申请日：2009-07-20
申请人： Hyung Soo Kim
发明人： Hyung Soo Kim
IPC分类号： F16L3/08
CPC分类号： F16L3/18 , A62C31/28 , A62C35/68
摘要： The present invention relates to a structure for fixing a reducer for a sprinkler in a side wall, and more particularly, to a structure for fixing a reducer for a sprinkler for side wall construction, in which since the reducer can easily adjust a distance from the side wall in the horizontal direction, a connection work between the reducer and the sprinkler head for the side wall construction connected to the reducer can be conveniently performed.
摘要翻译：本发明涉及一种用于在侧壁中固定用于喷洒器的减速器的结构，更具体地，涉及一种用于固定用于侧壁结构的喷洒器的减速器的结构，其中由于减速器可以容易地调节距离侧壁在水平方向上，可以方便地进行与还原器连接的侧壁结构的减速器和喷头之间的连接作业。

92. 发明授权

US07646223B2 Phase locked loop circuit having set initial locking level and control method thereof 失效
标题翻译：具有设定初始锁定电平的锁相环电路及其控制方法
公开(公告)号：US07646223B2
公开(公告)日：2010-01-12
申请号：US11640965
申请日：2006-12-19
申请人： Yong-Ju Kim , Kun-Woo Park , Hyung-Soo Kim , Ic-Su Oh , Hee-Woong Song , Jong-Woon Kim , Tae-Jin Hwang
发明人： Yong-Ju Kim , Kun-Woo Park , Hyung-Soo Kim , Ic-Su Oh , Hee-Woong Song , Jong-Woon Kim , Tae-Jin Hwang
IPC分类号： H03L7/06
CPC分类号： H03L7/107 , H03L7/1075
摘要： A phase locked loop circuit and a control method thereof. A phase locked loop circuit includes a phase detecting and correcting block configured to detect a phase difference between a reference clock and a feedback clock, and to correct the phase of the feedback clock such that the phase of the reference clock and the phase of the feedback clock are consistent with each other, and an initial locking level setting block configured to set a locking level in a normal operation mode in the phase detecting and correcting block. The initial locking level setting block includes a digital-to-analog converting unit configured to generate an analog voltage according to a digital code corresponding to the set frequency, and charges the capacitive element with the analog voltage, and a switching unit configured to connect the digital-to-analog converting unit and the capacitive element in response to an input of an operation start signal.
摘要翻译：一种锁相环电路及其控制方法。锁相环电路包括相位检测和校正块，被配置为检测参考时钟和反馈时钟之间的相位差，并且校正反馈时钟的相位，使得参考时钟的相位和反馈的相位时钟彼此一致，并且初始锁定电平设置块被配置为在相位检测和校正块中将正常操作模式中的锁定电平设置为1。初始锁定电平设置块包括数模转换单元，被配置为根据与设定频率相对应的数字码产生模拟电压，并且用模拟电压对电容元件充电;以及开关单元，被配置为将数字模拟转换单元和电容元件，以响应于操作开始信号的输入。

93. 发明申请

US20090149142A1 RECEIVER CIRCUIT 有权
标题翻译：接收电路
公开(公告)号：US20090149142A1
公开(公告)日：2009-06-11
申请号：US12179486
申请日：2008-07-24
申请人： Tae Jin Hwang , Kun Woo Park , Yong Ju Kim , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Hae Rang Choi , Ji Wang Lee , Jae Min Jang
发明人： Tae Jin Hwang , Kun Woo Park , Yong Ju Kim , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Hae Rang Choi , Ji Wang Lee , Jae Min Jang
IPC分类号： G06F3/033
CPC分类号： G06F13/4072
摘要： A receiver circuit is capable of improving its operating characteristics. The receiver circuit includes a variable converter configured to output off-set control voltages in a first output range in a first operation mode and output the off-set control voltages in a second output range in a second operation mode according to a test mode activation signal, and a sense amplifier configured to sense input data based on a sensitivity, wherein the sensitivity is controlled by the off-set control voltages.
摘要翻译：接收机电路能够改善其操作特性。接收器电路包括可变转换器，其被配置为在第一操作模式中在第一输出范围中输出偏移控制电压，并且根据测试模式激活信号在第二操作模式中将偏移控制电压输出到第二输出范围以及感测放大器，被配置为基于灵敏度来感测输入数据，其中灵敏度由偏移控制电压控制。

94. 发明申请

US20090129459A1 DATA RECEIVER OF SEMICONDUCTOR INTEGRATED CIRCUIT 失效
标题翻译：半导体集成电路的数据接收器
公开(公告)号：US20090129459A1
公开(公告)日：2009-05-21
申请号：US12177829
申请日：2008-07-22
申请人： Hyung Soo Kim , Kun Woo Park , Yong Ju Kim , Hee Woong Song , Ic Su Oh , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee
发明人： Hyung Soo Kim , Kun Woo Park , Yong Ju Kim , Hee Woong Song , Ic Su Oh , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee
IPC分类号： H03K5/159
CPC分类号： H03K19/09425
摘要： A semiconductor integrated circuit equipped with an equalizer which has a circuit structure simpler than that of a related equalizer according to an FFE scheme or a DFE scheme and is capable of preventing a noise component from being amplified. The data receiver includes a plurality of receiver units, wherein each receiver unit includes a plurality of level detectors which detect different levels, and an encoder, in which the level detectors receive data according to a clock signal having a predetermined phase difference and perform an amplification operation including an equalization function based on feedback data, thereby outputting an amplification signal, and wherein level detectors of one receiver unit receive an amplification signal, as the feedback data, from level detectors of another receiver unit that receives a first clock signal having a phase more advanced than a phase of a second clock signal received in one receiver unit.
摘要翻译：一种配备有均衡器的半导体集成电路，其具有比根据FFE方案或DFE方案的相关均衡器的电路结构简单的电路结构，并且能够防止噪声分量被放大。数据接收机包括多个接收机单元，其中每个接收机单元包括检测不同电平的多个电平检测器和编码器，其中电平检测器根据具有预定相位差的时钟信号接收数据并执行放大操作包括基于反馈数据的均衡功能，从而输出放大信号，并且其中一个接收器单元的电平检测器从另一接收器单元的电平检测器接收作为反馈数据的放大信号，该接收器单元接收具有相位的第一时钟信号比在一个接收机单元中接收的第二时钟信号的相位更先进。

95. 发明申请

US20090067278A1 DATA OUTPUT CIRCUIT FOR SEMICONDUCTOR MEMORY APPARATUS 有权
标题翻译：半导体存储器的数据输出电路
公开(公告)号：US20090067278A1
公开(公告)日：2009-03-12
申请号：US12169568
申请日：2008-07-08
申请人： Hae Rang Choi , Kun Woo Park , Yong Ju Kim , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Ji Wang Lee
发明人： Hae Rang Choi , Kun Woo Park , Yong Ju Kim , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Ji Wang Lee
IPC分类号： G11C8/08
CPC分类号： G11C7/1051 , G11C7/1057 , G11C29/028 , G11C29/1201 , G11C29/50
摘要： A data output circuit for a semiconductor memory apparatus includes a driver control signal generating unit that has a plurality of control signal generating units, each of which generates a driver unit control signal in response to a test signal during a test, and generates the driver unit control signal according to whether or not a fuse is cut after the test is completed, a first driver that has a plurality of driver units, each of which is activated in response to the driver unit control signal to drive a first data signal as an input signal and to output the driven first data signal to an output node, a signal combining unit that generates a first driver control signal in response to the driver unit control signal and an enable signal, and a second driver that has a plurality of driver units, each of which is activated in response to the first driver control signal to drive a second data signal as an input signal and to output the driven second data signal to the output node, and the number of driver units being two or more times as much as the number of driver units in the first driver. A voltage level on the output node is the voltage level of an output signal.
摘要翻译：一种用于半导体存储装置的数据输出电路，包括具有多个控制信号生成单元的驱动器控制信号生成单元，每个控制信号生成单元响应于测试期间的测试信号生成驱动单元控制信号，并且生成驱动单元根据在测试完成之后是否切断熔丝的控制信号，具有多个驱动单元的第一驱动器，每个驱动器单元响应于驱动单元控制信号被激活以驱动第一数据信号作为输入信号并将驱动的第一数据信号输出到输出节点;响应于驱动单元控制信号和使能信号产生第一驱动器控制信号的信号组合单元，以及具有多个驱动器单元的第二驱动器，其中的每一个响应于第一驱动器控制信号被激活，以驱动第二数据信号作为输入信号，并将驱动的第二数据信号输出到输出节点;以及驱动器单元的数量是第一驱动器中的驱动器单元的数量的两倍或更多倍。输出节点上的电压电平是输出信号的电压电平。

96. 发明申请

US20090045862A1 CLOCK GENERATING CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS 审中-公开
标题翻译：半导体存储器的时钟发生电路
公开(公告)号：US20090045862A1
公开(公告)日：2009-02-19
申请号：US12167066
申请日：2008-07-02
申请人： Yong Ju Kim , Kun Woo Park , Dae Han Kwon , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee
发明人： Yong Ju Kim , Kun Woo Park , Dae Han Kwon , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee
IPC分类号： H03K4/00
CPC分类号： H03K5/151
摘要： A clock generating circuit of a semiconductor memory apparatus includes a phase splitter that delays a clock to generate a delayed clock and inverts the clock to generate an inverted clock, and a clock buffer that buffers the delayed clock and the inverted clock and outputs a rising clock and a falling clock.
摘要翻译：半导体存储装置的时钟产生电路包括：相位分离器，其延迟时钟以产生延迟的时钟并使时钟反相以产生反相时钟;以及时钟缓冲器，缓冲延迟时钟和反相时钟，并输出上升时钟和一个下降的时钟。

97. 发明申请

US20090041154A1 APPARATUS FOR TRANSMITTING SIGNAL IN SEMICONDUCTOR INTEGRATED CIRCUIT 失效
标题翻译：用于在半导体集成电路中发送信号的装置
公开(公告)号：US20090041154A1
公开(公告)日：2009-02-12
申请号：US11966250
申请日：2007-12-28
申请人： Hyung Soo Kim , Kun Woo Park , Yong Ju Kim , Jong Woon Kim , Hee Woong Song , Ic Su Oh , Tae Jin Hwang
发明人： Hyung Soo Kim , Kun Woo Park , Yong Ju Kim , Jong Woon Kim , Hee Woong Song , Ic Su Oh , Tae Jin Hwang
IPC分类号： H04L25/49
CPC分类号： H04L25/4917
摘要： An apparatus for transmitting a signal in a semiconductor integrated circuit includes a multilevel transmission control block that outputs a plurality of bits of an input signal in serial or parallel according to whether a multilevel transmission operation is performed or not, and a signal processing block that selectively performs the multilevel transmission operation according to a form of the input signal, which are output in serial or parallel from the multilevel transmission control block.
摘要翻译：一种用于在半导体集成电路中发送信号的装置包括：多电平传输控制块，其根据是否执行多级传输操作来串行或并行输出输入信号的多个位;以及信号处理块，其选择性地根据从多级传输控制块串行或并行输出的输入信号的形式执行多级传输操作。

98. 发明申请

US20090027369A1 Organic light emitting display and driving method thereof 有权
标题翻译：有机发光显示器及其驱动方法
公开(公告)号：US20090027369A1
公开(公告)日：2009-01-29
申请号：US12219602
申请日：2008-07-24
申请人： Wang-jo Lee , Bo-yong Chung , Sang-moo Choi , Hyung-soo Kim
发明人： Wang-jo Lee , Bo-yong Chung , Sang-moo Choi , Hyung-soo Kim
IPC分类号： G09G5/00 , G09G3/30
CPC分类号： G09G3/3275 , G09G3/20 , G09G3/2022 , G09G2310/0235 , G09G2310/0291 , G09G2310/0297
摘要： An organic light emitting display configured to be driven using a frame divided into a plurality of sub-frames includes a data driver configured to supply a plurality of data signals to output lines during a first period of one horizontal period of the sub-frame, a scan driver configured to sequentially supply a scan signal to scan lines during a second period of the one horizontal period of the sub-frame, a demultiplexer coupled to each output line, the demultiplexer being configured to supply the data signals to a plurality of data lines, buffers configured to supply buffers supplying signals from the demulitplexers to the data lines, the buffers including PMOS transistors, and pixels disposed at intersections of the scan lines and the data lines, the pixels being configured to display images corresponding to the data signals.
摘要翻译：配置为使用划分为多个子帧的帧来驱动的有机发光显示器包括数据驱动器，被配置为在子帧的一个水平周期的第一周期期间将多个数据信号提供给输出行，扫描驱动器，其被配置为在所述子帧的所述一个水平周期的第二周期期间将扫描信号顺序地提供给扫描线，耦合到每个输出线的解复用器，所述解复用器被配置为将数据信号提供给多个数据线缓冲器，被配置为提供从所述解复用器向数据线提供信号的缓冲器，所述缓冲器包括PMOS晶体管，以及设置在所述扫描线和所述数据线的交点处的像素，所述像素被配置为显示对应于所述数据信号的图像。

99. 发明申请

US20080191776A1 SIGNAL RECEIVER CIRCUIT CAPABLE OF IMPROVING AREA AND POWER EFFICIENCY IN SEMICONDUCTOR INTEGRATED CIRCUITS 有权
标题翻译：提高半导体集成电路面积和功率效率的信号接收电路
公开(公告)号：US20080191776A1
公开(公告)日：2008-08-14
申请号：US11959264
申请日：2007-12-18
申请人： Hee Woong Song , Kun Woo Park , Yong Ju Kim , Jong Woon Kim , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang
发明人： Hee Woong Song , Kun Woo Park , Yong Ju Kim , Jong Woon Kim , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang
IPC分类号： H03L5/00
CPC分类号： H03K5/08 , H03K3/356139 , H03K3/356191 , H04L25/062
摘要： A signal receiver circuit includes a first level detector for offset-controlling a first output node in response to a pair of first reference signals. A second level detector offset-controls a second output node in response to a pair of second reference signals.
摘要翻译：信号接收器电路包括第一电平检测器，用于响应于一对第一参考信号偏移控制第一输出节点。第二级检测器偏移 - 响应于一对第二参考信号来控制第二输出节点。

100. 发明申请

US20080061840A1 Receiver circuit having compensated offset voltage 失效
标题翻译：接收器电路具有补偿失调电压
公开(公告)号：US20080061840A1
公开(公告)日：2008-03-13
申请号：US11822503
申请日：2007-07-06
申请人： Tae Jin Hwang , Kun Woo Park , Yong Ju Kim , Jong Woon Kim , Hee Woong Song , Ic Su Oh , Hyung Soo Kim
发明人： Tae Jin Hwang , Kun Woo Park , Yong Ju Kim , Jong Woon Kim , Hee Woong Song , Ic Su Oh , Hyung Soo Kim
IPC分类号： H03F3/42
CPC分类号： H03F3/45766 , G11C7/02 , G11C7/065 , G11C7/08 , G11C7/1051 , G11C7/1057 , G11C7/106 , G11C7/1078 , G11C7/109 , H03F3/45179 , H03F3/45475 , H03F3/45991 , H03F2203/45136 , H03F2203/45212 , H03F2203/45352 , H03F2203/45354
摘要： A receiver circuit includes an offset control signal generating unit that outputs a plurality of offset control signals using an offset voltage. A sense amplifier receives a first current and a second current generated on the basis of an up input signal and a down input signal, respectively, converts the first current and the second current into an up compensating signal and a down compensating signal having electric potentials compensating the offset voltage, and amplifies the up compensating signal and the down compensating signal to output an up output signal and a down output signal.
摘要翻译：接收器电路包括偏移控制信号生成单元，其使用偏移电压输出多个偏移控制信号。读出放大器分别接收基于上输入信号和下输入信号产生的第一电流和第二电流，将第一电流和第二电流分别转换成上补偿信号和具有补偿电位的下补偿信号偏移电压，并放大上补偿信号和下降补偿信号，以输出上输出信号和下输出信号。

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