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91. 发明授权

US08892819B2 Multi-core system and external input/output bus control method 有权
标题翻译：多核系统和外部输入/输出总线控制方式
公开(公告)号：US08892819B2
公开(公告)日：2014-11-18
申请号：US13718292
申请日：2012-12-18
申请人： Fujitsu Limited
发明人： Koji Kurihara , Koichiro Yamashita , Hiromasa Yamauchi
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/0835 , G06F12/0806 , G06F12/0811 , G06F2212/1028 , G06F2212/502 , G06F2212/6012 , Y02D10/13
摘要： A multi-core system includes processor cores having caches; an external input/output bus connected to the processor cores; memory accessed by the processor cores via the external input/output bus; profile information indicating the volume of a write access to the memory by tasks concurrently allocated to the processor cores and whether a cache miss will occur in a read access to the caches; and an operating system that controls clock frequency of the external input/output bus to be a first frequency, based on the volume of the write access to the memory by the tasks and the bus width of the external input/output bus when a cache miss in read access is judged to not occur in executing the tasks and that controls the clock frequency of the external input/output bus to be a second frequency higher than the first frequency when a cache miss in read access is judged.
摘要翻译：多核系统包括具有高速缓存的处理器核心; 连接到处理器核心的外部输入/输出总线; 由处理器内核经由外部输入/输出总线访问的存储器; 简档信息，指示并发分配给处理器核的任务对存储器的写访问量，以及在对高速缓存的读取访问中是否发生高速缓存未命中; 以及操作系统，其将外部输入/输出总线的时钟频率控制为第一频率，所述操作系统基于当高速缓存未命中时任务和对外部输入/输出总线的总线宽度的写访问量在读取访问被判定为不执行任务时，并且当判断读取访问中的高速缓存未命中时，将外部输入/输出总线的时钟频率控制为高于第一频率的第二频率。

92. 发明申请

US20140164468A1 DATA PROCESSING METHOD 有权
标题翻译：数据处理方法
公开(公告)号：US20140164468A1
公开(公告)日：2014-06-12
申请号：US14090430
申请日：2013-11-26
申请人： FUJITSU LIMITED
发明人： Koichiro Yamashita , Hiromasa Yamauchi , Takahisa Suzuki , Koji Kurihara
IPC分类号： H04L29/08
CPC分类号： H04L67/10 , H04W4/08 , H04W84/22
摘要： A data processing method is executed by a first data processing apparatus, and includes setting based on a size of data that is for executing a predetermined function, a first division number for dividing the data; producing groups of a second division number, each including N (a positive integer) elements by dividing the first division number; assigning a plurality of data processing apparatuses each capable of communicating with the first data processing apparatus, to the groups of the second division number; and assigning sub-data formed by dividing the data by the first division number, to the groups of the second division number.
摘要翻译：数据处理方法由第一数据处理装置执行，并且包括基于用于执行预定功能的数据的大小的设置，用于划分数据的第一分割数; 生成第二分割数的组，每组包括通过划分第一分割数的N（正整数）元素; 将能够与第一数据处理装置通信的多个数据处理装置分配给第二分割数的组; 以及将通过将所述数据除以所述第一分割数而形成的子数据分配给所述第二分割数的组。

93. 发明申请

US20140108758A1 DATA PROCESSING METHOD AND DATA PROCESSING SYSTEM 有权
标题翻译：数据处理方法和数据处理系统
公开(公告)号：US20140108758A1
公开(公告)日：2014-04-17
申请号：US14134675
申请日：2013-12-19
申请人： FUJITSU LIMITED
发明人： Toshiya Otomo , Koichiro Yamashita , Naoki Odate , Takahisa Suzuki , Hiromasa Yamauchi , Koji Kurihara
IPC分类号： G06F3/06
CPC分类号： G06F3/065 , G06F3/0604 , G06F3/061 , G06F3/0614 , G06F3/0683 , G06F3/0685 , G06F11/1464 , G06F11/1469 , G06F11/2035 , G06F11/2043 , G06F11/2097 , H04L67/1097
摘要： A data processing method that is executed by a first data processing apparatus included among plural data processing apparatuses, includes producing a copy of data, and restoration information that includes a first address of memory to which the copy of the data is stored; transmitting any one among the data and the copy of the data to a second data processing apparatus that is included among the data processing apparatuses; and storing the restoration information to shared memory that is memory of at least one data processing apparatus among the data processing apparatuses, and shared among the data processing apparatuses.
摘要翻译：一种由多个数据处理装置中包括的第一数据处理装置执行的数据处理方法，包括产生数据的副本以及包含存储数据的副本的存储器的第一地址的恢复信息; 将所述数据和所述数据的副本中的任一个发送到所述数据处理装置中包括的第二数据处理装置; 以及将所述恢复信息存储在所述数据处理装置中的至少一个数据处理装置的存储器的共享存储器中，并在所述数据处理装置之间共享。

94. 发明申请

US20140012921A1 FILE SHARING METHOD AND TERMINAL 有权
标题翻译：文件共享方法和终端
公开(公告)号：US20140012921A1
公开(公告)日：2014-01-09
申请号：US14026481
申请日：2013-09-13
申请人： FUJITSU LIMITED
发明人： Toshiya Otomo , Koichiro Yamashita , Takahisa Suzuki , Hiromasa Yamauchi , Koji Kurihara , Naoki Odate , Tetsuo Hiraki
IPC分类号： H04L29/08
CPC分类号： H04L67/104 , G06F9/5094 , G06F17/30115 , G06F17/30165 , H04L67/04 , H04L67/06 , H04L67/10 , Y02D10/22
摘要： A file sharing method executed by a first terminal, and including selecting from among multiple terminals including the first terminal and based on a remaining battery level of the terminals and a processing time of a shared process, a second terminal to execute the shared process for sharing multiple files among the terminals; and assigning the shared process to the second terminal.
摘要翻译：一种由第一终端执行的文件共享方法，包括从包括第一终端的多个终端中选择并基于终端的剩余电池电平和共享处理的处理时间进行选择，第二终端执行用于共享的共享处理终端之间的多个文件; 以及将共享进程分配给第二终端。

95. 发明申请

US20130318310A1 PROCESSOR PROCESSING METHOD AND PROCESSOR SYSTEM 审中-公开
标题翻译：处理器处理方法和处理器系统
公开(公告)号：US20130318310A1
公开(公告)日：2013-11-28
申请号：US13949922
申请日：2013-07-24
申请人： FUJITSU LIMITED
发明人： Hiromasa Yamauchi , Koichiro Yamashita , Takahisa Suzuki , Koji Kurihara , Fumihiko Hayakawa , Toshiya Otomo
IPC分类号： G06F12/00
CPC分类号： G06F12/00 , G06F11/0724 , G06F11/073 , G06F11/076 , G06F11/203 , G06F11/2038 , G06F11/3471 , G06F11/3476
摘要： A processor processing method is executed by a memory controller, and includes determining based on a log of access of a shared resource by a first application, whether the first application running on a first processor operates normally; and causing a second processor to run a second application other than the first application upon the first application being determined to not be operating normally.
摘要翻译：处理器处理方法由存储器控制器执行，并且包括基于第一应用的共享资源的访问日志来确定在第一处理器上运行的第一应用是否正常运行; 并且使得第二处理器在第一应用被确定为不正常工作时运行除第一应用之外的第二应用。

96. 发明申请

US20130312002A1 SCHEDULING METHOD AND SCHEDULING SYSTEM 有权
标题翻译：调度方法和调度系统
公开(公告)号：US20130312002A1
公开(公告)日：2013-11-21
申请号：US13946361
申请日：2013-07-19
申请人： FUJITSU LIMITED
发明人： Hiromasa Yamauchi , Koichiro Yamashita , Tetsuo Hiraki , Koji Kurihara , Toshiya Otomo
IPC分类号： G06F9/50
CPC分类号： G06F9/5027 , G06F9/4881 , G06F9/5083
摘要： A scheduling method executed by a scheduler that manages multiple processors, includes detecting based on an application information table when a first application is started up, a processor that executes a second application that is not executed concurrently with the first application; and assigning the first application to the processor.
摘要翻译：由管理多个处理器的调度器执行的调度方法包括当第一应用启动时基于应用信息表进行检测;执行与第一应用并行执行的第二应用的处理器; 以及将所述第一应用分配给所述处理器。

97. 发明申请

US20130298132A1 MULTI-CORE PROCESSOR SYSTEM AND SCHEDULING METHOD 审中-公开
标题翻译：多核处理器系统和调度方法
公开(公告)号：US20130298132A1
公开(公告)日：2013-11-07
申请号：US13941141
申请日：2013-07-12
申请人： Fujitsu Limited
发明人： Koji Kurihara , Koichiro Yamashita , Takahisa Suzuki , Hiromasa Yamauchi , Toshiya Otomo , Naoki Odate
IPC分类号： G06F9/48
CPC分类号： G06F9/4881 , G06F9/4843
摘要： A multi-core processor system includes plural processors; and a scheduler that assigns applications to the processors. The scheduler upon receiving a startup request for a given application and based on start times of the applications executed by the processors, selects a processor that is to execute the given application.
摘要翻译：多核处理器系统包括多个处理器; 以及将应用程序分配给处理器的调度器。调度器在接收到给定应用程序的启动请求并基于处理器执行的应用程序的启动时间时，选择要执行给定应用程序的处理器。

98. 发明申请

US20130275790A1 MULTICORE PROCESSOR SYSTEM AND POWER CONTROL METHOD 有权
标题翻译：多处理器系统和功率控制方法
公开(公告)号：US20130275790A1
公开(公告)日：2013-10-17
申请号：US13916039
申请日：2013-06-12
申请人： FUJITSU LIMITED
发明人： Takahisa SUZUKI , Koichiro Yamashita , Hiromasa Yamauchi , Koji Kurihara , Fumihiko Hayakawa , Naoki Odate , Tetsuo Hiraki , Toshiya Otomo
IPC分类号： G06F1/32
CPC分类号： G06F1/324 , G06F1/3203 , G06F1/3243 , G06F1/3296 , G06F9/526 , Y02D10/126 , Y02D10/152 , Y02D10/172
摘要： A multicore processor system includes multiple processors; a device; a memory that stores information of voltage and clock frequency for minimizing power consumption in connection with a number of the processors accessing to the device; and a power control unit that controls the voltage and the clock frequency of the processors on the basis of the information stored in the memory if the number of the processors accessing to the device changes.
摘要翻译：多核处理器系统包括多个处理器; 一个装置; 存储器，其存储电压和时钟频率的信息，以便与接入设备的多个处理器相关联地最小化功耗; 以及功率控制单元，如果访问设备的处理器的数量改变，则根据存储在存储器中的信息来控制处理器的电压和时钟频率。

99. 发明申请

US20130239113A1 INFORMATION PROCESSING APPARATUS, COMPUTER PRODUCT, AND INFORMATION PROCESSING METHOD 审中-公开
标题翻译：信息处理设备，计算机产品和信息处理方法
公开(公告)号：US20130239113A1
公开(公告)日：2013-09-12
申请号：US13856775
申请日：2013-04-04
申请人： FUJITSU LIMITED
发明人： Koji KURIHARA , Koichiro Yamashita , Hiromasa Yamauchi , Takashisa Suzuki
IPC分类号： G06F9/46
CPC分类号： G06F9/46 , G06F9/52
摘要： An information processing apparatus includes a memory unit having numbers each specifying an output order and a data memory area corresponding to each number; a setting unit that sets in each data memory area correlating an execution order of a thread with a number specifying the output order, a storage location for a value of a common variable of the thread among threads receiving write requests for the value or the common variable; a first storing unit that stores to the data memory area set for each thread, the value of the common variable for the thread of the execution order corresponding to the number specifying the output order of the data memory area; and a second storing unit that upon completion of ail the threads and In the output order, reads-out each value of the common variable stored to the data memory areas and overwrites a specific storage location.
摘要翻译：一种信息处理装置，包括具有各自指定输出顺序的数量的存储器单元和与每个编号对应的数据存储区域; 在每个数据存储区域中设置将线程的执行顺序与指定输出顺序的数字相关联的设置单元，接收针对该值的写入请求的线程的公共变量的值的存储位置或公共变量 ; 存储到针对每个线程设置的数据存储区域的第一存储单元，与指定数据存储区域的输出顺序的数字相对应的执行顺序线程的公共变量的值; 以及第二存储单元，其在完成线程之后，并且在输出顺序中，读出存储到数据存储器区域的公共变量的每个值并覆盖特定的存储位置。

100. 发明申请

US20130238882A1 MULTI-CORE PROCESSOR SYSTEM, MONITORING CONTROL METHOD, AND COMPUTER PRODUCT 有权
标题翻译：多核处理器系统，监控控制方法和计算机产品
公开(公告)号：US20130238882A1
公开(公告)日：2013-09-12
申请号：US13856934
申请日：2013-04-04
申请人： FUJITSU LIMITED
发明人： Takahisa SUZUKI , Koichiro Yamashita , Hiromasa Yamauchi , Koji Kurihara
IPC分类号： G06F9/30
CPC分类号： G06F9/30043 , G06F9/3009 , G06F9/3842 , G06F11/00 , G06F11/0724 , G06F11/1407 , G06F11/1438 , G06F2201/865 , G06F2209/5018
摘要： A multi-core processor system includes a given core among multiple cores, wherein the given core is configured to detect execution of a process by the cores; and generate upon detecting the execution of the process, a specific thread that saves state information indicating an executed state of the process and an executed state of each thread to be monitored of the process.
摘要翻译：多核处理器系统包括多个核心中的给定核心，其中所述给定核心被配置为检测所述核心的进程的执行; 并且在检测到处理的执行时生成一个特定的线程，其保存指示进程的执行状态的状态信息以及要被监视的进程的每个线程的执行状态。

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