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91. 发明授权

US08214417B2 Subnormal number handling in floating point adder without detection of subnormal numbers before exponent subtraction 有权
标题翻译：浮点加法器中的次正规数处理，而不是指数减法之前检测到次正规数
公开(公告)号：US08214417B2
公开(公告)日：2012-07-03
申请号：US12191526
申请日：2008-08-14
申请人： Sadar U. Ahmed
发明人： Sadar U. Ahmed
IPC分类号： G06F7/42
CPC分类号： G06F7/485 , G06F7/49915
摘要： In an embodiment, a floating point unit (FPU) comprises an adder configured to add a first mantissa and a second mantissa and an operand adjust unit coupled to provide at least the first mantissa to the adder. The operand adjust unit is coupled to receive a first operand and a second operand for a floating point add operation, and is configured to: right shift at least one mantissa corresponding to one of the first and second operands responsive to a shift count generated from exponent portions of the first and second operands; to detect whether or not neither, one, or both of the first and second operands are subnormal numbers in parallel with at least a portion of the right shifting; and to left shift by one bit the right shifted mantissa responsive to only one of the first and second operands being a subnormal floating point number.
摘要翻译：在一个实施例中，浮点单元（FPU）包括加法器，其被配置为添加第一尾数和第二尾数以及操作数调整单元，该单元被耦合以向加法器提供至少第一尾数。操作数调整单元被耦合以接收用于浮点添加操作的第一操作数和第二操作数，并且被配置为：响应于从指数生成的移位计数，右移与对应于第一和第二操作数之一的至少一个尾数第一和第二操作数的部分; 以检测第一和第二操作数中的一个或两个是否与右移位的至少一部分并行的是次正规数; 并且响应于第一和第二操作数中的仅一个是正常的浮点数，左移一位右移位尾数。

92. 发明申请

US20110238718A1 LOOK UP TABLE STRUCTURE SUPPORTING QUATERNARY ADDERS 有权
标题翻译：查看表结构支持季刊
公开(公告)号：US20110238718A1
公开(公告)日：2011-09-29
申请号：US12732104
申请日：2010-03-25
申请人： Martin Langhammer
发明人： Martin Langhammer
IPC分类号： G06F7/42
CPC分类号： G06F17/10 , G06F7/5057 , G06F7/506 , G06F7/509
摘要： A lookup table structure having multiple lookup tables is configured to include a quaternary adder. In particular examples, an adaptive logic module (ALM) including a fracturable lookup table (LUT) is configured to include a quaternary (4-1) adder. In some examples, only an XOR gate, an AND gate, two single bit 2-1 multiplexers, and minor connectivity changes to a LUT structure supporting a ternary (3-1) adder are needed to support 4-1 adders. Binary (2-1) and ternary adders are still supported using the original signal flows, as the ternary adder feature can be easily multiplexed out.
摘要翻译：具有多个查找表的查找表结构被配置为包括四进制加法器。在具体示例中，包括可分解查找表（LUT）的自适应逻辑模块（ALM）被配置为包括四进制（4-1）加法器。在一些示例中，仅需要XOR门，AND门，两个单位2-1多路复用器以及支持三进制（3-1）加法器的LUT结构的次要连接性改变以支持4-1加法器。二进制（2-1）和三进制加法器仍然支持使用原始信号流，因为三进制加法器特征可以容易地多路复用。

93. 发明申请

US20100209896A1 VIRTUAL MANIPULATIVES TO FACILITATE LEARNING 审中-公开
标题翻译：虚拟机器人来学习
公开(公告)号：US20100209896A1
公开(公告)日：2010-08-19
申请号：US12691884
申请日：2010-01-22
申请人： Mickelle Weary , Rebecca M. Lewis , Laura Koch , Jennifer A. Seery , Catherine Twomey Fosnot , Aja M. Hammerly , Neil Smith , Nigel J. Green , Roy Leban , Slavi Marinov Marinov , Valentin Mihov , Christopher M. Franklin , Cristopher Cook , Nathan Brutzman , Lou Gray , Benjamin W. Slivka , Lorenzo Pasqualis , Daniel R. Kerns , Tami Caryl Borowick , Ken Curspe , Ronald Anthony Kornfeld , Sarah Daniels
发明人： Mickelle Weary , Rebecca M. Lewis , Laura Koch , Jennifer A. Seery , Catherine Twomey Fosnot , Aja M. Hammerly , Neil Smith , Nigel J. Green , Roy Leban , Slavi Marinov Marinov , Valentin Mihov , Christopher M. Franklin , Cristopher Cook , Nathan Brutzman , Lou Gray , Benjamin W. Slivka , Lorenzo Pasqualis , Daniel R. Kerns , Tami Caryl Borowick , Ken Curspe , Ronald Anthony Kornfeld , Sarah Daniels
IPC分类号： G09B5/00 , G06F7/42 , G09B19/02
CPC分类号： G09B19/025
摘要： Embodiments of the invention disclose a virtual manipulative to facilitate math learning. The virtual manipulative comprises a user interface to progressively form one on more columns to hold partial sums or number decompositions to assist a learner in computing a sum.
摘要翻译：本发明的实施例公开了一种虚拟操纵以便于数学学习。虚拟操纵包括用户界面，用于逐渐在更多列上形成一个以保持部分和或数字分解以帮助学习者计算和。

94. 发明申请

US20100023574A1 FLOATING-POINT ADDITION ACCELERATION 失效
标题翻译：浮点加速
公开(公告)号：US20100023574A1
公开(公告)日：2010-01-28
申请号：US12180759
申请日：2008-07-28
申请人： Lawrence A. Rigge
发明人： Lawrence A. Rigge
IPC分类号： G06F7/42
CPC分类号： G06F7/485 , G06F7/49936
摘要： Embodiments of the present invention generate a normalized floating-point sum from at least two floating-point addends. The mantissa of an un-normalized floating-point sum is generated. A pointer is generated which indicates the location of the left-most significant digit (LSD) in the mantissa of the un-normalized floating-point sum. A plurality of possible values for the exponent of the normalized floating-point sum are generated, in parallel with each other and in parallel with the mantissa addition, based on a common exponent value (e.g., the largest of the two addends' exponent values). Based on the LSD pointer, one of the possible values is selected as the exponent of the normalized floating-point sum. The mantissa of the un-normalized floating-point sum is normalized to yield the mantissa of the normalized floating-point sum. By generating the possible exponent values in parallel, embodiments of the present invention can result in significant time savings over prior-art methods.
摘要翻译：本发明的实施例从至少两个浮点加数生成归一化浮点和。生成非归一化浮点和的尾数。产生指示非标准化浮点和的尾数中最高有效位（LSD）的位置的指针。基于公共指数值（例如，两个加数指数值中的最大值），生成与归一化浮点和指数相关并且与尾数相加并行的多个可能值，。基于LSD指针，选择其中一个可能的值作为归一化浮点和的指数。非归一化浮点和的尾数被归一化以产生标准化浮点和的尾数。通过平行地产生可能的指数值，与现有技术方法相比，本发明的实施例可以导致显着的时间节省。

95. 发明申请

US20100011042A1 Method and Apparatus for Efficient Integer Transform 有权
标题翻译：高效整数变换的方法和装置
公开(公告)号：US20100011042A1
公开(公告)日：2010-01-14
申请号：US12560225
申请日：2009-09-15
申请人： Eric Debes , William W. Macy , Jonathan J. Tyler
发明人： Eric Debes , William W. Macy , Jonathan J. Tyler
IPC分类号： G06F17/14 , G06F7/44 , G06F7/42
CPC分类号： G06F9/3885 , G06F9/30014 , G06F9/30018 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/30109 , G06F17/147 , G06F17/15
摘要： A method and apparatus for including in a processor instructions for performing integer transforms including multiply-add operations and horizontal-add operations on packed data. In one embodiment, a processor is coupled to a memory that stores a first packed byte data and a second packed byte data. The processor performs operations on said first packed byte data and said second packed byte data to generate a third packed data in response to receiving a multiply-add instruction. A plurality of the 16-bit data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed byte data. The processor adds together at least a first and a second 16-bit data element of the third packed data in response to receiving an horizontal-add instruction to generate a 16-bit result as one of a plurality of data elements of a fourth packed data.
摘要翻译：一种用于在处理器中包括用于执行整数变换的指令的方法和装置，包括对打包数据的乘法运算和水平加法运算。在一个实施例中，处理器耦合到存储第一打包字节数据和第二打包字节数据的存储器。处理器对所述第一打包字节数据和所述第二打包字节数据执行操作，以响应于接收到加法指令而产生第三打包数据。该第三打包数据中的多个16位数据元素存储对第一和第二打包字节数据中的数据元素执行加法运算的结果。处理器响应于接收到水平加法指令而将第三打包数据的至少第一和第二16位数据元素加在一起，以生成作为第四打包数据的多个数据元素之一的16位结果。

96. 发明申请

US20090113186A1 MICROCONTROLLER AND CONTROLLING SYSTEM 审中-公开
标题翻译：微控制器和控制系统
公开(公告)号：US20090113186A1
公开(公告)日：2009-04-30
申请号：US12262173
申请日：2008-10-30
申请人： Naoki KATO , Tetsuya Yamada , Fumio Arakawa , Hiromichi Yamada , Shigeru Oho , Makoto Ishikawa
发明人： Naoki KATO , Tetsuya Yamada , Fumio Arakawa , Hiromichi Yamada , Shigeru Oho , Makoto Ishikawa
IPC分类号： G06F9/22 , G06F7/42 , G06F3/00
CPC分类号： G06F9/30025 , G06F7/483 , G06F9/3001 , H03M7/24
摘要： A microcontroller and a controlling system having the same are provided, in which the increase in the program code for performing floating-point arithmetic, in particular, the increase in the amount of code due to a variable are suppressed, and the processing overhead for converting fixed-point data into floating-point data is reduced. The microcontroller includes a floating-point converter which inputs integer data and corresponding decimal point position data as fixed-point data and which converts the input data into floating-point data by acquiring a fraction part, an exponent part, and a sign of the floating type from the input data, and a floating-point arithmetic logic unit which receives the output of the floating-point converter and calculates the floating-point data. The floating-point converter acquires the exponent part by performing addition and subtraction of the decimal point position data and the shift amount of the fraction part to the integer data.
摘要翻译：提供了一种微控制器及其控制系统，其中用于执行浮点运算的程序代码的增加，特别是由于变量引起的代码量的增加被抑制，并且用于转换的处理开销定点数据进入浮点数据减少。微控制器包括一个浮点转换器，它将整数数据和对应的小数点位置数据作为定点数据输入，并通过获取浮点数的分数部分，指数部分和符号将输入数据转换为浮点数据从输入数据输入;以及浮点算术逻辑单元，接收浮点转换器的输出并计算浮点数据。浮点转换器通过对小数点位置数据和分数部分的移位量进行加，减来获取指数部分到整数数据。

97. 发明申请

US20080307030A1 GENERATION OF TEST CASES WITH RANGE CONSTRAINTS FOR FLOATING POINT ADD AND SUBTRACT INSTRUCTIONS 失效
标题翻译：产生用于浮点添加和放弃说明的范围限制的测试案例
公开(公告)号：US20080307030A1
公开(公告)日：2008-12-11
申请号：US12193396
申请日：2008-08-18
申请人： Abraham Ziv
发明人： Abraham Ziv
IPC分类号： G06F7/38 , G06F7/42
CPC分类号： G06F17/5022 , G06F7/483 , G06F7/49957
摘要： Methods, apparatus and systems are disclosed for the generation of range-constrained test cases for verification of designs of arithmetic floating point units. Given three ranges of floating point numbers Rx, Ry, Rz, a floating point operation (op), and a rounding-mode (round), three floating point numbers x, y, z are generated such that xεRx, yεRy, zεRz, and z=round ( x op y). Solutions are provided for add and subtract operations. Range constraints are imposed on the input operands and on the result operand of floating point add and subtract instructions to target corner cases when generating test cases for use in verification of floating point hardware.
摘要翻译：公开了用于生成用于验证算术浮点单元的设计的范围限制测试用例的方法，装置和系统。给定浮点数Rx，Ry，Rz，浮点运算（op）和舍入模式（round）三个浮点数x，y，z的三个范围，使得 xepsilonRx， yepsilonRy， zepsilonRz和 z = round（ x op y）。提供解决方案用于加减操作。在生成用于验证浮点硬件的测试用例时，对输入操作数和浮点加法和减法指令的结果操作数施加范围约束。

98. 发明授权

US07282983B2 Secure and fast calculating unit 有权
公开(公告)号：US07282983B2
公开(公告)日：2007-10-16
申请号：US11373829
申请日：2006-03-10
申请人： Norbert Janssen , Tanja Roemer
发明人： Norbert Janssen , Tanja Roemer
IPC分类号： G06F7/42
CPC分类号： G06F7/501 , G06F2207/3872 , G06F2207/7266
摘要： The calculating unit includes a dual rail input stage, a switching stage for a bit to be calculated and an output stage for an output bit, wherein the output stage provides a dual rail output. The switching stage is not implemented in dual rail technology but according to a “one-hot” realization. The switching stage includes at least one internal node which is, in the preparation mode according to a control signal on a control line from a control means, connected to a reference potential, while the node potential circuit for handling the internal node in the data mode is not active. Thus, an area-efficient, cross-current-reduced and reliable calculating unit is obtained, which may additionally be clocked at high speed, as a transition form a preparation mode to a data mode takes place without time-consuming discharge processes.

99. 发明申请

US20070192396A1 Packed add-subtract operation in a microprocessor 有权
标题翻译：在微处理器中进行加减法操作
公开(公告)号：US20070192396A1
公开(公告)日：2007-08-16
申请号：US11352711
申请日：2006-02-13
申请人： Ronny Pedersen , Erik Renno , Oyvind Strom
发明人： Ronny Pedersen , Erik Renno , Oyvind Strom
IPC分类号： G06F7/42 , G06F9/44
CPC分类号： G06F7/505 , G06F7/49921 , G06F9/30014 , G06F9/30036 , G06F9/3885 , G06F17/142 , G06F2207/382
摘要： A packed half-word addition and subtraction operation is performed by a microprocessor in parallel upon half-word operands obtained from designated top or bottom half-word locations of designated source registers of a register file and the sum and difference results of such operation are packed into respective top and bottom half-word locations of a designated destination register. The microprocessor includes an arithmetic-logic unit (ALU) with adder circuitry that can be selectively split into separate half-word adders that are independently selectable to perform either an addition operation or subtraction operation upon the selected half-word operands. The half-word adders of the ALU access the operands from source registers via a set of multiplexers that select among the top and bottom half-word locations. Operations with halving and saturation modifications to the sum and difference results may also be provided.
摘要翻译：一个微处理器的加字和减法操作由微处理器并行地由从寄存器文件的指定的源寄存器的指定的顶部或底部的半字位置获得的半字操作数并行，并且这些操作的和和差分结果被打包分配到指定目的地寄存器的相应顶部和底部半字位置。微处理器包括具有加法器电路的加法器电路的算术逻辑单元（ALU），其可选择性地分成独立的可选择的半字加法器，以对所选择的半字操作数执行加法运算或减法运算。 ALU的半字加法器通过一组多路复用器从源寄存器访问操作数，这些复用器在顶部和底部的半字位置之间进行选择。还可以提供对和差和差异结果的减半和饱和度修改的操作。

100. 发明授权

US07164290B2 Field programmable gate array logic unit and its cluster 有权
标题翻译：现场可编程门阵列逻辑单元及其集群
公开(公告)号：US07164290B2
公开(公告)日：2007-01-16
申请号：US10974107
申请日：2004-10-26
申请人： Guy Schlacter
发明人： Guy Schlacter
IPC分类号： H03K19/177 , G06F7/42
CPC分类号： H03K19/17736 , H03K19/17728
摘要： The embodiments of the present invention relate to the general area of the Field Programmable Gate Arrays, and, in particular to the architecture and the structure of the building blocks of the Field Programmable Gate Arrays. The proposed logic units, as separate units or cluster of units, which are mainly comprised of look-up tables, multiplexers, and a latch, implement functions such as addition, subtraction, multiplication, and can perform as shift registers, finite state machines, multiplexers, accumulators, counters, multi-level random logic, and look-up tables, among other functions. Having two outputs, the embodiments of the logic unit can operate in split-mode and perform two separate logic and/or arithmetic functions at the same time. Clusters of the proposed logic units, which utilize local interconnections instead of traditional routing channels, add to efficiency, speed, and reduce required real estate.
摘要翻译：本发明的实施例涉及现场可编程门阵列的一般区域，特别涉及现场可编程门阵列的结构单元的架构和结构。所提出的逻辑单元，作为主要由查找表，多路复用器和锁存器组成的分离单元或单元组，实现加法，减法，乘法等功能，并且可以作为移位寄存器，有限状态机，多路复用器，累加器，计数器，多级随机逻辑和查找表等功能。具有两个输出，逻辑单元的实施例可以在分离模式下操作并且同时执行两个单独的逻辑和/或算术功能。所提出的逻辑单元的集群利用局部互连而不是传统的路由信道来增加效率，速度和减少所需的房地产。

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