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91. 发明授权

US09337785B1 High-linearity, ultra-wideband multi-stage track-and-hold amplifier with shunted source-follower first-stage 有权
标题翻译：具有分流源极跟随器第一级的高线性，超宽带多级跟踪保持放大器
公开(公告)号：US09337785B1
公开(公告)日：2016-05-10
申请号：US14179503
申请日：2014-02-12
申请人： SEMTECH CORPORATION
发明人： Sandeep Louis D'Souza , Kenneth Colin Dyer , Raghava Manas Bachu
IPC分类号： G11C27/02 , H03F3/16
CPC分类号： H03F3/16 , G11C27/02 , H03F2200/297 , H03F2200/411
摘要： Examples are provided for a multi-stage track-and-hold amplifier (THA). The multi-stage THA may include a first stage, a second stage, and a third stage. The first stage may be coupled to an input signal and configured to sample the input signal. The second stage may be coupled to the first stage and may include a buffer circuit. The third stage may be coupled to the second stage and can include a bootstrapped THA. The first stage may further include a shunted source-follower circuit and a switched source-follower circuit. The shunted source-follower circuit may include a first switch that can be operable to couple an output node of the shunted source-follower circuit to ground potential.
摘要翻译：为多级跟踪保持放大器（THA）提供了实例。多级THA可以包括第一级，第二级和第三级。第一级可以耦合到输入信号并被配置为对输入信号进行采样。第二级可以耦合到第一级，并且可以包括缓冲器电路。第三级可以耦合到第二级并且可以包括引导的THA。第一级还可以包括分流源跟随器电路和开关源跟随器电路。分流源跟随器电路可以包括第一开关，其可操作以将分流源跟随器电路的输出节点耦合到地电位。

92. 发明授权

US09325299B2 Detecting method and device for suppressing interference of low-frequency noise 有权
标题翻译：用于抑制低频噪声干扰的检测方法和装置
公开(公告)号：US09325299B2
公开(公告)日：2016-04-26
申请号：US13889702
申请日：2013-05-08
申请人： EGALAX—EMPIA TECHNOLOGY INC.
发明人： Chin-Fu Chang , Shang-Tai Yeh , Guang-Huei Lin , Po-Chuan Lin
IPC分类号： H03K3/013 , H04B1/10 , G06F3/044 , G11C27/02 , G06F3/041 , G06F3/0354
CPC分类号： H03K3/013 , G06F3/03545 , G06F3/0418 , G06F3/044 , G11C27/026
摘要： The invention, upon receiving an input signal, sums the absolute values of the difference of each pair of values adjacent to each other within a series of detected signal values to suppress the interference of low-frequency noise. Furthermore, the invention sums the absolute values of the moving averages of the differences of each pair of values adjacent to each other within a series of detected signal values to suppress both the interference of low-frequency noise and the interference of high-frequency noise. No synchronization with the input signal is necessary. The detection can be started at any phase of the input signal.
摘要翻译：本发明在接收到输入信号后，将一系列检测信号值中的每对相邻值的差的绝对值求和，以抑制低频噪声的干扰。此外，本发明将一系列检测信号值中的彼此相邻的每对值的差的移动平均值的绝对值相加，以抑制低频噪声的干扰和高频噪声的干扰。不需要与输入信号同步。可以在输入信号的任何阶段开始检测。

93. 发明授权

US09318999B2 Sampling mixer circuit and receiver 有权
标题翻译：采样混频电路和接收机
公开(公告)号：US09318999B2
公开(公告)日：2016-04-19
申请号：US14368770
申请日：2013-01-22
申请人： Panasonic Corporation
发明人： Yohei Morishita
IPC分类号： H03D7/16 , H04B1/26 , H03D7/00 , H03D7/12 , H03D7/18 , G11C19/00 , G11C27/02 , H03H19/00 , H04B7/08 , H04L25/08 , H03H15/00 , H03D7/14
CPC分类号： H03D7/00 , G11C19/00 , G11C27/024 , H03D7/125 , H03D7/1441 , H03D7/18 , H03D2200/0062 , H03D2200/0068 , H03H15/00 , H03H19/004 , H04B7/0885 , H04L25/08
摘要： The sampling mixer circuit comprises: a clock generating circuit that outputs four-phase control signals the periods of which are in accordance with the carrier frequency of an input signal and the phases of which are different from one another; a voltage-to-current converting circuit that converts a voltage signal based on the input signal to a current signal; four-system charge sharing circuits in which the current signal as converted is input to a plurality of capacitors in accordance with the different phases based on the four-phase control signals and in which charges are exchanged among the plurality of capacitors; and a phase-to-phase capacitor that is selectively connected, on the basis of the four-phase control signals, to the respective ones of nodes, which are other than the input nodes of the current signal, in the four-system charge sharing circuits.
摘要翻译：采样混频器电路包括：时钟发生电路，其输出其周期与输入信号的载波频率和相位彼此不同的四相控制信号; 电压 - 电流转换电路，其将基于所述输入信号的电压信号转换为电流信号; 四变系统电荷共享电路，其中根据四相控制信号将转换的电流信号输入到多个电容器，并且其中电荷在多个电容器之间交换; 以及基于四相控制信号在四系统电荷共享中被选择性地连接到不同于当前信号的输入节点的各个节点的相电容器电路。

94. 发明申请

US20160099269A1 Fully Differential Output Swing for Analog Array Based Charge Mode Readout used in a CMOS Image Sensor 有权
标题翻译：用于CMOS图像传感器中的基于模拟阵列的充电模式读出的全差分输出摆幅
公开(公告)号：US20160099269A1
公开(公告)日：2016-04-07
申请号：US14875511
申请日：2015-10-05
申请人： Forza Silicon Corporation
发明人： Steven Huang
IPC分类号： H01L27/146 , G11C27/02 , H03F3/45
CPC分类号： G11C27/026 , H03F3/45475 , H03F2203/45134 , H03F2203/45156 , H03F2203/45171 , H03F2203/45514 , H03F2203/45551 , H04N5/378
摘要： Disclosed herein are novel charge mode readout circuits and associated methods of signal processing. The devices and methods of the invention allow for the improved processing of stored signals by a charge mode readout amplifier, wherein the readout level may be shifted to a desired range and wherein a fully differential output swing may be imparted. The invention advantageously employs a single pair of capacitors to serve the dual roles of modulating amplifier gain and level shifting the output.
摘要翻译：这里公开了新颖的充电模式读出电路和相关的信号处理方法。本发明的装置和方法允许通过充电模式读出放大器对存储的信号的改进处理，其中读出电平可以移动到期望的范围，并且其中可以赋予全差分输出摆幅。本发明有利地采用单对电容器来实现调制放大器增益和电平移位输出的双重作用。

95. 发明授权

US09280168B2 Low-power, high-accuracy current reference for highly distributed current references for cross point memory 有权
标题翻译：用于交叉点存储器的高分布电流参考的低功耗，高精度电流参考
公开(公告)号：US09280168B2
公开(公告)日：2016-03-08
申请号：US13853813
申请日：2013-03-29
申请人： Intel Corporation
发明人： Matthew G. Dayley , Yadhu Vamshi S. Vancha
IPC分类号： G06G7/28 , G05F3/08 , G11C7/14 , G11C27/02
CPC分类号： G11C5/147 , G05F3/08 , G05F3/26 , G11C7/10 , G11C7/14 , G11C27/02 , G11C27/024
摘要： A highly distributed current reference for a solid-state memory comprises a centrally located current digital-to-analog converter (IDAC) and a plurality of remotely located tile current references. The IDAC comprises a first active device that generates a reference current, and a device that forms a first source degeneration resistance for the first active device. The IDAC outputs a voltage signal that represents a magnitude of the reference current. A remotely located tile current reference comprises a second active device and a device that forms a second source degeneration resistance for the second active device. The source degeneration resistances and capacitance coupled to the voltage signal output from the IDAC compensate for current, temperature, supply and process variations.
摘要翻译：用于固态存储器的高分布式电流参考包括位于中心的当前数模转换器（IDAC）和多个远程定位的瓦片电流参考。 IDAC包括产生参考电流的第一有源器件和形成第一有源器件的第一源极退变电阻的器件。 IDAC输出表示参考电流大小的电压信号。远程定位的瓦片电流参考包括第二有源器件和为第二有源器件形成第二源极变性电阻的器件。耦合到从IDAC输出的电压信号的源极退化电阻和电容补偿了电流，温度，电源和工艺变化。

96. 发明授权

US09263115B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09263115B2
公开(公告)日：2016-02-16
申请号：US14476433
申请日：2014-09-03
申请人： Micron Technology, Inc.
发明人： Kazuhiko Kajigaya
IPC分类号： G11C11/16 , G11C13/00 , G11C27/02
CPC分类号： G11C11/1675 , G11C11/1653 , G11C11/1659 , G11C11/1673 , G11C11/1693 , G11C13/0061 , G11C13/0069 , G11C27/02 , G11C2013/0092
摘要： A method includes measuring a first pulse width of a resistance variable memory cell coupled between a first terminal and a second terminal, the first pulse width including a period from starting a first data writing of the resistance variable memory cell by applying a voltage between the first and second terminals to ending the first data writing of the resistance variable memory cell, and measuring a second pulse width of the resistance variable memory cell coupled between the first and the second terminal. The method includes setting longer one of the first and second pulse widths in a first storage area as a pulse width to be used in program.
摘要翻译：一种方法包括测量耦合在第一端子和第二端子之间的电阻可变存储单元的第一脉冲宽度，所述第一脉冲宽度包括从所述电阻可变存储单元的第一数据写入开始的时段，以及第二端子，用于结束电阻可变存储单元的第一数据写入，以及测量耦合在第一和第二端子之间的电阻变量存储单元的第二脉冲宽度。该方法包括将第一存储区域中的第一和第二脉冲宽度的较长时间设置为要在程序中使用的脉冲宽度。

97. 发明授权

US09245649B2 Resistive switching sample and hold 有权
标题翻译：电阻式开关采样和保持
公开(公告)号：US09245649B2
公开(公告)日：2016-01-26
申请号：US14108877
申请日：2013-12-17
申请人： Intermolecular Inc.
发明人： Federico Nardi , Ryan C. Clarke , Yun Wang
IPC分类号： G11C27/02 , G11C13/00
CPC分类号： G11C27/02 , G11C13/0002 , G11C13/0007
摘要： A nonvolatile sample and hold circuit can include a resistive switching circuit, a sample circuit, a reset circuit, and a converter circuit. The resistive switching circuit can be operable to accept an input voltage Vg, and provide a resistance response Rrs that corresponds to the input signal Vg. The sampling circuit can be operable to sample an input signal such as an input voltage Vin, to provide a sampled voltage Vg. The reset circuit can be operable to reset the resistive switching circuit to a high resistance state. The converter circuit can be operable to convert the resistive switching circuit to an output voltage. The novel sample and hold circuit can have no issues related to charge injection, no settling time and instantaneous sampling time, together with potentially infinite hold time.
摘要翻译：非易失性采样和保持电路可以包括电阻开关电路，采样电路，复位电路和转换器电路。电阻开关电路可操作以接受输入电压Vg，并且提供对应于输入信号Vg的电阻响应Rrs。采样电路可以用于对诸如输入电压Vin的输入信号进行采样，以提供采样电压Vg。复位电路可以用于将电阻式开关电路复位到高电阻状态。转换器电路可操作以将电阻开关电路转换成输出电压。新颖的采样和保持电路可以没有与电荷注入相关的问题，无需建立时间和瞬间采样时间，以及潜在的无限延时时间。

98. 发明申请

US20150332785A1 CONFIGURING SIGNAL-PROCESSING SYSTEMS 有权
标题翻译：配置信号处理系统
公开(公告)号：US20150332785A1
公开(公告)日：2015-11-19
申请号：US14712539
申请日：2015-05-14
申请人： LINEAR TECHNOLOGY CORPORATION
发明人： Jesper Steensgaard-Madsen , Manideep Gande
IPC分类号： G11C27/02 , H03M1/12
CPC分类号： G11C27/024 , G06F17/5031 , G06F17/5054 , G06F2217/84 , H03M1/12 , H03M1/1255 , H03M1/126 , H03M5/02 , Y02T10/82
摘要： A configurable signal-processing circuit may provide a plurality of selectable signal-processing operations. The configurable signal-processing circuit may have a configuration circuit that provides a configuration code that selects a first signal-processing operation from the plurality of selectable signal-processing operations based on a timing pattern for evaluating an input signal and outputting an output signal.
摘要翻译：可配置信号处理电路可以提供多个可选择的信号处理操作。可配置信号处理电路可以具有配置电路，该配置电路基于用于评估输入信号并输出输出信号的定时模式，提供从多个可选信号处理操作中选择第一信号处理操作的配置码。

99. 发明授权

US09159450B2 Sampling circuit for measuring reflected voltage of transformer for power converter operated in DCM and CCM 有权
标题翻译：用于测量DCM和CCM中功率变换器变压器反射电压的采样电路
公开(公告)号：US09159450B2
公开(公告)日：2015-10-13
申请号：US13847567
申请日：2013-03-20
申请人： SYSTEM GENERAL CORP.
发明人： Li Lin , Yue-Hong Tang , Chin-Yen Lin , Jung-Sheng Chen , Ta-Yung Yang
IPC分类号： G11C27/02 , H03K5/00 , H02M3/335
CPC分类号： G11C27/02 , G11C27/026 , H02M3/33523
摘要： A sampling circuit of the power converter according to the present invention comprises an amplifier circuit receiving a reflected voltage for generating a first signal. A first switch and a first capacitor are utilized to generate a second signal in response to the reflected voltage. A sample-signal circuit generates a sample signal in response to the disable of a switching signal. The switching signal is generated in accordance with a feedback signal for regulating an output of the power converter. The feedback signal is generated in accordance with the second signal. The sample signal is utilized to control the first switch for sampling the reflected voltage. The sample signal is disabled once the first signal is lower than the second signal. The sampling circuit precisely samples the reflected voltage of the transformer of the power converter for regulating the output of the power converter.
摘要翻译：根据本发明的功率转换器的采样电路包括接收用于产生第一信号的反射电压的放大器电路。利用第一开关和第一电容器来响应于反射电压产生第二信号。采样信号电路响应于开关信号的禁用而产生采样信号。根据用于调节功率转换器的输出的反馈信号产生开关信号。反馈信号根据第二信号产生。采样信号用于控制第一开关以对反射电压进行采样。第一个信号低于第二个信号时，采样信号被禁止。采样电路对功率转换器的变压器的反射电压进行精确采样，以调节功率转换器的输出。

100. 发明授权

US09154089B2 Buffer amplifier circuit 有权
标题翻译：缓冲放大器电路
公开(公告)号：US09154089B2
公开(公告)日：2015-10-06
申请号：US14210958
申请日：2014-03-14
申请人： Hae-Seung Lee
发明人： Hae-Seung Lee
IPC分类号： H03F3/16 , G11C27/02 , H03H19/00 , H03M1/12 , G11C13/02 , H03F3/00
CPC分类号： H03F3/16 , G11C27/024 , H03F3/005 , H03F3/62 , H03F3/70 , H03F2200/156 , H03F2200/159 , H03F2200/357 , H03F2200/42 , H03H19/004 , H03M1/1245 , H03M1/468
摘要： Amplifier circuits implemented with a buffer amplifier with a voltage gain substantially equal to one. In one example, a continuous-time amplifier is implemented by applying the input source across the input and the output terminals of the buffer amplifier. In another example, a discrete-time amplifier is implemented. During the sampling phase at least one input voltage is sampled, and during the transfer phase at least one capacitor is coupled across the input and the output terminals of a buffer amplifier to effectuate an amplification.
摘要翻译：具有电压增益基本上等于1的缓冲放大器实现的放大器电路。在一个示例中，通过在缓冲放大器的输入端和输出端上施加输入源来实现连续时间放大器。在另一示例中，实现了离散时间放大器。在采样阶段期间，对至少一个输入电压进行采样，并且在传输阶段期间，至少一个电容器跨越缓冲放大器的输入端和输出端耦合以实现放大。

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