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1. 发明申请

US20190012287A1 MICROCONTROLLER PROGRAMMABLE SYSTEM ON A CHIP 审中-公开
公开(公告)号：US20190012287A1
公开(公告)日：2019-01-10
申请号：US15995409
申请日：2018-06-01
申请人： Cypress Semiconductor Corporation
发明人： Warren S. Snyder , Monte Mar
IPC分类号： G06F13/40 , H03K3/0231 , H03K3/014 , G06F1/08 , G06F1/32 , H03K3/012 , H03H19/00 , H03B5/36 , H03B5/32 , G11C16/10 , G06G7/06 , G06F15/78 , G06F13/36 , G06F13/10 , G06F9/445 , G06F13/42 , G05B19/042
CPC分类号： G06F13/4068 , G05B19/0423 , G05B2219/25033 , G06F1/08 , G06F1/32 , G06F9/44505 , G06F13/102 , G06F13/36 , G06F13/40 , G06F13/4282 , G06F15/7817 , G06F15/7867 , G06G7/06 , G11C16/10 , H03B5/32 , H03B5/364 , H03H19/004 , H03K3/012 , H03K3/014 , H03K3/02315
摘要： Embodiments of the present invention are directed to a microcontroller device having a microprocessor, programmable memory components, and programmable analog and digital blocks. The programmable analog and digital blocks are configurable based on programming information stored in the memory components. Programmable interconnect logic, also programmable from the memory components, is used to couple the programmable analog and digital blocks as needed. The advanced microcontroller design also includes programmable input/output blocks for coupling selected signals to external pins. The memory components also include user programs that the embedded microprocessor executes. These programs may include instructions for programming the digital and analog blocks “on-the-fly,” e.g., dynamically. In one implementation, there are a plurality of programmable digital blocks and a plurality of programmable analog blocks.

2. 发明申请

US20180159549A1 Input Circuit for a Dynamic Comparator 审中-公开
公开(公告)号：US20180159549A1
公开(公告)日：2018-06-07
申请号：US15826668
申请日：2017-11-29
申请人： IMEC VZW
发明人： Ewout Martens , Benjamin Hershberg , Jan Craninckx
IPC分类号： H03M1/38 , H03K5/24 , H03H19/00
CPC分类号： H03M1/38 , H03F3/45179 , H03H19/004 , H03K5/2481 , H03M1/361
摘要： The present disclosure relates to an input circuit comprising positive and negative branches, each branch comprising a transistor arranged for receiving an input voltage at its gate terminal and a first fixed voltage at its drain terminal via a first switch characterized in that the source terminal of the transistor in each of the positive branch and the negative branch is connectable via a second switch to a first plate of a first capacitor in the positive branch and of a second capacitor in the negative branch, respectively, with a second plate of the first capacitor and of the second capacitor being connected to a second fixed voltage and the input circuit further being arranged for receiving a first reset voltage on the first plate of the first capacitor in the positive branch and a second reset voltage on the first plate of the second capacitor in the negative branch.

3. 发明授权

US09929760B2 Ultra-low-power RF receiver frontend with tunable matching networks 有权
公开(公告)号：US09929760B2
公开(公告)日：2018-03-27
申请号：US15098784
申请日：2016-04-14
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Hong-Lin Chu , Hsieh-Hung Hsieh , Tzu-Jin Yeh
IPC分类号： H04B1/18 , H04B1/10 , H03F3/193 , H03H19/00 , H03F3/45
CPC分类号： H04B1/1036 , H03F1/565 , H03F3/193 , H03F3/3022 , H03F3/45071 , H03F2200/165 , H03F2200/171 , H03F2200/213 , H03F2200/222 , H03F2200/294 , H03F2200/336 , H03F2200/451 , H03F2203/30031 , H03F2203/45288 , H03H19/004
摘要： A tunable matching circuit for use with ultra-low power RF receivers is described to support a variety of RF communication bands. A switched-capacitor array and a switched-resistor array are used to adjust the input impedance presented by the operating characteristics of transistors in an ultra-low-power mode. An RF sensor may be used to monitor performance of the tunable matching circuit and thereby determine optimal setting of the digital control word that drives the switched-capacitor array and switched-resistor array. An effective match over a significant bandwidth is achievable. The optimal matching configuration may be updated at any time to adjust to changing operating conditions. Memory may be used to store the optimal matching configurations of the switched capacitor array and switched resistor array.

4. 发明申请

US20180019717A1 PHYSICAL QUANTITY DETECTION CIRCUIT, PHYSICAL QUANTITY DETECTION DEVICE, ELECTRONIC APPARATUS, AND VEHICLE 审中-公开
公开(公告)号：US20180019717A1
公开(公告)日：2018-01-18
申请号：US15646376
申请日：2017-07-11
申请人： Seiko Epson Corporation
发明人： Noriyuki MURASHIMA
IPC分类号： H03F3/387 , H03F3/45 , G01D5/241 , G11C27/02 , H03H7/01 , H03G3/20
CPC分类号： H03F3/387 , G01D5/2417 , G01D21/00 , G11C27/02 , G11C27/026 , H03F3/45475 , H03F2203/45514 , H03G1/0094 , H03G3/001 , H03G3/20 , H03H7/0138 , H03H19/004
摘要： A physical quantity detection device includes a switched capacitor filter circuit having a first sample-and-hold circuit adapted to sample and hold a first signal, which is based on an output signal of a physical quantity detection element, an amplifier circuit to which an output signal of the first sample-and-hold circuit is input, and a first switched capacitor circuit to which a first output signal of the amplifier circuit is input, wherein an output signal of the first switched capacitor circuit is input to the amplifier circuit, and an A/D conversion circuit adapted to perform an A/D conversion on an output signal of the switched capacitor filter circuit.

5. 发明授权

US09685933B2 Notch filter for ripple reduction 有权
公开(公告)号：US09685933B2
公开(公告)日：2017-06-20
申请号：US14669863
申请日：2015-03-26
申请人： Linear Technology Corporation
发明人： Jeremy H. Wong , Joseph G. Petrofsky
IPC分类号： H03F1/02 , H03H19/00 , H03F3/45 , H02M1/15 , H02M3/07
CPC分类号： H03H19/004 , H02M1/15 , H02M3/07 , H03F3/45475
摘要： A notch filter is controlled synchronously with a chopper to filter out chopping ripple. In one embodiment, the notch filter is coupled to the differential output of the chopper and includes a sampling capacitor, a hold capacitor, and a second set of switches between the sampling capacitor and the hold capacitor. The second set of switches is temporarily closed once per chopper switching cycle to transfer charge from the sampling capacitor to the hold capacitor such that the ripple from the chopper is not transferred to the hold capacitor. The voltage across the hold capacitor may be coupled to any other circuit, such as to the differential inputs of an amplifier.

6. 发明授权

US09590593B2 MOS capacitors with head-to-head fingers and methods of forming the same 有权
标题翻译：具有头对头手指的MOS电容器及其形成方法
公开(公告)号：US09590593B2
公开(公告)日：2017-03-07
申请号：US15085720
申请日：2016-03-30
申请人： TDK Corporation
发明人： Rien Gahlsdorf , Jianwen Bao
IPC分类号： G05F1/10 , H03H19/00 , H01L49/02 , G05F3/20 , G05F3/24
CPC分类号： H03H19/004 , G05F3/205 , G05F3/24 , H01L28/40 , H01L29/66189 , H01L29/94 , H03H7/0153 , H03H7/12 , H03H7/40 , H03H7/463 , H03H2250/00
摘要： A capacitor structure is described. The capacitor structure includes a substrate, a plurality of source/drain regions, a first plurality gates, and a second plurality of gates. The plurality of source/drain regions is formed in the substrate. The first and second plurality of gates is formed above the substrate. Each gate of the first and second plurality of gates has a gate width. The gate widths are configured to be less than an active area width and each gate of the first and second plurality of gates is formed between a pair of the source/drain regions of the plurality of source/drain regions. And, each gate of the first plurality of gates is configured to be in line with a corresponding gate of the second plurality of gates to form a head-to-head gate configuration.
摘要翻译：描述电容器结构。电容器结构包括衬底，多个源极/漏极区，第一多个栅极和第二多个栅极。在衬底中形成多个源极/漏极区域。第一和第二多个栅极形成在衬底上。第一和第二多个栅极的每个栅极具有栅极宽度。栅极宽度被配置为小于有效面积宽度，并且第一和第二多个栅极的每个栅极形成在多个源极/漏极区域的一对源极/漏极区域之间。并且，第一多个栅极的每个栅极被配置为与第二多个栅极的对应栅极对齐以形成头对头栅极配置。

7. 发明授权

US09577608B2 Discrete time lowpass filter 有权
标题翻译：离散时间低通滤波器
公开(公告)号：US09577608B2
公开(公告)日：2017-02-21
申请号：US12541834
申请日：2009-08-14
申请人： Russell John Fagg , Joseph Patrick Burke
发明人： Russell John Fagg , Joseph Patrick Burke
IPC分类号： G06F17/17 , H03H19/00 , H03H15/00 , H03H17/06
CPC分类号： H03H19/004 , H03H15/023 , H03H17/0657 , H03H17/0664
摘要： A discrete time (DT) lowpass filter having various advantages is described. In an exemplary design, the DT lowpass filter includes a decimating DT filter (which may include a passive DT FIR filter and/or a passive DT IIR filter) and an active DT filter. The decimating DT filter receives a first DT signal at a first sample rate, filters and decimates the first DT signal by a factor of N, and provides a second DT signal at a second sample rate lower than the first sample rate. N may be greater than one. The active DT filter filters the second DT signal and provides a third DT signal at the second sample rate. A sampler samples a continuous time signal and provides the first DT signal. The sampler may further double the voltage of the first DT signal relative to the voltage of the continuous time signal.
摘要翻译：描述了具有各种优点的离散时间（DT）低通滤波器。在示例性设计中，DT低通滤波器包括抽取DT滤波器（其可以包括无源DT FIR滤波器和/或无源DT IIR滤波器）和有源DT滤波器。抽取DT滤波器以第一采样速率接收第一DT信号，以N因子对第一DT信号进行滤波和抽取，并以低于第一采样率的第二采样速率提供第二DT信号。 N可能大于1。有源DT滤波器对第二DT信号进行滤波，并以第二采样率提供第三DT信号。采样器采样连续时间信号并提供第一个DT信号。采样器可以相对于连续时间信号的电压进一步使第一DT信号的电压加倍。

8. 发明授权

US09473074B1 Chopper stabilized amplifier with synchronous switched capacitor noise filtering 有权
标题翻译：具有同步开关电容噪声滤波的斩波稳压放大器
公开(公告)号：US09473074B1
公开(公告)日：2016-10-18
申请号：US14852921
申请日：2015-09-14
申请人： IXYS Corporation
发明人： Eric Blom
IPC分类号： H03F1/02 , H03F1/26 , H03F3/393
CPC分类号： H03F3/393 , H03F1/26 , H03F3/45192 , H03F3/45475 , H03F2200/171 , H03F2200/271 , H03F2200/411 , H03F2200/555 , H03F2203/45514 , H03H19/004
摘要： A chopper stabilized amplifier with synchronous switched capacitor noise filtering is disclosed. In an exemplary embodiment, an apparatus includes a chopper amplifier having an input that receives an input signal and an output that outputs an amplified signal. The chopper amplifier includes an input chopping circuit and an output chopping circuit, where the input and output chopping circuits operate in response to a chop clock. The apparatus also includes a switched capacitor filter having an input that receives the amplified signal and an output that outputs a filtered signal. The switched capacitor filter operates in response to a filter clock. The apparatus also includes a filter timing adjuster that receives a reference voltage and adjusts a phase of the filter clock with respect to the chop clock to reduce chopper noise on that reference voltage.
摘要翻译：公开了具有同步开关电容噪声滤波的斩波稳定放大器。在示例性实施例中，一种装置包括具有接收输入信号的输入和输出放大信号的输出的斩波放大器。斩波放大器包括输入斩波电路和输出斩波电路，其中输入和输出斩波电路响应于斩波时钟而工作。该装置还包括具有接收放大信号的输入端和输出滤波信号的输出的开关电容滤波器。开关电容滤波器响应于滤波器时钟而工作。该装置还包括滤波器定时调节器，其接收参考电压并相对于斩波时钟调节滤波器时钟的相位，以减小该参考电压的斩波噪声。

9. 发明申请

US20160294368A1 MOS CAPACITORS WITH HEAD-TO-HEAD FINGERS AND METHODS OF FORMING THE SAME 有权
标题翻译：具有头对头指状物的MOS电容器及其形成方法
公开(公告)号：US20160294368A1
公开(公告)日：2016-10-06
申请号：US15085720
申请日：2016-03-30
申请人： TDK Corporation
发明人： Jim Bao , Rien Gahlsdorf
IPC分类号： H03H19/00 , G05F3/20 , G05F3/24 , H01L49/02
CPC分类号： H03H19/004 , G05F3/205 , G05F3/24 , H01L28/40 , H01L29/66189 , H01L29/94 , H03H7/0153 , H03H7/12 , H03H7/40 , H03H7/463 , H03H2250/00
摘要： A capacitor structure is described. The capacitor structure includes a substrate, a plurality of source/drain regions, a first plurality gates, and a second plurality of gates. The plurality of source/drain regions is formed in the substrate. The first and second plurality of gates is formed above the substrate. Each gate of the first and second plurality of gates has a gate width. The gate widths are configured to be less than an active area width and each gate of the first and second plurality of gates is formed between a pair of the source/drain regions of the plurality of source/drain regions. And, each gate of the first plurality of gates is configured to be in line with a corresponding gate of the second plurality of gates to form a head-to-head gate configuration.
摘要翻译：描述电容器结构。电容器结构包括衬底，多个源极/漏极区，第一多个栅极和第二多个栅极。在衬底中形成多个源极/漏极区域。第一和第二多个栅极形成在衬底上。第一和第二多个栅极的每个栅极具有栅极宽度。栅极宽度被配置为小于有效面积宽度，并且第一和第二多个栅极的每个栅极形成在多个源极/漏极区域的一对源极/漏极区域之间。并且，第一多个栅极的每个栅极被配置为与第二多个栅极的对应栅极对齐以形成头对头栅极配置。

10. 发明申请

US20160293778A1 MOS CAPACITORS FLOW TYPE DEVICES AND METHODS OF FORMING THE SAME 有权
标题翻译： MOS电容器流动型器件及其形成方法
公开(公告)号：US20160293778A1
公开(公告)日：2016-10-06
申请号：US15085788
申请日：2016-03-30
申请人： TDK Corporation
发明人： Jim Bao , Rien Gahlsdorf
IPC分类号： H01L29/94 , G05F3/24 , H03H19/00 , H01L27/08 , H01L29/66 , G05F3/20 , H01L27/12
CPC分类号： H01L29/94 , G05F3/205 , G05F3/24 , H01L27/0811 , H01L27/1203 , H01L29/66189 , H01L29/93 , H03H7/0153 , H03H7/12 , H03H7/40 , H03H7/463 , H03H19/004 , H03H2250/00
摘要： A capacitor structure is described. The capacitor structure includes a substrate; a source/drain region formed in the substrate to form an active area, the active area having an active area width; and at least two gates formed above the substrate. The at least two gates having a gate width. The gate width is configured to be less than the active area width. And, the at least two gates are formed such that the source/drain region is between the two gates to form at least one channel between the two gates.
摘要翻译：描述电容器结构。电容器结构包括基板; 源极/漏极区，形成在所述衬底中以形成有源区，所述有源区具有有效面积宽度; 并且至少两个栅极形成在衬底上。所述至少两个门具有门宽度。栅极宽度被配置为小于有效区域宽度。并且，至少两个栅极形成为使得源极/漏极区域在两个栅极之间以在两个栅极之间形成至少一个沟道。

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