专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

91. 发明授权

US07994538B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07994538B2
公开(公告)日：2011-08-09
申请号：US12205074
申请日：2008-09-05
申请人： Young Suk Kim
发明人： Young Suk Kim
IPC分类号： H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109
CPC分类号： H01L29/66636 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/6653 , H01L29/6659 , H01L29/7834 , H01L29/7848
摘要： A semiconductor device to which a stress technique is applied and in which a leakage current caused by silicidation can be suppressed. A gate electrode is formed over an element region defined by an isolation region formed in a semiconductor substrate with a gate insulating film between. Extension regions and source/drain regions are formed in the element region on both sides of the gate electrode. In addition, a semiconductor layer which differs from the semiconductor substrate in lattice constant is formed apart from at least part of the isolation region. By doing so, the formation of a spike near the isolation region is suppressed even if a silicide layer is formed. Accordingly, a leakage current caused by such a spike can be suppressed.
摘要翻译：应用技术的半导体器件可以抑制由硅化产生的漏电流。栅极电极形成在由形成在半导体衬底中的隔离区限定的元件区域上，栅绝缘膜在其间。延伸区域和源极/漏极区域形成在栅电极两侧的元件区域中。此外，与晶格常数的半导体衬底不同的半导体层与隔离区域的至少一部分分开形成。通过这样做，即使形成硅化物层，也抑制了隔离区附近的尖峰的形成。因此，可以抑制由这种尖峰引起的漏电流。

92. 发明授权

US07960755B2 Strained quantum-well semiconductor devices 失效
标题翻译：应变量子阱半导体器件
公开(公告)号：US07960755B2
公开(公告)日：2011-06-14
申请号：US10577938
申请日：2004-11-08
申请人： Timothy J Phillips , Timothy Ashley
发明人： Timothy J Phillips , Timothy Ashley
IPC分类号： H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109
CPC分类号： H01L29/1004 , H01L27/0605 , H01L29/7373 , H01L29/7378 , H01L29/7783 , H01L29/7784
摘要： In a transistor in which the majority carriers are holes, at least one narrow bandgap region or layer is doped p-type or contains an excess of holes and is subject to compressive mechanical strain, whereby hole mobility may be significantly increased. In a p-channel quantum well FET, the quantum well InSb well p-type layer 5 (modulation or directly doped) lies between In1-xAlxSb layers 4, 6 where x is of a value sufficient to induce strain in layer 5 to an extent that light and heavy holes are separated by much more than kT. Transistors falling within the invention, including bipolar pnp devices, may be used with their more conventional electron majority carriers counterparts in complementary logic circuitry.
摘要翻译：在其中多数载流子为空穴的晶体管中，至少一个窄带隙区域或层被掺杂为p型或含有过量的孔，并且经受压缩机械应变，从而可以显着增加空穴迁移率。在p沟道量子阱FET中，量子阱InSb阱p型层5（调制或直接掺杂）位于In1-xAlxSb层4,6之间，其中x具有足以在层5中诱导应变的值那个轻而重的洞比kT多得多。落入本发明内的晶体管，包括双极性pnp器件，可以与互补逻辑电路中更常规的电子多数载流子对应使用。

93. 发明授权

US07948009B2 Nitride semiconductor epitaxial wafer and nitride semiconductor device 有权
标题翻译：氮化物半导体外延晶片和氮化物半导体器件
公开(公告)号：US07948009B2
公开(公告)日：2011-05-24
申请号：US12382481
申请日：2009-03-17
申请人： Yoshihiko Moriya , Takeshi Tanaka , Yohei Otoki , Masae Sahara
发明人： Yoshihiko Moriya , Takeshi Tanaka , Yohei Otoki , Masae Sahara
IPC分类号： H01L31/072 , H01L31/109 , H01L31/0328 , H01L31/0336
CPC分类号： H01L29/2003 , H01L29/1075 , H01L29/7786
摘要： A nitride semiconductor epitaxial wafer includes a growth substrate including a surface for growing a nitride semiconductor thereon, a first structure layer formed on the growth substrate, a dislocation propagation direction changing layer formed on the first structure layer for changing a propagation direction of a dislocation propagated in the first structure layer into a lateral direction, a second structure layer formed on the dislocation propagation direction changing layer, and a buffer layer formed on the second structure layer for changing a propagation direction of a dislocation propagated in the second structure layer.
摘要翻译：氮化物半导体外延晶片包括生长衬底，其包括用于在其上生长氮化物半导体的表面，形成在生长衬底上的第一结构层，形成在第一结构层上的位错传播方向改变层，用于改变传播的位错的传播方向在第一结构层中形成横向，形成在位错传播方向改变层上的第二结构层，以及形成在第二结构层上的缓冲层，用于改变在第二结构层中传播的位错的传播方向。

94. 发明授权

US07915645B2 Monolithic vertically integrated composite group III-V and group IV semiconductor device and method for fabricating same 有权
标题翻译：单片垂直整合复合组III-V和IV族半导体器件及其制造方法
公开(公告)号：US07915645B2
公开(公告)日：2011-03-29
申请号：US12455117
申请日：2009-05-28
申请人： Michael A. Briere
发明人： Michael A. Briere
IPC分类号： H01L29/739 , H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109
CPC分类号： H01L27/0629 , H01L21/8221 , H01L21/8258 , H01L23/481 , H01L23/535 , H01L27/0605 , H01L27/0694 , H01L29/16 , H01L29/2003 , H01L29/205 , H01L29/778 , H01L29/7786 , H01L29/78 , H01L29/861 , H01L29/872 , H01L2924/0002 , H03K17/567 , H01L2924/00
摘要： According to one disclosed embodiment, a monolithic vertically integrated composite device comprises a double sided semiconductor substrate having first and second sides, a group IV semiconductor layer formed over the first side and comprising at least one group IV semiconductor device, and a group III-V semiconductor body formed over the second side and comprising at least one group III-V semiconductor device electrically coupled to the at least one group IV semiconductor device. The composite device may further comprise a substrate via and/or a through-wafer via providing electric coupling. In one embodiment, the group IV semiconductor layer may comprise an epitaxial silicon layer, and the at least one group IV semiconductor device may be a combined FET and Schottky diode (FETKY) fabricated on the epitaxial silicon layer. In one embodiment, the at least one group III-V semiconductor device may be a III-nitride high electron mobility transistor (HEMT).
摘要翻译：根据一个公开的实施例，单片垂直集成复合器件包括具有第一和第二侧面的双面半导体衬底，在第一侧上形成的包含至少一个IV族半导体器件的IV族半导体层，以及III-V族半导体本体形成在第二侧上并且包括电耦合到至少一个IV族半导体器件的至少一个III-V族半导体器件。复合器件还可以通过提供电耦合来包括衬底通孔和/或贯通晶片。在一个实施例中，IV族半导体层可以包括外延硅层，并且该至少一个IV族半导体器件可以是在外延硅层上制造的组合FET和肖特基二极管（FETKY）。在一个实施例中，所述至少一个III-V族III族半导体器件可以是III族氮化物高电子迁移率晶体管（HEMT）。

95. 发明授权

US07868367B2 System and method for CMOS image sensing 有权
标题翻译： CMOS图像感测的系统和方法
公开(公告)号：US07868367B2
公开(公告)日：2011-01-11
申请号：US12136568
申请日：2008-06-10
申请人： Zhu Hong , Jim Yang
发明人： Zhu Hong , Jim Yang
IPC分类号： H01L31/062 , H01L31/113 , H01L27/15 , H01L29/16 , H01L31/12 , H01L33/00 , H01L29/161 , H01L31/153 , H01L29/735 , H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109 , H01L31/06
CPC分类号： H01L27/14647 , H01L27/14689
摘要： A system and method for sensing image on CMOS. According to an embodiment, the present invention provide a CMOS image sensing pixel. The pixel includes an n-type substrate, which includes a first width and a first thickness. The pixel also includes a p-type epitaxy layer overlying the n-type substrate. The p-type epitaxy layer includes a second width and a second thickness. The second width is associated with one or more characteristics of a colored light. The pixel additionally includes an n-type layer overlying the p-type epitaxy layer. The n-type layer is associated with a third width and a third thickness. Additionally, the pixel includes an pn junction formed between the p-type epitaxy layer and the n-type layer. Moreover, the pixel includes a control circuit being coupled to the CMOS image sensing pixel.
摘要翻译：一种用于感测CMOS图像的系统和方法。根据实施例，本发明提供一种CMOS图像感测像素。像素包括n型衬底，其包括第一宽度和第一厚度。像素还包括覆盖在n型衬底上的p型外延层。 p型外延层包括第二宽度和第二厚度。第二宽度与彩色光的一个或多个特性相关联。像素还包括覆盖p型外延层的n型层。 n型层与第三宽度和第三厚度相关联。另外，像素包括在p型外延层和n型层之间形成的pn结。此外，像素包括耦合到CMOS图像感测像素的控制电路。

96. 发明授权

US07851821B2 Group III nitride semiconductor device, epitaxial substrate, and method of fabricating group III nitride semiconductor device 有权
标题翻译： III族氮化物半导体器件，外延衬底和制造III族氮化物半导体器件的方法
公开(公告)号：US07851821B2
公开(公告)日：2010-12-14
申请号：US12714049
申请日：2010-02-26
申请人： Takashi Kyono , Yusuke Yoshizumi , Yohei Enya , Katsushi Akita , Masaki Ueno , Takamichi Sumitomo , Takao Nakamura
发明人： Takashi Kyono , Yusuke Yoshizumi , Yohei Enya , Katsushi Akita , Masaki Ueno , Takamichi Sumitomo , Takao Nakamura
IPC分类号： H01L29/24 , H01L33/00 , H01L29/06 , H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109 , H01L29/739
CPC分类号： H01L21/02389 , B82Y20/00 , H01L21/02433 , H01L21/02458 , H01L21/02491 , H01L21/0254 , H01L21/02573 , H01L21/0262 , H01L33/16 , H01L33/32 , H01S5/305 , H01S5/3086 , H01S5/3202 , H01S5/3211 , H01S5/34333 , H01S2304/04
摘要： A group III nitride semiconductor device having a gallium nitride based semiconductor film with an excellent surface morphology is provided. A group III nitride optical semiconductor device 11a includes a group III nitride semiconductor supporting base 13, a GaN based semiconductor region 15, an active layer active layer 17, and a GaN semiconductor region 19. The primary surface 13a of the group III nitride semiconductor supporting base 13 is not any polar plane, and forms a finite angle with a reference plane Sc that is orthogonal to a reference axis Cx extending in the direction of a c-axis of the group III nitride semiconductor. The GaN based semiconductor region 15 is grown on the semipolar primary surface 13a. A GaN based semiconductor layer 21 of the GaN based semiconductor region 15 is, for example, an n-type GaN based semiconductor, and the n-type GaN based semiconductor is doped with silicon. A GaN based semiconductor layer 23 of an oxygen concentration of 5×1016 cm−3 or more provides an active layer 17 with an excellent crystal quality, and the active layer 17 is grown on the primary surface of the GaN based semiconductor layer 23.
摘要翻译：提供具有优异表面形态的具有氮化镓基半导体膜的III族氮化物半导体器件。 III族氮化物光半导体器件11a包括III族氮化物半导体支撑基底13，GaN基半导体区域15，有源层有源层17和GaN半导体区域19.第III族氮化物半导体支撑基底13的主表面13a 基座13不是任何极性平面，并且与参考平面Sc形成有限的角度，该参考平面Sc与在III族氮化物半导体的c轴方向上延伸的基准轴Cx正交。在半极性主表面13a上生长GaN基半导体区域15。 GaN系半导体区域15的GaN系半导体层21例如为n型GaN系半导体，n型GaN系半导体掺杂有硅。氧浓度为5×1016cm-3以上的GaN系半导体层23提供具有优异晶体质量的有源层17，并且在GaN基半导体层23的主表面上生长有源层17。

97. 发明授权

US07847319B2 Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07847319B2
公开(公告)日：2010-12-07
申请号：US11984723
申请日：2007-11-21
申请人： Yutaka Hirose , Yoshito Ikeda , Kaoru Inoue
发明人： Yutaka Hirose , Yoshito Ikeda , Kaoru Inoue
IPC分类号： H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109
CPC分类号： H01L21/28581 , H01L29/2003 , H01L29/42316 , H01L29/475 , H01L29/66462
摘要： A semiconductor device has a Group III nitride semiconductor layer and a gate electrode formed on the Group III nitride semiconductor layer. The gate electrode contains an adhesion enhancing element. A thermally oxidized insulating film is interposed between the Group III nitride semiconductor layer and the gate electrode.
摘要翻译：半导体器件具有形成在III族氮化物半导体层上的III族氮化物半导体层和栅电极。栅极电极含有粘附增强元件。在III族氮化物半导体层和栅电极之间插入热氧化绝缘膜。

98. 发明授权

US07847281B2 Semiconductor device with strain in channel region and its manufacture method 有权
标题翻译：通道区应变半导体器件及其制造方法
公开(公告)号：US07847281B2
公开(公告)日：2010-12-07
申请号：US12057427
申请日：2008-03-28
申请人： Takashi Mimura , Atsushi Yamada
发明人： Takashi Mimura , Atsushi Yamada
IPC分类号： H01L29/06 , H01L31/072 , H01L31/0336 , H01L31/0328 , H01L31/109
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/165 , H01L29/495 , H01L29/66545 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7843 , H01L29/7848 , H01L2924/0002 , H01L2924/00
摘要： A first film made of SiGe is formed over a support substrate whose surface layer is made of Si. A gate electrode is formed over a partial area of the first film, and source and drain regions are formed in the surface layer of the support substrate on both sides of the gate electrode. The gate electrode and source and drain regions constitute a first field effect transistor. A first stressor internally containing compressive strain or tensile strain is formed over the first film on both sides of the gate electrode of the first field effect transistor. The first stressor forms strain in a channel region.
摘要翻译：由SiGe制成的第一薄膜形成在表面层由Si制成的支撑基板上。栅极电极形成在第一膜的部分区域上，并且源极和漏极区域形成在栅电极两侧的支撑衬底的表面层中。栅极电极和源极和漏极区域构成第一场效应晶体管。在第一场效应晶体管的栅电极的两侧上的第一膜上形成内部包含压应变或拉伸应变的第一应力器。第一应激源在通道区域中形成应变。

99. 发明授权

US07829882B2 Nitride semiconductor light emitting device 有权
标题翻译：氮化物半导体发光器件
公开(公告)号：US07829882B2
公开(公告)日：2010-11-09
申请号：US11581335
申请日：2006-10-17
申请人： Sun Woon Kim , Je Won Kim , Sang Won Kang , Keun Man Song , Bang Won Oh
发明人： Sun Woon Kim , Je Won Kim , Sang Won Kang , Keun Man Song , Bang Won Oh
IPC分类号： H01L29/06 , H01L31/072 , H01L31/109 , H01L31/0328 , H01L31/0336 , H01L31/00
CPC分类号： H01L33/06 , B82Y20/00 , H01L33/32
摘要： The invention provides a highly reliable nitride semiconductor light emitting device improved in electrostatic discharge withstand voltage. In the light emitting device, an n-type nitride semiconductor layer, an active layer and a p-type nitride semiconductor layer are sequentially formed on a substrate. The active layer features a multiple quantum well structure including a plurality of multiple quantum barrier layers and quantum well layers. At least one of the quantum barrier layers has a band-gap modulated multilayer structure.
摘要翻译：本发明提供了一种改进了静电放电耐受电压的高度可靠的氮化物半导体发光器件。在发光器件中，在衬底上依次形成n型氮化物半导体层，有源层和p型氮化物半导体层。有源层具有包括多个多量子势垒层和量子阱层的多量子阱结构。至少一个量子势垒层具有带隙调制多层结构。

100. 发明授权

US07791064B2 Semiconductor device and fabrication method thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US07791064B2
公开(公告)日：2010-09-07
申请号：US11107945
申请日：2005-04-18
申请人： Yosuke Shimamune , Akira Katakami , Akiyoshi Hatada , Masashi Shima , Naoyoshi Tamura
发明人： Yosuke Shimamune , Akira Katakami , Akiyoshi Hatada , Masashi Shima , Naoyoshi Tamura
IPC分类号： H01L29/06 , H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109
CPC分类号： H01L29/7848 , H01L21/02381 , H01L21/02532 , H01L21/02579 , H01L21/0262 , H01L21/02639 , H01L21/28518 , H01L21/30608 , H01L29/045 , H01L29/0653 , H01L29/0847 , H01L29/165 , H01L29/45 , H01L29/4975 , H01L29/518 , H01L29/665 , H01L29/66628 , H01L29/66636 , H01L29/78 , H01L29/7833 , Y10S257/90
摘要： A semiconductor device includes a gate electrode formed on a silicon substrate via a gate insulation film in correspondence to a channel region, source and drain regions of a p-type diffusion region formed in the silicon substrate at respective outer sides of sidewall insulation films of the gate electrode, and a pair of SiGe mixed crystal regions formed in the silicon substrate at respective outer sides of the sidewall insulation films in epitaxial relationship to the silicon substrate, the SiGe mixed crystal regions being defined by respective sidewall surfaces facing with each other, wherein, in each of the SiGe mixed crystal regions, the sidewall surface is defined by a plurality of facets forming respective, mutually different angles with respect to a principal surface of the silicon substrate.
摘要翻译：一种半导体器件包括：栅极电极，形成在硅衬底上，栅极绝缘膜对应于沟道区，形成在硅衬底中的p型扩散区的源极和漏极区域的侧壁绝缘膜的相应外侧栅电极和在硅衬底中在与硅衬底呈外延角的侧壁绝缘膜的各外侧形成的一对SiGe混合晶体区域，SiGe混晶区域由彼此相对的侧壁表面限定，其中在每个SiGe混合晶体区域中，侧壁表面由相对于硅衬底的主表面形成相应不同角度的多个面限定。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式