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91. 发明授权

US5412262A Semiconductor integrated circuit device having plurality of supply potential lines connected thereto, and system employing the same 失效
标题翻译：具有与其连接的多个电源电位线的半导体集成电路器件及其系统
公开(公告)号：US5412262A
公开(公告)日：1995-05-02
申请号：US279626
申请日：1994-07-25
申请人： Yoji Nishio , Fumio Murabayashi , Kozaburo Kurita , Masahiro Iwamura
发明人： Yoji Nishio , Fumio Murabayashi , Kozaburo Kurita , Masahiro Iwamura
IPC分类号： H03K19/00 , H01L27/02 , H03K19/0175 , H03K19/0185 , H03K19/02
CPC分类号： H03K19/017527 , H03K19/018521 , H01L27/0214
摘要： In a system wherein a plurality of semiconductor integrated circuit devices are coexistent and wherein a plurality of supply potential lines are laid, the main power sources of a TTL interface LSI and an ECL interface LSI are shared so as to reduce the number of supply potential lines. Besides, in a case where an LSI, for example, BiCMOS LSI to interface with both the TTL and ECL interface LSI's has a device withstand voltage of about 3 V, it is permitted to interface with both the LSI's across the supply voltage .vertline.5 V.vertline. of the main power source of the TTL interface LSI and the supply voltage .vertline.2 V.vertline. of the power source of the emitter follower portion of the ECL interface LSI because the supply voltages have a difference of 3 V.
摘要翻译：在其中多个半导体集成电路器件共存并且其中布置多条电源线的系统中，TTL接口LSI和ECL接口LSI的主电源被共享，以便减少电源电位线的数量。此外，在与例如TTL和ECL接口LSI接口的BiCMOS LSI的LSI具有约3V的器件耐受电压的情况下，允许与两者的两端的电源电压| 5V | 的TTL接口LSI的主电源和电源电压| 2 V | 由于电源电压具有3V的差异，所以ECL接口LSI的射极跟随器部分的电源。

92. 发明授权

US5397937A Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US5397937A
公开(公告)日：1995-03-14
申请号：US70249
申请日：1993-06-02
申请人： Kimio Ueda , Hiroaki Suzuki
发明人： Kimio Ueda , Hiroaki Suzuki
IPC分类号： H01L21/8249 , H01L27/06 , H03K17/04 , H03K17/567 , H03K17/62 , H03K19/08 , H03K19/21 , H03K19/02
CPC分类号： H03K19/21 , H03K17/6257
摘要： There is disclosed a semiconductor integrated circuit comprising pass transistor circuits (PT3, PT4) for producing logically complementary signals. The output of the pass transistor circuit (PT3) is connected to the base electrode of an NPN bipolar transistor (BN1), and the output of the pass transistor circuit (PT4) is connected to the gate electrode of an NMOS transistor (MN9). PMOS transistors (MP15, MP16) are connected between the outputs of the pass transistor circuits (PT3, PT4) and a first potential (VDD). The gate electrodes of the PMOS transistors (MP15, MP16) are connected to the outputs of the pass transistor circuits (PT3, PT4). The bipolar transistor (BN1) having a large driving force charges and discharges a load capacity (CL1) connected to an output terminal in response to the output signal of the pass transistor circuit (PT3). This provides for a logic circuit which operates at high speeds in the semiconductor integrated circuit.
摘要翻译：公开了一种半导体集成电路，包括用于产生逻辑互补信号的传输晶体管电路（PT3，PT4）。传输晶体管电路（PT3）的输出端连接到NPN双极晶体管（BN1）的基极，传输晶体管电路（PT4）的输出端连接到NMOS晶体管（MN9）的栅电极。 PMOS晶体管（MP15，MP16）连接在传输晶体管电路（PT3，PT4）的输出端和第一电位（VDD）之间。 PMOS晶体管（MP15，MP16）的栅电极连接到传输晶体管电路（PT3，PT4）的输出端。具有大驱动力的双极型晶体管（BN1）响应于传输晶体管电路（PT3）的输出信号，对连接到输出端子的负载电容（CL1）进行充电和放电。这提供了在半导体集成电路中以高速工作的逻辑电路。

93. 发明授权

US5323376A Atomic scale electronic switch 失效
标题翻译：原子电子开关
公开(公告)号：US5323376A
公开(公告)日：1994-06-21
申请号：US918752
申请日：1992-07-27
申请人： Donald M. Eigler
发明人： Donald M. Eigler
IPC分类号： G11C11/00 , G01Q30/00 , G01Q60/40 , G01Q60/42 , G11B9/00 , G11B11/00 , G11C11/56 , G11C13/02 , H03K17/51 , H03K17/54 , H03K17/56 , H03K19/00 , H03K19/02 , H01J37/30
CPC分类号： G11C13/0014 , B82Y10/00 , G11B11/002 , G11B9/14 , G11B9/1463 , G11C11/5664 , G11C13/02 , H03K17/51 , H03K17/545 , H03K19/02 , G11C13/025 , G11C13/04 , Y10S977/936 , Y10S977/947 , Y10T307/826 , Y10T307/839
摘要： The present invention relates to an atomic scale electronic switch; wherein the position of one or more atoms or molecules is or are varied to control the state of the switch. The switch includes a plurality of fixed terminals approximately separated less than 100 .ANG.. Controlling the state of the switch is accomplished by applying a voltage or current to the terminals, thereby moving at least one atoms toward a desired terminal.
摘要翻译：本发明涉及一种原子级电子开关; 其中一个或多个原子或分子的位置是或被改变以控制开关的状态。开关包括大致分开的多个固定端子小于100安培。通过向端子施加电压或电流来实现控制开关的状态，从而将至少一个原子移向期望的端子。

94. 发明授权

US5309039A Power supply dependent input buffer 失效
标题翻译：电源相关的输入缓冲器
公开(公告)号：US5309039A
公开(公告)日：1994-05-03
申请号：US953153
申请日：1992-09-29
申请人： Hamed Ghassemi , Perry H. Pelley, III
发明人： Hamed Ghassemi , Perry H. Pelley, III
IPC分类号： H03F3/45 , H03F3/50 , H03K19/003 , H03K19/0175 , H03K19/086 , H03K3/01 , G06G7/12 , H03K17/60 , H03K19/02
CPC分类号： H03K19/00376 , H03K19/017527
摘要： A power supply dependent input buffer (20) having a differential amplifier (22), emitter-follower transistors (29 and 32), level shifting resistors (30 and 33), and power supply dependent current sources (31 and 34) receives an ECL input signal referenced to a positive power supply voltage and provides buffered level shifted signals referenced to ground. The current sources (31 and 34) receive a power supply dependent bias voltage that changes in relation to a change in the positive power supply voltage. In turn, the voltage drop across the resistors (30 and 33) changes with respect to the positive power supply voltage such that the buffered level shifted signals are constant with respect to ground. The power supply dependent input buffer (20) is for use at low power supply voltages (such as 3.3 volts), resulting in low power consumption and wider margins on following stages, such as a level converter.
摘要翻译：具有差分放大器（22），射极跟随器晶体管（29和32），电平移位电阻（30和33）以及与电源相关的电流源（31和34）的电源依赖输入缓冲器（20）接收ECL 参考正电源电压的输入信号，并提供参考地的缓冲电平移位信号。电流源（31和34）接收相对于正电源电压变化而变化的电源相关偏置电压。反过来，电阻器（30和33）上的电压降相对于正电源电压变化，使得缓冲电平移位信号相对于地而恒定。电源相关的输入缓冲器（20）用于低电源电压（例如3.3伏特），导致低功耗，并且在后续阶段（例如电平转换器）具有更宽的裕度。

95. 发明授权

US5287021A Low noise BICMOS circuit 失效
标题翻译：低噪声BICMOS电路
公开(公告)号：US5287021A
公开(公告)日：1994-02-15
申请号：US880109
申请日：1992-05-06
申请人： Carlos D. Obregon , Eric D. Neely , Michael A. Wells
发明人： Carlos D. Obregon , Eric D. Neely , Michael A. Wells
IPC分类号： H03K19/003 , H03K17/60 , H03K17/16 , H03K19/02 , H03K19/20
CPC分类号： H03K19/00346
摘要： A plurality of transistors (22, 23, 27) are utilized to provide a low noise high-to-low transition (40) on an output (19) of a circuit (10). The transistors (22, 23, 27) are sequentially enabled to vary a rate of change of output current thereby minimizing noise created by the high-to-low transition (40). A first transistor (22) is enabled to provide a low rate of change. Subsequently, a second transistor (23) is enabled to provide a higher rate of change. Then, just prior to disabling the second transistor (23) a third transistor (27) is enabled to provide a d.c. level.
摘要翻译：多个晶体管（22,23,27）用于在电路（10）的输出（19）上提供低噪声的高到低的转换（40）。晶体管（22,23,27）依次使能以改变输出电流的变化率，从而最小化由高到低的转变产生的噪声（40）。第一晶体管（22）能够提供低变化率。随后，第二晶体管（23）能够提供更高的变化率。然后，在禁止第二晶体管（23）之前，第三晶体管（27）能够提供直流水平。

96. 发明授权

US5254885A Bi-CMOS logic circuit with feedback 失效
标题翻译：具有反馈的双CMOS逻辑电路
公开(公告)号：US5254885A
公开(公告)日：1993-10-19
申请号：US818094
申请日：1992-01-08
申请人： Kouichi Ando
发明人： Kouichi Ando
IPC分类号： H03K19/08 , H03K19/00 , H03K19/0944 , H03K19/02
CPC分类号： H03K19/09448 , H03K19/0008
摘要： A logic circuit includes a first and a second bipolar transistor forming a signal output circuit; first and a second MOS transistor circuits each for performing a specified logic operation with the input signal, and making or breaking connection between the collector and the base of the first and second bipolar transistors, respectively, in reverse relation to each other. A third MOS transistor circuit is connected between the first bipolar transistor and a ground potential point, and second MOS transistor is connected between the base and the emitter of the first MOS. A control circuit is provided for causing the first and second MOS transistors to turn ON or OFF later than the turn-ON of turn-OFF of the first and second MOS transistor circuits. Further, a third MOS transistor caused to turn ON or OFF by the control circuit is provided between the base of the first bipolar transistor and the third MOS transistor.
摘要翻译：逻辑电路包括形成信号输出电路的第一和第二双极晶体管; 第一和第二MOS晶体管电路，每个用于利用输入信号执行指定的逻辑运算，以及分别使第一和第二双极晶体管的集电极和基极之间的连接彼此相反地或断开。第三MOS晶体管电路连接在第一双极晶体管和地电位点之间，第二MOS晶体管连接在第一MOS的基极和发射极之间。提供控制电路，用于使第一和第二MOS晶体管比第一和第二MOS晶体管电路的关断的导通更迟地导通或截止。此外，在第一双极晶体管的基极和第三MOS晶体管之间设置由控制电路导通或截止的第三MOS晶体管。

97. 发明授权

US5138586A Acoustic logic circuits 失效
标题翻译：声学逻辑电路
公开(公告)号：US5138586A
公开(公告)日：1992-08-11
申请号：US706915
申请日：1991-05-29
申请人： Michael A. Marcus
发明人： Michael A. Marcus
IPC分类号： G01H13/00 , G01S15/02 , G10K15/00 , H03K19/02 , H04R1/28
CPC分类号： G10K15/00 , G01S15/02 , Y10S367/903
摘要： An acoustic sensor functioning as a digital logic device comprises a resonant chamber, at least one port establishing a first resonant frequency therein when the port is closed and establishing a second resonant frequency therein when the port is open, a transmitter in communication with the chamber and tuned to either of the first or second resonant frequencies and a receiver in communication with the chamber for providing a digital logic output. When the port is closed or open and when the transmitter is tuned to the second or first resonant frequencies, respectively, the device functions as an inverter.In another form an acoustic logic device comprises a resonant chamber, at least two ports establishing a plurality of resonant frequencies therein depending upon whether the ports are all open, all closed or some open and the rest closed, a receiver in communication with the chamber for providing a digital logic output, and a transmitter in communication with the chamber and tuned to one of the resonant frequencies. When the device includes two ports and the transmitter is tuned to the resonant frequency corresponding to both of the ports being closed, or both of the ports being open or one of the ports being open and the other port being closed, the device functions as an AND gate or a NOR gate or an EXCLUSIVE OR gate, respectively. Also provided are acoustic logic devices having three or more ports.
摘要翻译：用作数字逻辑装置的声传感器包括谐振室，当端口闭合时至少一个端口建立第一谐振频率，并且当端口打开时建立第二共振频率，与腔室连通的发射器和调谐到第一或第二谐振频率中的任一个，以及与腔室通信的接收器，用于提供数字逻辑输出。当端口关闭或断开时，并且当发射机分别调谐到第二或第一谐振频率时，该装置用作逆变器。在另一种形式中，声学逻辑装置包括谐振室，至少两个端口在其中建立多个谐振频率，这取决于这些端口是否全部是开放的，全部闭合的，还是一些开放的，而其余的封闭，与腔室连通的接收器，提供数字逻辑输出，以及与腔室通信并被调谐到谐振频率之一的发射器。当设备包括两个端口并且发射机被调谐到对应于正在关闭的两个端口的谐振频率，或者两个端口是打开的，或者其中一个端口是打开的，而另一个端口被闭合时，该装置用作 AND门或NOR门或EXCLUSIVE或门。还提供了具有三个或更多个端口的声学逻辑器件。

98. 发明授权

US4810903A BICMOS driver circuit including submicron on chip voltage source 失效
标题翻译： BICMOS驱动电路包括亚微米片上电压源
公开(公告)号：US4810903A
公开(公告)日：1989-03-07
申请号：US132843
申请日：1987-12-14
申请人： Thomas P. Bushey , Walter C. Seelbach
发明人： Thomas P. Bushey , Walter C. Seelbach
IPC分类号： H03K17/567 , H03K19/013 , H03K19/08 , H03K19/0944 , H03K19/02 , H03K17/16 , H03K19/094
CPC分类号： H03K19/09448 , H03K19/0136
摘要： A BICMOS driver circuit is provided having high input impedence and high output current drive with low static power dissipation that provides supply voltages and full logic output voltage swing for circuits having submicron dimensions. An inverter circuit is coupled to a voltage divider circuit and the input terminal for inverting the input signal. A complementary emitter follower circuit is coupled to an output terminal for providing a digital output signal. A current source circuit is coupled to the complementary emitter follower circuit and the input terminal for sourcing current to the complementary emitter follower circuit in response to the input signal. A bipolar bias circuit is coupled to the complementary emitter follower circuit and the inverter circuit for biasing the complementary emitter follower circuit in response to an inverted input signal.

99. 发明授权

US4798983A Driving circuit for cascode BiMOS switch 失效
标题翻译：串联BiMOS开关的驱动电路
公开(公告)号：US4798983A
公开(公告)日：1989-01-17
申请号：US53339
申请日：1987-05-21
申请人： Satoshi Mori
发明人： Satoshi Mori
IPC分类号： H03K17/04 , H03K17/56 , H03K17/567 , H03K17/60 , H03K3/01 , H03K5/00 , H03K19/02
CPC分类号： H03K17/567
摘要： A driving circuit for driving a cascode bype BiMOS switch which includes a bipolar transistor whose collector is connected through a load to a positive electrode of a power source and a field effect transistor whose drain is connected to an emitter of the bipolar transistor and whose source is connected to a negative electrode of the power source. The driving circuit comprises an n.p series body formed by connecting an n-channel field effect transistor in series relation with a p-channel field effect transistor, wherein a mid-point to the n.p series body is connected to a base of the bipolar transistor. A drain and a source of the n-channel field effect transistor are connected to a D.C. power source and the mid-point, respectively. A drain and a source of the p-channel field effect transistor are connected to the mid-point and the negative electrode of the power source, and a gate of the field effect transistor and gates of the n-channel and p-channel field effect transistors are connected to an input terminal, whereby the cascode type BiMOS switch is driven by a single positive or negative signal.
摘要翻译：用于驱动共源共栅BiMOS开关的驱动电路，其包括集电极通过负载连接到电源的正极的双极晶体管和漏极连接到双极晶体管的发射极的场效应晶体管，连接到电源的负极。驱动电路包括通过与p沟道场效应晶体管串联连接n沟道场效应晶体管而形成的n.p系列体，其中n.p系列体的中点连接到双极晶体管的基极。 n沟道场效应晶体管的漏极和源极分别连接到直流电源和中点。 p沟道场效应晶体管的漏极和源极连接到电源的中点和负极，场效应晶体管的栅极和n沟道和p沟道场效应的栅极晶体管连接到输入端，由此共源共栅型BiMOS开关由单个正或负信号驱动。

100. 发明授权

US4713559A Multiple input and multiple output or/and circuit 失效
标题翻译：多输入和多路输出或/和电路
公开(公告)号：US4713559A
公开(公告)日：1987-12-15
申请号：US728066
申请日：1985-04-29
申请人： Tho T. Vu , Kang W. Lee
发明人： Tho T. Vu , Kang W. Lee
IPC分类号： H03K19/0185 , H03K3/356 , H03K19/0952 , H03K19/0956 , H03K19/02 , H03K19/084 , H03K19/092 , H03K19/094
CPC分类号： H03K19/0956 , H03K3/356026
摘要： An OR logic function is provided in at least two separate circuit branches by diodes in parallel summing current at a first logic node and a first circuit branch and diodes in parallel summing current at a second logic node in a second current branch. An AND logic function is performed at a third logic node by using additional diodes connected in parallel at the third logic node so as to share current passing through the third logic node, with the logic conditions at the first and second logic nodes serving as the inputs to the AND logic function. The logic condition at the third logic node is applied to the gate of a switching FET. The switching FET is conveniently employed to invert the logic condition at the third logic node. The invention is particularly suited for use with MESFET logic families using gallium arsenide (GaAs) substrates.
摘要翻译：在至少两个独立的电路分支中，在第一逻辑节点处以并行求和电流的二极管和第二电路分支中的第一电路支路以及在第二电流分支中的第二逻辑节点处的并联求和电流的二极管在至少两个独立的电路分支中提供OR逻辑功能。通过使用在第三逻辑节点处并联连接的附加二极管来执行AND逻辑功能，以在第三逻辑节点处共享通过第三逻辑节点的电流，第一和第二逻辑节点的逻辑条件用作输入到AND逻辑功能。第三逻辑节点处的逻辑条件被施加到开关FET的栅极。切换FET方便地用于反转第三逻辑节点处的逻辑条件。本发明特别适用于使用砷化镓（GaAs）衬底的MESFET逻辑系列。

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