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91. 发明授权

US4916334A High voltage booster circuit for use in EEPROMs 失效
标题翻译：用于EEPROM的高压升压电路
公开(公告)号：US4916334A
公开(公告)日：1990-04-10
申请号：US226312
申请日：1988-07-29
申请人： Hidenobu Minagawa , Yuuichi Tatsumi , Hiroshi Iwahashi , Masamichi Asano , Mizuho Imai
发明人： Hidenobu Minagawa , Yuuichi Tatsumi , Hiroshi Iwahashi , Masamichi Asano , Mizuho Imai
IPC分类号： G11C16/30 , H02M3/07 , H03K5/02
CPC分类号： G11C16/30 , H02M3/07 , H03K5/023
摘要： A semiconductor integrated circuit includes a CMOS circuit operated on a voltage of a first voltage level to set an output node thereof to a voltage of the first voltage level or a reference voltage; an output circuit for controlling supply of a voltage of a second voltage level which is higher than the first voltage level to a signal output node; and an isolation MOS transistor having a current path connected between the output node of the CMOS circuit and the signal output node and a gate connected to receive a control signal. The output node of the CMOS circuit is set to the reference voltage with the conduction resistance of the isolation MOS transistor kept high after the lapse of period in which the voltage of the second voltage level is kept supplied to the signal output node. After this, the conduction resistance of the isolation MOS transistor is reduced in response to the control signal.
摘要翻译：半导体集成电路包括以第一电压电平工作的CMOS电路，以将其输出节点设置为第一电压电平或参考电压的电压; 输出电路，用于控制向信号输出节点提供高于第一电压电平的第二电压电平的电压; 以及隔离MOS晶体管，其具有连接在CMOS电路的输出节点和信号输出节点之间的电流路径以及连接以接收控制信号的栅极。 CMOS电路的输出节点被设定为参考电压，其中隔离MOS晶体管的导通电阻保持高电平，其中第二电压电平的电压被保持提供给信号输出节点。此后，隔离MOS晶体管的导通电阻响应于控制信号而减小。

92. 发明授权

US4916330A Signal level transforming circuit 失效
标题翻译：信号电平变换电路
公开(公告)号：US4916330A
公开(公告)日：1990-04-10
申请号：US249157
申请日：1988-09-26
申请人： Akira Hatakeyama , Takeshi Nakane
发明人： Akira Hatakeyama , Takeshi Nakane
IPC分类号： H03K3/0233 , H03K3/2893 , H03K5/02 , H03K5/08 , H03K19/018
CPC分类号： H03K3/2893 , H03K3/02337
摘要： A signal level transforming circuit includes a constant current circuit for supplying a constant current corresponding to a power voltage of an input signal to an electrical line connected between an output terminal connected with an input terminal via an input resistor and a common voltage level terminal, a low level clamping circuit for clamping the minimum value of the voltage at the output terminal to a first low level voltage, a voltage generating circuit for generating a constant voltage so as to transform a voltage signal in the input terminal into a binary signal, and a comparing circuit having a hysteresis characteristic and including a multi-collector type transistor having one collector connected with a voltage output terminal in the voltage generating circuit via a resistor for setting a comparing voltage, and having another collector connected to the output terminal, and a transistor inserted between a base of the multi-collector type transistor and the resistor for setting a comparing voltage and for turning ON when the voltage at the input terminal exceeds the voltage in the resistor.
摘要翻译：信号电平变换电路包括：恒流电路，用于将与输入信号的电源电压相对应的恒定电流提供给连接在经由输入电阻器与输入端子连接的输出端子与公共电压电平端子之间的电线; 低电平钳位电路，用于将输出端子处的电压的最小值钳位到第一低电平电压;电压产生电路，用于产生恒定电压，以将输入端子中的电压信号转换为二进制信号;以及具有滞后特性的比较电路，包括具有一个集电极的多集电极型晶体管，该多极集电极型晶体管通过用于设定比较电压的电阻器与电压产生电路中的电压输出端子连接，并且具有连接到输出端子的另一个集电极插入在多集电极型晶体管的基极和用于固定的电阻器之间 g是一个比较电压，当输入端的电压超过电阻中的电压时导通。

93. 发明授权

US4906867A Buffer circuit with load sensitive transition control 失效
标题翻译：具有负载敏感转换控制的缓冲电路
公开(公告)号：US4906867A
公开(公告)日：1990-03-06
申请号：US269022
申请日：1988-11-09
申请人： William K. Petty
发明人： William K. Petty
IPC分类号： H01L23/58 , G11C7/10 , G11C11/417 , H03K5/02 , H03K17/16 , H03K19/003 , H03K19/0175 , H03K19/0185 , H03K19/094
CPC分类号： G11C7/1051 , G11C7/1078 , H03K19/00361 , H03K19/09429
摘要： A buffer circuit particularly suited for driving the output pad of an integrated circuit, characterized in its provision of features which limit the rate of change of current flow in the power supply and ground lines to reduce noise. The circuit features feedback responsive compensation for variations in the capacitive load on the pad. In one form, the circuit includes a feedback capacitor between the pad and the control gate of the output transistor pulling the pad. The control gate of such pulling output driver transistor is, under one operational condition, provided with a voltage which increases at a limited rate during current enablement. The steady-state enablement of the output driver transistor is established later by a circuit logically responsive to the voltage on the output pad. The output driver transistor is subject to rapid disablement in response to a pulling of the control gate by a high speed and drive capacity transistor. In a preferred arrangement the circuit includes tri-state operation capability.

94. 发明授权

US4888505A Voltage multiplier compatible with a self-isolated C/DMOS process 失效
标题翻译：电压倍增器与自我隔离的C / DMOS工艺兼容
公开(公告)号：US4888505A
公开(公告)日：1989-12-19
申请号：US189442
申请日：1988-05-02
申请人： Timothy J. Skovmand
发明人： Timothy J. Skovmand
IPC分类号： H02M7/25 , H01L27/092 , H02M3/07 , H03K5/02 , H03K17/06 , H03K17/687 , H03K19/096
CPC分类号： H02M3/07 , H01L27/092 , H03K17/063
摘要： A CMOS structure is employed to create an isolated large area power output transistor along with a voltage multiplier that acts to develop an overdrive bias in response to clock pulses. The circuit can be employed to couple a relatively low power supply voltage to an output terminal while encountering a small voltage drop across the power transistor.
摘要翻译：使用CMOS结构来产生隔离的大面积功率输出晶体管以及用于响应于时钟脉冲产生过驱动偏压的电压倍增器。该电路可用于将相对低的电源电压耦合到输出端子，同时在功率晶体管两端遇到小的压降。

95. 发明授权

US4857766A BiMos input circuit 失效
标题翻译： BiMos输入电路
公开(公告)号：US4857766A
公开(公告)日：1989-08-15
申请号：US114973
申请日：1987-10-30
申请人： Wilbur D. Pricer , Francis W. Wiedman
发明人： Wilbur D. Pricer , Francis W. Wiedman
IPC分类号： H03K5/02 , H03K19/0175 , H03K19/0944
CPC分类号： H03K19/09448 , H03K19/017518
摘要： An ECL input circuit which receives an ECL input signal and which generates, in response to the input signal, a CMOS-compatible output signal. The input circuit includes a bipolar transistor, having its emitter region adapted to receive the ECL input signal, having its collector region coupled to a first current source, and having its base region connected to a second current source. The circuit further includes an output circuit which is coupled to the collector region of the bipolar transistor for providing the CMOS-compatible signal.

96. 发明授权

US4835419A Source-follower emitter-coupled-logic receiver circuit 失效
标题翻译：源极跟随器发射极耦合逻辑接收器电路
公开(公告)号：US4835419A
公开(公告)日：1989-05-30
申请号：US115690
申请日：1987-10-30
申请人： Barbara A. Chappell , Terry I. Chappell , Stanley E. Schuster
发明人： Barbara A. Chappell , Terry I. Chappell , Stanley E. Schuster
IPC分类号： H03K5/02 , H03K19/003 , H03K19/0185
CPC分类号： H03K19/018521 , H03K19/00384
摘要： A circuit means for interfacing between small emitter-coupled-logic (ECL) circuit voltage levels and larger field effect transistor (FET) circuits voltage level. The circuit interface means includes a source-follower stage wherein a first transistor device is ratioed relative to a second transistor device, so that a high percentage of an input voltage level signal to the first transistor device appears at a node between the first and second transistor devices, having been level shifted downward by greater than or equal to an n-channel threshold voltage. The percentage is enhanced by applying the complement of the input voltage level signal to the gate of the second transistor device. A gain stage is connected to the source-follower stage and includes third and fourth transistor devices wherein gain is developed by applying the level shifted input signal to the source of the fourth transistor device and the complement of the input signal directly to the gate of the fourth transistor device. A compensation stage for the circuit may also be included.

97. 发明授权

US4807190A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US4807190A
公开(公告)日：1989-02-21
申请号：US17533
申请日：1987-02-24
申请人： Kyoko Ishii , Kazumasa Yanagisawa , Masaya Muranaka
发明人： Kyoko Ishii , Kazumasa Yanagisawa , Masaya Muranaka
IPC分类号： G11C11/407 , G11C11/408 , H03K5/01 , H03K5/02 , H03K17/06 , H03K19/096 , G11C7/00
CPC分类号： H03K5/023 , G11C11/4085
摘要： A dynamic RAM is provided in which an output voltage of a booster circuit for forming a word line selection timing signal is rendered greater than a power source potential and less than a predetermined potential by providing voltage limitation means, thereby preventing destruction of circuit elements receiving the output voltage.
摘要翻译：提供了一种动态RAM，其中通过提供电压限制装置使用于形成字线选择定时信号的升压电路的输出电压大于电源电位并小于预定电位，从而防止接收输出电压。

98. 发明授权

US4800294A Pin driver circuit 失效
标题翻译：引脚驱动电路
公开(公告)号：US4800294A
公开(公告)日：1989-01-24
申请号：US147484
申请日：1988-01-25
申请人： Keith A. Taylor
发明人： Keith A. Taylor
IPC分类号： H03K19/088 , G01R31/319 , H03K5/02 , H03K17/66 , H03K19/0175 , H03K19/082 , H03K3/023 , H03K5/12
CPC分类号： G01R31/31924 , H03K17/666 , H03K19/0826 , G01R31/31922
摘要： A pin driver circuit for driving a digital integrated circuit is capable of producing symmetrical rise and fall characteristics, yet is suitable for implementation in monolithic bipolar integrated circuits. This circuit includes a pair of matched transconductance amplifiers, one at each end of an output resistor, connected between a voltage source and a return voltage. Each amplifier has one of a pair of equal resistors between its input terminal and high output terminal to develop an equal swing voltage on alternate ends of the output resistor when a swing voltage current source is switched between the two input resistors by a control signal. The output is taken from the junction between the output resistor and the low output terminal of the amplifier at the high end of the output resistor. An additional current source is connected to the input resistor of the amplifier at the low end of the divider to provide a current which may be adjusted to allow the standing current in the output resistor to be reduced to a satisfactory minimum. Additional circuitry can be added to allow the output to be put in a high impedance condition. In a preferred embodiment, the high level of the output, the swing voltage, and the standing current may all be controlled.
摘要翻译：用于驱动数字集成电路的引脚驱动电路能够产生对称的上升和下降特性，但适用于单片双极集成电路中的实现。该电路包括一对匹配的跨导放大器，一个在输出电阻器的每一端，连接在电压源和返回电压之间。每个放大器在其输入端和高输出端之间具有一对相等电阻中的一个，当通过控制信号在两个输入电阻之间切换摆动电压电流源时，在输出电阻的交替端产生相等的摆幅电压。输出取自输出电阻器高端的放大器的输出电阻和低输出端之间的结。额外的电流源连接到放大器的输入电阻器在分压器的低端，以提供可以被调节的电流，以使输出电阻器中的驻极电流能够降低到令人满意的最小值。可以添加额外的电路，以使输出处于高阻抗状态。在优选实施例中，可以全部控制输出的高电平，摆幅电压和静止电流。

99. 发明授权

US4785205A High speed ECL to CMOS converter 失效
标题翻译：高速ECL至CMOS转换器
公开(公告)号：US4785205A
公开(公告)日：1988-11-15
申请号：US067348
申请日：1987-06-29
申请人： Ikuo J. Sanwo , Mukesh B. Suthar
发明人： Ikuo J. Sanwo , Mukesh B. Suthar
IPC分类号： H03K5/02 , H03K19/003 , H03K19/0175 , H03K19/0185 , H03K17/16 , H03K19/017 , H03K19/092
CPC分类号： H03K19/018521 , H03K19/00384
摘要： An ECL to CMOS converter which connects the ECL input signal directly to the source electrode of a MOS gate, and the gate electrode of the MOS gate is independently regulated by connection to a reference voltage that is current sinked through a D.C. path to the negative CMOS voltage supply terminal. The drain electrode of the MOS gate is connected to the input of a CMOS inverter to provide the necessary logic level shift. Another MOS gate provides a D.C. signal path by connecting the input of the CMOS inverter to the negative CMOS voltage supply terminal.
摘要翻译：将ECL输入信号直接连接到MOS栅极的源电极的ECL至CMOS转换器和MOS栅极的栅电极通过连接到电流通过DC路径吸收到负CMOS的参考电压来独立地调节电源端子。 MOS栅极的漏电极连接到CMOS反相器的输入端，以提供必要的逻辑电平移位。另一个MOS栅极通过将CMOS反相器的输入连接到负CMOS电压源端子来提供直流信号路径。

100. 发明授权

US4782340A Electronic arrays having thin film line drivers 失效
标题翻译：具有薄膜线驱动器的电子阵列
公开(公告)号：US4782340A
公开(公告)日：1988-11-01
申请号：US899442
申请日：1986-08-22
申请人： Wolodymyr Czubatyj , Roger W. Pryor
发明人： Wolodymyr Czubatyj , Roger W. Pryor
IPC分类号： G11C11/407 , G11C8/08 , H01L21/8229 , H01L27/10 , H01L27/102 , H03K5/02 , H03K19/0175 , G09G3/34
CPC分类号： G11C8/08 , H01L27/10 , H03K19/017545 , H03K5/023 , G11C2211/5614
摘要： Fully integrated thin film electronic arrays including thin film line driver circuits and address decoding circuits are disclosed. Each line driver employs a two terminal thin film threshold switching device of the type exhibiting a negative resistance characteristic for very high speed, high current operation. The line drivers are particularly useful when driving address lines or other switched conductors in arrays having large capacitive loads or current requirements. The address decoding circuits are constructed from an array of thin film diodes configured as a plurality of AND logic gates, with the output of each AND gate providing the trigger signal to turn on a line driver circuit associated with a particular address line. Thin film structures used to implement the fully integrated arrays include diodes and threshold switches arranged as high density vertical devices in the form of multilayer mesa structures. An electronic memory array having a plurality of vertically arranged cells, with each cell provided with a thin film isolation diode and a thin film memory element, is also disclosed.
摘要翻译：公开了包括薄膜线路驱动电路和地址解码电路的完全集成的薄膜电子阵列。每个线路驱动器采用具有负电阻特性的类型的双端子薄膜阈值开关器件，用于非常高速，高电流操作。当驱动具有大容性负载或电流要求的阵列中的地址线或其他开关导体时，线路驱动器特别有用。地址解码电路由配置为多个AND逻辑门的薄膜二极管阵列构成，每个与门的输出提供触发信号以接通与特定地址线相关联的线路驱动电路。用于实现完全集成阵列的薄膜结构包括二极管和阈值开关，其布置为多层台面结构形式的高密度垂直器件。还公开了具有多个垂直排列的单元的电子存储器阵列，每个单元设置有薄膜隔离二极管和薄膜存储元件。

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