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11. 发明授权

US07826306B2 Semiconductor memory apparatus 有权
标题翻译：半导体存储装置
公开(公告)号：US07826306B2
公开(公告)日：2010-11-02
申请号：US12332298
申请日：2008-12-10
申请人： Ji-Wang Lee , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Jae-Min Jang , Chang-Kun Park
发明人： Ji-Wang Lee , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Jae-Min Jang , Chang-Kun Park
IPC分类号： G11C8/00
CPC分类号： G11C7/1078 , G11C5/063 , G11C7/02 , G11C7/1084 , G11C7/1093 , G11C29/02 , G11C29/022 , G11C29/023 , G11C29/028
摘要： A semiconductor memory apparatus includes a clock generator configured to generate an internal clock signal, an asynchronous data input buffer configured to buffer a data input signal through a data pad to output a buffered data signal, and a synchronous data input buffer configured to buffer the buffered data signal synchronously with the internal clock signal, wherein a length of a line, through which the internal clock signal is transmitted to the synchronous data input buffer, is configured to be substantially the same with a length of a line, through which the buffered data is transmitted to the synchronous data input buffer.
摘要翻译：一种半导体存储装置，包括被配置为产生内部时钟信号的时钟发生器，配置成通过数据焊盘缓冲数据输入信号以输出缓冲数据信号的异步数据输入缓冲器，以及被配置为缓冲缓冲的数据输入缓冲器数据信号与内部时钟信号同步，其中通过其将内部时钟信号发送到同步数据输入缓冲器的线路的长度被配置为与线路的长度基本相同，通过该线路的长度，缓冲的数据被发送到同步数据输入缓冲器。

12. 发明授权

US07800416B2 Data output buffer circuit 有权
标题翻译：数据输出缓冲电路
公开(公告)号：US07800416B2
公开(公告)日：2010-09-21
申请号：US12340882
申请日：2008-12-22
申请人： Yong Ju Kim , Sung Woo Han , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee , Jae Min Jang , Chang Kun Park
发明人： Yong Ju Kim , Sung Woo Han , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee , Jae Min Jang , Chang Kun Park
IPC分类号： H03K3/00
CPC分类号： G11C7/1051 , G11C7/02 , G11C7/04 , G11C7/1057 , G11C7/1066 , G11C7/1072 , G11C11/4093
摘要： A data output circuit includes a pre-driving block configured to receive input data, generate a plurality of pull-up signals and pull-down signals, and change enable times of the pull-up signals and the pull-down signals in response to a plurality of control signals, and a main driving block configured to generate output data in response to the pull-up signals and the pull-down signals.
摘要翻译：数据输出电路包括：预驱动块，被配置为接收输入数据，产生多个上拉信号和下拉信号，以及响应于一个上拉信号和下拉信号改变使能时间多个控制信号和主驱动块，被配置为响应于上拉信号和下拉信号而产生输出数据。

13. 发明授权

US07786783B2 Duty cycle correction circuit with reduced current consumption 失效
标题翻译：占空比校正电路，降低电流消耗
公开(公告)号：US07786783B2
公开(公告)日：2010-08-31
申请号：US12333193
申请日：2008-12-11
申请人： Hee-Woong Song , Yong-Ju Kim , Sung-Woo Han , Jae-Min Jang , Hyung-Soo Kim , Ji-Wang Lee , Chang-Kun Park , Ic-Su Oh , Hae-Rang Choi , Tae-Jin Hwang
发明人： Hee-Woong Song , Yong-Ju Kim , Sung-Woo Han , Jae-Min Jang , Hyung-Soo Kim , Ji-Wang Lee , Chang-Kun Park , Ic-Su Oh , Hae-Rang Choi , Tae-Jin Hwang
IPC分类号： H03K3/017
CPC分类号： H03K5/1565
摘要： A duty cycle correction circuit includes a signal generating unit including a first signal generating unit coupled to a power supply voltage terminal and configured to output a complementary output signal of an output signal in response to a clock signal, and a second signal generating unit coupled to the power supply voltage terminal and configured to output the output signal in response to a complementary clock signal of the clock signal; a variable resistor unit coupled between the first and second signal generating units configured to vary an amount of current flowing into the signal generating unit according to a duty correction control signal, the duty correction control signal having a voltage level determined based on a voltage level of the output signal; and a current source coupled between the variable resistor unit and a ground voltage terminal configured to supply current to the signal generating unit.
摘要翻译：一种占空比校正电路包括：信号产生单元，包括耦合到电源电压端并被配置为响应于时钟信号输出输出信号的互补输出信号的第一信号产生单元，以及耦合到所述电源电压端子被配置为响应于所述时钟信号的互补时钟信号而输出所述输出信号; 耦合在第一和第二信号发生单元之间的可变电阻器单元，被配置为根据占空比校正控制信号改变流入信号生成单元的电流量，该占空比校正控制信号具有基于电压电平输出信号; 以及耦合在可变电阻器单元和被配置为向信号产生单元提供电流的接地电压端子之间的电流源。

14. 发明申请

US20100164567A1 INTERNAL SUPPLY VOLTAGE GENERATING CIRCUIT AND METHOD FOR GENERATING INTERNAL SUPPLY VOLTAGE 失效
标题翻译：内部电源电压生成电路及内部电源电压的生成方法
公开(公告)号：US20100164567A1
公开(公告)日：2010-07-01
申请号：US12347605
申请日：2008-12-31
申请人： Yong-Ju KIM , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-jin Hwang , Hae-Rang Choi , Ji-Wang Lee , Jae-Min Jang , Chang-Kun Park
发明人： Yong-Ju KIM , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-jin Hwang , Hae-Rang Choi , Ji-Wang Lee , Jae-Min Jang , Chang-Kun Park
IPC分类号： H03L7/00 , G11C5/14 , G05F1/10
CPC分类号： G05F1/56 , G11C5/145 , H03L7/0812 , H03L7/093
摘要： An internal supply voltage generating circuit includes a clock comparator configured to compare a first clock signal having clock information corresponding to a level of a reference voltage with a second clock signal having clock information corresponding to a level of an internal supply voltage, a control signal generator configured to generate a driving control voltage having a voltage level corresponding to an output signal of the clock comparator; and a driver configured to drive a terminal of the internal supply voltage in response to the driving control voltage.
摘要翻译：内部电源电压产生电路包括：时钟比较器，被配置为将具有与参考电压电平相对应的时钟信息的第一时钟信号与具有对应于内部电源电压电平的时钟信息的第二时钟信号进行比较;控制信号发生器被配置为产生具有与所述时钟比较器的输出信号相对应的电压电平的驱动控制电压; 以及配置为响应于驱动控制电压驱动内部电源电压的端子的驱动器。

15. 发明申请

US20100064163A1 DOMAIN CROSSING CIRCUIT OF A SEMICONDUCTOR MEMORY APPARATUS 失效
标题翻译：半导体存储器装置的域交叉电路
公开(公告)号：US20100064163A1
公开(公告)日：2010-03-11
申请号：US12346675
申请日：2008-12-30
申请人： Hae Rang Choi , Yong Ju Kim , Sung Woo Han , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Ji Wang Lee , Jae Min Jang , Chang Kun Park
发明人： Hae Rang Choi , Yong Ju Kim , Sung Woo Han , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Ji Wang Lee , Jae Min Jang , Chang Kun Park
IPC分类号： G06F1/12
CPC分类号： G11C7/1051 , G06F1/12 , G11C7/1072 , G11C7/222
摘要： A domain crossing circuit of a semiconductor memory apparatus, the domain crossing circuit comprising first and second count signals generated at substantially a same clock period, and representing predetermined clock differences with reference to an internal clock signal with respect to same bit combination data, and a data processing unit configured to provide output data corresponding to input data based on the second count signal in response to the input data synchronized to an external clock signal.
摘要翻译：半导体存储器装置的域交叉电路，域交叉电路包括在基本上相同的时钟周期产生的第一和第二计数信号，并且相对于相同位组合数据参考内部时钟信号表示预定的时钟差，以及数据处理单元，被配置为响应于与外部时钟信号同步的输入数据，基于第二计数信号提供对应于输入数据的输出数据。

16. 发明申请

US20100034043A1 SEMICONDUCTOR IC DEVICE HAVING POWER-SHARING AND METHOD OF POWER-SHARING THEREOF 失效
标题翻译：具有动力共享的半导体IC器件及其共享方法
公开(公告)号：US20100034043A1
公开(公告)日：2010-02-11
申请号：US12333194
申请日：2008-12-11
申请人： Hyung Soo Kim , Yong Ju Kim , Sung Woo Han , Hee- Woong Song , Ic Su Oh , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee , Jae Min Jang , Chang Kun Park
发明人： Hyung Soo Kim , Yong Ju Kim , Sung Woo Han , Hee- Woong Song , Ic Su Oh , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee , Jae Min Jang , Chang Kun Park
IPC分类号： G11C5/14 , G11C7/00
CPC分类号： G11C5/14 , Y10T307/352 , Y10T307/391 , Y10T307/50 , Y10T307/505 , Y10T307/549 , Y10T307/555 , Y10T307/56 , Y10T307/565 , Y10T307/571 , Y10T307/576 , Y10T307/582 , Y10T307/587 , Y10T307/593
摘要： A semiconductor IC device capable of power-sharing includes a first power line configured to be supplied with a first power, a second power line configured to be supplied with a second power, a switching block configured to connect the first power line with the second power line in response to a first control signal, and a power-sharing control block configured to generate the control signal in accordance with a plurality of operation command signals.
摘要翻译：能够进行功率共享的半导体IC器件包括被配置为被提供第一电力的第一电力线，被配置为被提供第二电力的第二电力线，被配置为将第一电力线与第二电力连接的开关块响应于第一控制信号的线路;以及功率共享控制块，被配置为根据多个操作命令信号产生控制信号。

17. 发明申请

US20090257301A1 Voltage Level Comparison Circuit of Semiconductor Memory Apparatus, Voltage Adjustment Circuit Using Voltage Level Comparison Circuit, and Semiconductor Memory Apparatus Using the Same 失效
标题翻译：半导体存储器件的电压电平比较电路，使用电压电平比较电路的电压调节电路和使用其的半导体存储器件
公开(公告)号：US20090257301A1
公开(公告)日：2009-10-15
申请号：US12336423
申请日：2008-12-16
申请人： Ic Su Oh , Yong Ju Kim , Sung Woo Han , Hee Woong Song , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee , Jae Min Jang , Chang Kun Park
发明人： Ic Su Oh , Yong Ju Kim , Sung Woo Han , Hee Woong Song , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee , Jae Min Jang , Chang Kun Park
IPC分类号： G11C5/14
CPC分类号： G11C5/147
摘要： A voltage adjustment circuit of a semiconductor memory apparatus includes a control voltage generating unit configured to distribute an external voltage for selectively outputting a plurality of distribution voltages as a control voltage in response to a control signal, the plurality of the distribution voltages each have different voltage levels, a comparing unit configured to include a voltage supply unit configured to control an external voltage supplied to a first node and a second node if a level of an output voltage is higher than a level of a reference voltage in response to a level of the control voltage, and a detection signal generating unit configured to drop potential levels of the first and second nodes according to the levels of the output voltage and the reference voltage, and to output the potential level of the second node as a detection signal, and a voltage generating unit configured to drive the external voltage according to a potential level of the detection signal and to output the external voltage as the output voltage.
摘要翻译：半导体存储装置的电压调整电路包括：控制电压生成部，其被配置为响应于控制信号分配用于选择性地输出多个分配电压的外部电压作为控制电压，所述多个分配电压各自具有不同的电压电平，比较单元，被配置为包括电压供应单元，其被配置为响应于所述电平的电平而控制提供给第一节点的外部电压和第二节点，如果输出电压的电平高于参考电压的电平以及检测信号生成单元，被配置为根据输出电压和参考电压的电平来降低第一和第二节点的电位电平，并输出第二节点的电位电平作为检测信号，以及电压产生单元，被配置为根据检测信号的电位来驱动外部电压并输出外部电压作为输出电压。

18. 发明申请

US20090212853A1 APPARATUS FOR SUPPLYING POWER IN SEMICONDUCTOR INTEGRATED CIRCUIT AND INPUT IMPEDANCE CONTROL METHOD OF THE SAME 审中-公开
标题翻译：用于在半导体集成电路中供电的装置及其输入阻抗控制方法
公开(公告)号：US20090212853A1
公开(公告)日：2009-08-27
申请号：US12347318
申请日：2008-12-31
申请人： Hyung-Soo Kim , Yong Ju Kim , Sung Woo Han , Hee Woong Song , Jae Min Jang , Ji Wang Lee , Chang Kun Park , Ic Su Oh , Hae Rang Choi , Tae Jin Hwang
发明人： Hyung-Soo Kim , Yong Ju Kim , Sung Woo Han , Hee Woong Song , Jae Min Jang , Ji Wang Lee , Chang Kun Park , Ic Su Oh , Hae Rang Choi , Tae Jin Hwang
IPC分类号： G05F1/10 , H01L27/00
CPC分类号： H01L27/0727 , H01L29/94
摘要： An apparatus for supplying power in a semiconductor integrated circuit includes a plurality of power lines, each supplying external power to an interior of the semiconductor integrated circuit, and at least one decoupling capacitor set connected to the plurality of power lines and having a resistance value configured to be variable according to a bias voltage.
摘要翻译：一种用于在半导体集成电路中供电的装置包括多个电源线，每个电源线向半导体集成电路的内部提供外部电力，以及至少一个去耦电容器组，连接到多个电力线并具有电阻值配置根据偏置电压可变。

19. 发明申请

US20130051491A1 INTEGRATED CIRCUIT CHIP AND TRANSMITTING /RECEIVING SYSTEM INCLUDING THE SAME 有权
标题翻译：集成电路芯片和发送/接收系统，包括它们
公开(公告)号：US20130051491A1
公开(公告)日：2013-02-28
申请号：US13333692
申请日：2011-12-21
申请人： Yong-Ju KIM , Dae-Han Kwon , Hae-Rang Choi , Jae-Min Jang
发明人： Yong-Ju KIM , Dae-Han Kwon , Hae-Rang Choi , Jae-Min Jang
IPC分类号： H04L25/49
CPC分类号： G06F13/4077
摘要： A system for transmitting data includes a plurality of data lines configured to transmit the data and a transmitting chip configured to output the data to the data lines and perform a crosstalk prevention operation in response to a data pattern of the data to be transmitted through the data lines and array information of the data lines to prevent crosstalk from occurring in the data lines.
摘要翻译：用于发送数据的系统包括被配置为发送数据的多条数据线和被配置为将数据输出到数据线的发送芯片，并且响应于要通过数据发送的数据的数据模式执行串扰防止操作数据线的线和阵列信息，以防止在数据线中发生串扰。

20. 发明授权

US08378726B2 Clock signal duty correction circuit 有权
标题翻译：时钟信号占空比校正电路
公开(公告)号：US08378726B2
公开(公告)日：2013-02-19
申请号：US12846669
申请日：2010-07-29
申请人： Yong Ju Kim , Dae Han Kwon , Won Joo Yun , Hae Rang Choi , Jae Min Jang
发明人： Yong Ju Kim , Dae Han Kwon , Won Joo Yun , Hae Rang Choi , Jae Min Jang
IPC分类号： H03K5/04
CPC分类号： H03K5/1565
摘要： A clock signal duty correction circuit includes: a first transition timing control unit configured to generate a first control signal for controlling a rising timing of a duty correction clock signal by using a clock signal; a second transition timing control unit configured to generate a second control signal for varying a falling timing of the duty correction clock signal by using the clock signal according to a code signal; and a differential buffer unit configured to generate the duty correction clock signal, whose rising time or falling time is adjusted, in response to the first control signal and the second control signal.
摘要翻译：时钟信号占空比校正电路包括：第一转移定时控制单元，被配置为通过使用时钟信号产生用于控制占空比校正时钟信号的上升定时的第一控制信号; 第二转移定时控制单元，被配置为通过使用根据代码信号的时钟信号来生成用于改变占空比校正时钟信号的下降定时的第二控制信号; 以及差分缓冲器单元，被配置为响应于所述第一控制信号和所述第二控制信号而生成其上升时间或下降时间被调整的占空比校正时钟信号。

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