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    • 11. 发明申请
    • FLAT CABLE FOR MOUNTED DISPLAY DEVICES
    • 用于安装显示设备的平面电缆
    • US20090301755A1
    • 2009-12-10
    • US12134118
    • 2008-06-05
    • Peter Shintani
    • Peter Shintani
    • H01B7/08
    • H01B7/08
    • A flat high definition multimedia interface (HDMI) cable. The flat cable that is less visible in comparison to a round HDMI cable for wall mounted television setup. An HDMI connector is coupled to the flat cable. An active circuit isolates physical characteristics of the HDMI connector. The active circuit causes the flat cable to appear shorter than its actual length during HDMI compliance testing using impedance testing. Moreover, the active circuit causes a consumer electronic control (CEC) line, a display data channel (DDC) line and transition minimized differential signal (TMDS) line to actively terminate for reducing parasitic capacitance from the length of the flat cable during HDMI compliance testing. Thus, the isolation allows the flat cable to satisfy HDMI compliant testing. The flat cable may be selected from a group consisting of ribbon cable, twisted pair cable, flexible printed circuit board, micro coax cable, optical cable and glass fiber cable.
    • 平板高清多媒体接口(HDMI)电缆。 与用于壁挂式电视机的圆形HDMI电缆相比,扁平电缆不太可见。 HDMI连接器连接到扁平电缆。 有源电路隔离HDMI连接器的物理特性。 在使用阻抗测试的HDMI一致性测试期间,有源电路使扁平电缆看起来比其实际长度短。 此外,有源电路使得消费电子控制(CEC)线,显示数据通道(DDC)线和转换最小化差分信号(TMDS)线在HDMI一致性测试期间主动终止以减少来自扁平电缆的长度的寄生电容 。 因此,隔离允许扁平电缆满足HDMI兼容测试。 扁平电缆可以选自由带状电缆,双绞线,柔性印刷电路板,微同轴电缆,光缆和玻璃纤维电缆组成的组。
    • 12. 发明申请
    • HIGH-DEFINITION MULTIMEDIA INTERFACE RECEIVER/TRANSMITTER CHIPSET
    • 高分辨率多媒体接口/发射机芯片
    • US20090147135A1
    • 2009-06-11
    • US11953570
    • 2007-12-10
    • Peter SHINTANI
    • Peter SHINTANI
    • H04N7/00H04N11/00
    • G09G5/006G09G2370/12
    • A buffer chip is used to isolate the internal connection between an HDMI receiver chip and a remotely-located HDMI port in a consumer electronic device. In one embodiment, an HDMI receiver/transmitter circuit is coupled to a main processor via an internal bus. The HDMI receiver/transmitter circuit, which includes one or more local HDMI inputs/outputs, is further electrically coupled to an HDMI buffer chip, which is in turn connected to one or more HDMI ports located remotely from the HDMI receiver/transmitter circuit. In one embodiment, the detection and control of the HDMI buffer chip is provided directly by the HDMI receiver/transmitter circuit. In another embodiment, the HDMI buffer chip may be electrically isolated from the device's main processor.
    • 缓冲芯片用于隔离HDMI接收器芯片和消费电子设备中位于远程位置的HDMI端口之间的内部连接。 在一个实施例中,HDMI接收器/发射器电路经由内部总线耦合到主处理器。 包括一个或多个本地HDMI输入/输出的HDMI接收器/发射器电路进一步电耦合到HDMI缓冲器芯片,HDMI缓冲器芯片又连接到远离HDMI接收器/发射器电路的一个或多个HDMI端口。 在一个实施例中,HDMI缓冲器芯片的检测和控制由HDMI接收器/发射器电路直接提供。 在另一个实施例中,HDMI缓冲芯片可以与设备的主处理器电隔离。
    • 14. 发明授权
    • Controlled impedance bus with a buffer device
    • 带缓冲器的控制阻抗总线
    • US07517223B1
    • 2009-04-14
    • US12053474
    • 2008-03-21
    • Peter ShintaniKenichiro Toyoshima
    • Peter ShintaniKenichiro Toyoshima
    • H01R12/00
    • H05K1/111H05K1/0245H05K1/141H05K2201/09236H05K2201/09263H05K2201/10189H05K2201/10689Y02P70/611
    • A controlled impedance bus includes a pair of bus traces that carry a transmission minimized differential signal (TMDS). Two or more buffer output terminals. Each output terminal includes a pair of pads connected to the pair of bus traces such that unused pads create minimal stubs on the pair of bus traces. Two or more buffer input terminals are provided. Each of the buffer input terminals includes a pair of connector traces that extend substantially perpendicular to the bus traces. At least one connector is connected to a first end of the pair of connector traces of one of the buffer input terminals. At least one buffer device is connected to a second end of the pair of connector traces and to the pair of pads of one of the buffer output terminals. The buffer device provides signals on the pair of bus traces when enabled by an enable input.
    • 受控阻抗总线包括一对载送传输最小化差分信号(TMDS)的总线迹线。 两个或多个缓冲输出端子。 每个输出端子包括连接到该对总线迹线的一对焊盘,使得未使用的焊盘在该对总线迹线上形成最小的短截线。 提供两个或更多个缓冲器输入端子。 每个缓冲器输入端子包括基本上垂直于总线迹线延伸的一对连接器迹线。 至少一个连接器连接到缓冲器输入端之一的一对连接器迹线的第一端。 至少一个缓冲装置连接到一对连接器迹线的第二端和一个缓冲器输出端子的一对焊盘。 当使能输入使能时,缓冲器件在一对总线轨迹上提供信号。