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11. 发明授权

US07990772B2 Memory device having improved programming operation 有权
标题翻译：存储器件具有改进的编程操作
公开(公告)号：US07990772B2
公开(公告)日：2011-08-02
申请号：US12402158
申请日：2009-03-11
申请人： Prashant S. Damle , Krishna Parat , Alessandro Torsi , Carlo Musilli , Kalpana Vakati , Akira Goda
发明人： Prashant S. Damle , Krishna Parat , Alessandro Torsi , Carlo Musilli , Kalpana Vakati , Akira Goda
IPC分类号： G11C11/34
CPC分类号： G11C16/3404 , G11C16/0483 , G11C16/10 , G11C16/32
摘要： Some embodiments include methods and devices having a module and memory cells. The module is configured to reduce the amount of electrons in the sources and drains of the memory cells during a programming operation.
摘要翻译：一些实施例包括具有模块和存储器单元的方法和装置。该模块被配置为在编程操作期间减少存储器单元的源极和漏极中的电子量。

12. 发明申请

US20110090739A1 INDEPENDENT WELL BIAS MANAGEMENT IN A MEMORY DEVICE 有权
标题翻译：在存储设备中独立的良好BIAS管理
公开(公告)号：US20110090739A1
公开(公告)日：2011-04-21
申请号：US12582458
申请日：2009-10-20
申请人： Akira Goda , Tomoharu Tanaka , Krishna Parat , Prashant Damle , Shafqat Ahmed
发明人： Akira Goda , Tomoharu Tanaka , Krishna Parat , Prashant Damle , Shafqat Ahmed
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C16/0483
摘要： Methods for programming a memory device, memory devices configured to perform the disclosed programming methods, and memory systems having a memory device configured to perform the disclosed programming methods, for example, are provided. According to at least one such method, multiple independent semiconductor well regions each having strings of memory cells are independently biased during a programming operation performed on a memory device. Reduced charge leakage may be realized during a programming operation in response to independent well biasing methods.
摘要翻译：提供了用于编程存储器件的方法，被配置为执行所公开的编程方法的存储器件，以及具有被配置为执行所公开的编程方法的存储器件的存储器系统。根据至少一种这样的方法，在对存储器件执行的编程操作期间，各自具有存储器单元串的多个独立的半导体阱区被独立地偏置。响应于独立的井偏置方法，在编程操作期间可以实现减少的电荷泄漏。

13. 发明申请

US20100232234A1 MEMORY DEVICE HAVING IMPROVED PROGRAMMING OPERATION 有权
标题翻译：具有改进的编程操作的存储器件
公开(公告)号：US20100232234A1
公开(公告)日：2010-09-16
申请号：US12402158
申请日：2009-03-11
申请人： Prashant S. Damle , Krishna Parat , Alessandro Torsi , Carlo Musilli , Kalpana Vakati , Akira Goda
发明人： Prashant S. Damle , Krishna Parat , Alessandro Torsi , Carlo Musilli , Kalpana Vakati , Akira Goda
IPC分类号： G11C16/06 , G11C7/00
CPC分类号： G11C16/3404 , G11C16/0483 , G11C16/10 , G11C16/32
摘要： Some embodiments include methods and devices having a module and memory cells. The module is configured to reduce the amount of electrons in the sources and drains of the memory cells during a programming operation.
摘要翻译：一些实施例包括具有模块和存储器单元的方法和装置。该模块被配置为在编程操作期间减少存储器单元的源极和漏极中的电子量。

14. 发明申请

US20110134697A1 DYNAMIC PASS VOLTAGE FOR SENSE OPERATION IN A MEMORY DEVICE 有权
标题翻译：用于在存储器件中进行感测操作的动态输入电压
公开(公告)号：US20110134697A1
公开(公告)日：2011-06-09
申请号：US12630332
申请日：2009-12-03
申请人： Yijie Zhao , Akira Goda , Jian Li , Haitao Liu
发明人： Yijie Zhao , Akira Goda , Jian Li , Haitao Liu
IPC分类号： G11C16/26 , G11C16/04 , G11C16/34
CPC分类号： G11C11/5642 , G11C16/26 , G11C16/3418
摘要： Methods for sensing and memory devices are disclosed. One such method for sensing uses a dynamic pass voltage on at least one adjacent memory cell that is adjacent to a selected memory cell for programming. If the adjacent memory cell is not programmed, the pass voltage is reduced on the adjacent memory cell. The adjacent memory cell can be on the drain side, the source side, or both drain and source sides of the selected memory cell.
摘要翻译：公开了用于感测和存储器件的方法。用于感测的一种这样的方法在与选定的存储器单元相邻的至少一个相邻存储器单元上使用动态通过电压用于编程。如果相邻存储单元未编程，则相邻存储单元上的通过电压降低。相邻的存储单元可以在所选存储单元的漏极侧，源极侧或漏极和源极侧。

15. 发明授权

US08102712B2 NAND programming technique 有权
标题翻译： NAND编程技术
公开(公告)号：US08102712B2
公开(公告)日：2012-01-24
申请号：US12644408
申请日：2009-12-22
申请人： Akira Goda , Andrew Bickler , Haitao Liu , Tomoharu Tanaka
发明人： Akira Goda , Andrew Bickler , Haitao Liu , Tomoharu Tanaka
IPC分类号： G11C11/34
CPC分类号： G11C16/3418 , G11C16/0408 , G11C16/06
摘要： A NAND memory array is programmed applying a programming voltage Vpgm as a double pulse programming pulse if a data pattern associated with memory cells that are to be programmed form a two-sided column-stripe (CS2) data pattern. The CS2 data pattern comprises a memory cell that is not to be programmed directly between two memory cells that are to be programmed, such that a channel associated with the memory cell that is not to be programmed has an applied boost voltage, and the channels associated with the two memory cells that are to be programmed have an applied programming voltage. The first memory cell of the two memory cells is programmed by the first programming voltage pulse and the second memory cell is programmed by the second programming voltage pulse. A programming voltage Vpgm is applied as a single pulse if a CS2 data pattern is not formed.
摘要翻译：如果与要编程的存储器单元相关联的数据模式形成双面列条带（CS2）数据模式，则NAND存储器阵列被编程为将编程电压Vpgm应用为双脉冲编程脉冲。 CS2数据模式包括不被直接编程在待编程的两个存储器单元之间的存储器单元，使得与不被编程的存储器单元相关联的通道具有施加的升压电压，并且所述通道相关联要编程的两个存储单元具有应用的编程电压。两个存储单元的第一存储单元由第一编程电压脉冲编程，第二存储单元由第二编程电压脉冲编程。如果没有形成CS2数据模式，则将编程电压Vpgm作为单个脉冲施加。

16. 发明申请

US20190206889A1 MULTI-GATE STRING DRIVERS HAVING SHARED PILLAR STRUCTURE 审中-公开
公开(公告)号：US20190206889A1
公开(公告)日：2019-07-04
申请号：US15858509
申请日：2017-12-29
申请人： Akira Goda , Haitao Liu , Jin Chen , Guangyu Huang , Mojtaba Asadirad
发明人： Akira Goda , Haitao Liu , Jin Chen , Guangyu Huang , Mojtaba Asadirad
IPC分类号： H01L27/11573 , H01L27/11556 , H01L23/528 , H01L29/36 , H01L29/04 , H01L21/02 , H01L29/78 , H01L27/11582 , H01L27/11526 , H01L29/66 , H01L29/16 , H01L23/532 , G11C16/08 , G11C16/24
摘要： Some embodiments include apparatuses, and methods of forming the apparatuses. Some of the apparatuses include a first group of conductive materials interleaved with a first group of dielectric materials, a pillar extending through the conductive materials and the dielectric materials, memory cells located along the first pillar, a conductive contact coupled to a conductive material of the first group of conductive materials, and additional pillars extending through a second group of conductive materials and a second group of dielectric materials. The second pillar includes a first portion coupled to a conductive region, a second portion, a third portion, and a fourth portion coupled to the conductive contact. The second portion is located between the first and third portions. The second portion of each of the additional pillars is part of a piece of material extending from a first pillar to a second pillar of the additional pillars.

17. 发明授权

US08921891B2 Vertical memory cell string with dielectric in a portion of the body 有权
标题翻译：在身体的一部分具有电介质的垂直记忆单元格串
公开(公告)号：US08921891B2
公开(公告)日：2014-12-30
申请号：US13592086
申请日：2012-08-22
申请人： Haitao Liu , Akira Goda , Chandra Mouli , Krishna K. Parat
发明人： Haitao Liu , Akira Goda , Chandra Mouli , Krishna K. Parat
IPC分类号： H01L21/336
CPC分类号： H01L29/408 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L27/11582 , H01L29/7889 , H01L29/7926
摘要： Some embodiments include a memory cell string having a body having a channel extending therein and in contact with a source/drain, a select gate adjacent to the body, a plurality of access lines adjacent to the body, and a dielectric in a portion of the body between the source/drain and a level corresponding to an end of the plurality of access lines most adjacent to the select gate. The dielectric in the portion of the body does not extend along an entire length of the body. Other embodiments are described and claimed.
摘要翻译：一些实施例包括具有主体的存储单元串，该主体具有在其中延伸并与源极/漏极接触的通道，与主体相邻的选择栅极，与主体相邻的多个访问线，以及在该部分中的电介质源极/漏极与对应于与选择栅极最相邻的多条访问线路的端部相对应的电平。身体部分中的电介质不会沿着身体的整个长度延伸。描述和要求保护其他实施例。

18. 发明申请

US20140054666A1 VERTICAL MEMORY CELL STRING WITH DIELECTRIC IN A PORTION OF THE BODY 有权
标题翻译：垂直存储单元，具有介电体部分
公开(公告)号：US20140054666A1
公开(公告)日：2014-02-27
申请号：US13592086
申请日：2012-08-22
申请人： Haitao Liu , Akira Goda , Chandra Mouli , Krishna K. Parat
发明人： Haitao Liu , Akira Goda , Chandra Mouli , Krishna K. Parat
IPC分类号： H01L29/788
CPC分类号： H01L29/408 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L27/11582 , H01L29/7889 , H01L29/7926
摘要： Some embodiments include a memory cell string having a body having a channel extending therein and in contact with a source/drain, a select gate adjacent to the body, a plurality of access lines adjacent to the body, and a dielectric in a portion of the body between the source/drain and a level corresponding to an end of the plurality of access lines most adjacent to the select gate. The dielectric in the portion of the body does not extend along an entire length of the body. Other embodiments are described and claimed.
摘要翻译：一些实施例包括具有主体的存储单元串，该主体具有在其中延伸并与源极/漏极接触的通道，与主体相邻的选择栅极，与主体相邻的多个访问线，以及在该部分中的电介质源极/漏极与对应于与选择栅极最相邻的多条访问线路的端部相对应的电平。身体部分中的电介质不会沿着身体的整个长度延伸。描述和要求保护其他实施例。

19. 发明授权

US08144516B2 Dynamic pass voltage for sense operation in a memory device 有权
标题翻译：用于存储器件中的感测操作的动态通过电压
公开(公告)号：US08144516B2
公开(公告)日：2012-03-27
申请号：US12630332
申请日：2009-12-03
申请人： Yijie Zhao , Akira Goda , Jian Li , Haitao Liu
发明人： Yijie Zhao , Akira Goda , Jian Li , Haitao Liu
IPC分类号： G11C16/04
CPC分类号： G11C11/5642 , G11C16/26 , G11C16/3418
摘要： Methods for sensing and memory devices are disclosed. One such method for sensing uses a dynamic pass voltage on at least one adjacent memory cell that is adjacent to a selected memory cell for programming. If the adjacent memory cell is not programmed, the pass voltage is reduced on the adjacent memory cell. The adjacent memory cell can be on the drain side, the source side, or both drain and source sides of the selected memory cell.
摘要翻译：公开了用于感测和存储器件的方法。用于感测的一种这样的方法在与选定的存储器单元相邻的至少一个相邻存储器单元上使用动态通过电压用于编程。如果相邻存储单元未编程，则相邻存储单元上的通过电压降低。相邻的存储单元可以在所选存储单元的漏极侧，源极侧或漏极和源极侧。

20. 发明申请

US20110149654A1 NAND Programming Technique 有权
标题翻译： NAND编程技术
公开(公告)号：US20110149654A1
公开(公告)日：2011-06-23
申请号：US12644408
申请日：2009-12-22
申请人： Akira Goda , Andrew Bickler , Haitao Liu , Tomoharu Tanaka
发明人： Akira Goda , Andrew Bickler , Haitao Liu , Tomoharu Tanaka
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/3418 , G11C16/0408 , G11C16/06
摘要： A NAND memory array is programmed applying a programming voltage Vpgm as a double pulse programming pulse if a data pattern associated with memory cells that are to be programmed form a two-sided column-stripe (CS2) data pattern. The CS2 data pattern comprises a memory cell that is not to be programmed directly between two memory cells that are to be programmed, such that a channel associated with the memory cell that is not to be programmed has an applied boost voltage, and the channels associated with the two memory cells that are to be programmed have an applied programming voltage. The first memory cell of the two memory cells is programmed by the first programming voltage pulse and the second memory cell is programmed by the second programming voltage pulse. A programming voltage Vpgm is applied as a single pulse if a CS2 data pattern is not formed.
摘要翻译：如果与要编程的存储器单元相关联的数据模式形成双面列条带（CS2）数据模式，则NAND存储器阵列被编程为将编程电压Vpgm应用为双脉冲编程脉冲。 CS2数据模式包括不被直接编程在待编程的两个存储器单元之间的存储器单元，使得与不被编程的存储器单元相关联的通道具有施加的升压电压，并且所述通道相关联要编程的两个存储单元具有应用的编程电压。两个存储单元的第一存储单元由第一编程电压脉冲编程，第二存储单元由第二编程电压脉冲编程。如果没有形成CS2数据模式，则将编程电压Vpgm作为单个脉冲施加。

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