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11. 发明授权

US09508430B2 Three dimensional memory device including memory cells with resistance change layers 有权
标题翻译：三维存储器件包括具有电阻变化层的存储单元
公开(公告)号：US09508430B2
公开(公告)日：2016-11-29
申请号：US14849023
申请日：2015-09-09
申请人： Kabushiki Kaisha Toshiba
发明人： Kenichi Murooka
IPC分类号： G11C13/00 , G11C16/10
CPC分类号： G11C13/004 , G11C13/0002 , G11C13/0023 , G11C13/0026 , G11C13/0069 , G11C13/0097 , G11C2213/71 , G11C2213/77 , H01L27/2454 , H01L27/249 , H01L45/04 , H01L45/1226 , H01L45/1608
摘要： A memory device includes a plurality of first interconnects extending in a first direction; a plurality of second interconnects extending in the first direction; a plurality of third interconnects extending in a third direction; and memory cells each with resistance change layers provided on two side surfaces of a corresponding one of the third interconnects, which surfaces are opposite to each other in the second direction. The resistance change layers are connected to the different second interconnects. A plurality of selectors connect the third interconnects to the first interconnects. One of the selectors includes a semiconductor layer provided between the corresponding third interconnect and the corresponding first interconnect. Gates extending in the second direction and provided, via a gate insulating film, on two side surfaces that are opposite to each other in the first direction.
摘要翻译：存储器件包括沿第一方向延伸的多个第一互连件; 多个第二互连件，沿第一方向延伸; 多个第三互连，沿第三方向延伸; 以及每个具有电阻变化层的存储单元，所述电阻变化层设置在所述第三互连中相应一个的两个侧表面上，所述第三互连的所述表面在所述第二方向上彼此相对。电阻变化层连接到不同的第二互连。多个选择器将第三互连件连接到第一互连。选择器之一包括设置在对应的第三互连和对应的第一互连之间的半导体层。盖板沿第二方向延伸并且经由栅极绝缘膜在第一方向上彼此相对的两个侧表面上提供。

12. 发明申请

US20140027707A1 MEMORY DEVICE AND FABRICATING METHOD THEREOF 有权
标题翻译：存储器件及其制造方法
公开(公告)号：US20140027707A1
公开(公告)日：2014-01-30
申请号：US14038109
申请日：2013-09-26
申请人： Kabushiki Kaisha Toshiba
发明人： Kenichi Murooka
IPC分类号： H01L45/00 , G11C13/00
CPC分类号： H01L45/122 , G11C13/0002 , G11C2213/71 , H01L27/2409 , H01L27/2463 , H01L27/2481 , H01L45/04 , H01L45/124 , H01L45/146 , H01L45/147 , H01L45/1691
摘要： According to one embodiment, a memory device includes first interconnects, second interconnects, and a first memory cell. The first memory cell is located in an intersection of one of the first interconnects and one of the second interconnects. The first memory cell includes a first multilayer structure and a first variable resistance layer, the first multilayer structure including a first electrode, a first selector, and a first insulator which are stacked. The first selector and the first variable resistance layer are electrically connected in series between the one of the first interconnect and the one of the second interconnect. The first variable resistance layer is formed on a portion of a side surface of the first insulator to cover the portion without covering a residual portion.
摘要翻译：根据一个实施例，存储器件包括第一互连，第二互连和第一存储单元。第一存储器单元位于第一互连中的一个和第二互连中的一个的交叉点中。第一存储单元包括第一多层结构和第一可变电阻层，第一多层结构包括堆叠的第一电极，第一选择器和第一绝缘体。第一选择器和第一可变电阻层串联地电连接在第一互连和第二互连中的一个之间。第一可变电阻层形成在第一绝缘体的侧表面的一部分上以覆盖该部分而不覆盖剩余部分。

13. 发明授权

US08565007B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08565007B2
公开(公告)日：2013-10-22
申请号：US13764274
申请日：2013-02-11
申请人： Kabushiki Kaisha Toshiba
发明人： Kenichi Murooka
IPC分类号： G11C11/00
CPC分类号： G11C5/025 , G11C5/063 , G11C8/14 , G11C11/412 , G11C13/0007 , G11C13/0021 , G11C13/004 , G11C2013/005 , H01L27/2481 , H01L27/249 , H01L45/04 , H01L45/10 , H01L45/146 , H01L45/147
摘要： A semiconductor memory device in accordance with an embodiment includes a plurality of first word lines, a plurality of bit lines, a resistance varying material, a plurality of second word lines and an insulating film. The bit lines intersect the first word lines. The resistance varying material is disposed at respective intersections of the first word lines and the bit lines. The second word lines intersect the bit lines. The insulating film is disposed at respective intersections of the second word lines and the bit lines. One of the first word lines and one of the second word lines are disposed so as to sandwich the bit lines. The second word lines, the bit lines, and the insulating film configure a field-effect transistor at respective intersections of the second word lines and the bit lines. The field-effect transistor and the resistance varying material configure one memory cell.
摘要翻译：根据实施例的半导体存储器件包括多个第一字线，多个位线，电阻变化材料，多个第二字线和绝缘膜。位线与第一个字线相交。电阻变化材料设置在第一字线和位线的相应交点处。第二个字线与位线相交。绝缘膜设置在第二字线和位线的各个交叉处。第一字线和第二字线之一之一被布置成夹住位线。第二字线，位线和绝缘膜在第二字线和位线的各个交点配置场效应晶体管。场效应晶体管和电阻变化材料配置一个存储单元。

14. 发明授权

US09231029B2 Semiconductor memory device and method for manufacturing same 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US09231029B2
公开(公告)日：2016-01-05
申请号：US14284516
申请日：2014-05-22
申请人： Kabushiki Kaisha Toshiba
发明人： Kenichi Murooka
IPC分类号： H01L27/24 , H01L45/00
CPC分类号： H01L27/2481 , H01L27/2454 , H01L27/249 , H01L45/04 , H01L45/06 , H01L45/1226 , H01L45/1233 , H01L45/146 , H01L45/147 , H01L45/148 , H01L45/149 , H01L45/16
摘要： According to one embodiment, a semiconductor memory device includes a plurality of global bit lines, a plurality of word lines, a plurality of bit lines, a plurality of resistance change films, a plurality of semiconductor layers, a gate insulating film, and a plurality of gate electrodes. Spacing in the first direction between the plurality of semiconductor layers is larger than spacing in the second direction between the plurality of semiconductor layers. The plurality of gate electrodes is separated in the first direction.
摘要翻译：根据一个实施例，半导体存储器件包括多个全局位线，多个字线，多个位线，多个电阻变化膜，多个半导体层，栅极绝缘膜和多个的栅电极。在多个半导体层之间的第一方向上的间隔大于多个半导体层之间的第二方向上的间隔。多个栅电极在第一方向上分离。

15. 发明授权

US09129677B2 Memory device and method of controlling memory device 有权
标题翻译：存储器件和控制存储器件的方法
公开(公告)号：US09129677B2
公开(公告)日：2015-09-08
申请号：US14282047
申请日：2014-05-20
申请人： Kabushiki Kaisha Toshiba
发明人： Kenichi Murooka
IPC分类号： G11C11/00 , G11C13/00
CPC分类号： G11C13/0021 , G11C13/0002 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/0069 , G11C2213/71 , H01L27/2454 , H01L27/249
摘要： According to one embodiment, a memory device includes a plurality of global column lines arranged in parallel and extending in a first direction; a plurality of row lines extending in a second direction which is perpendicular to the first direction; a plurality of column lines in a two-dimensional arrangement, which extend in a third direction which is perpendicular to the first direction and the second direction; and a memory cell array including a plurality of memory cells arranged at intersections between the row lines and the column lines.
摘要翻译：根据一个实施例，存储器件包括平行布置并沿第一方向延伸的多个全局列线; 沿与第一方向垂直的第二方向延伸的多条行线; 多个垂直于第一方向和第二方向的第三方向延伸的二维排列的列线; 以及包括布置在行线和列线之间的交叉处的多个存储单元的存储单元阵列。

16. 发明授权

US08681532B2 Resistance change memory 有权
标题翻译：电阻变化记忆
公开(公告)号：US08681532B2
公开(公告)日：2014-03-25
申请号：US13937274
申请日：2013-07-09
申请人： Kabushiki Kaisha Toshiba
发明人： Kenichi Murooka
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0023 , G11C13/0033 , G11C2013/0092 , G11C2213/71 , G11C2213/72
摘要： A memory includes memory cells each includes a resistance change element and a diode, and each memory cell between one of row lines and one of column lines, a first decoder which selects one of the row lines as a selected row line, a second decoder which selects one of the column lines as a selected column line, a voltage pulse generating circuit which generates a voltage pulse, a voltage pulse shaping circuit which makes a rise time and a fall time of the voltage pulse longer, and a control circuit which applies the voltage pulse outputting from the voltage pulse shaping circuit to unselected column lines except the selected column line, and which applies a fixed potential to unselected row lines except the selected row line, in a data writing to a memory cell which is provided between the selected row line and the selected column line.
摘要翻译：存储器包括各自包括电阻变化元件和二极管的存储单元，以及行线和列线之一之间的每个存储单元，选择行行之一作为所选行行的第一解码器，第二解码器，选择列线之一作为选择的列线，产生电压脉冲的电压脉冲发生电路，使电压脉冲的上升时间和下降时间更长的电压脉冲整形电路以及施加电压脉冲的控制电路电压脉冲从电压脉冲整形电路输出到除了所选列线之外的未选择的列线，并且在设置在所选择的行之间的存储单元的数据写入中将固定电位施加到除所选行行之外的未选行行行和所选列行。

17. 发明授权

US09466367B2 Memory device, method of controlling memory device, and memory system 有权
公开(公告)号：US09466367B2
公开(公告)日：2016-10-11
申请号：US15131142
申请日：2016-04-18
申请人： Kabushiki Kaisha Toshiba
发明人： Kenichi Murooka
IPC分类号： G11C11/34 , G11C16/04 , G11C13/00
CPC分类号： G11C13/0069 , G06F3/0611 , G06F3/0659 , G06F3/0673 , G11C7/1006 , G11C13/0002 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/0033 , G11C13/004 , G11C2213/71 , H01L27/2454 , H01L27/249 , H01L45/16
摘要： A memory device according to an embodiment comprises a data processing circuit that includes: a data write pre-processing circuit that processes input data to generate first intermediate data; a data write processing circuit that sequentially sets a voltage difference between a selected row line and a selected global bit line based on the first intermediate data; a data read processing circuit that detects a current flowing in the selected global bit line or a voltage of the selected global bit line and sequentially generates second intermediate data from a result of that detection; and a data read post-processing circuit that processes the second intermediate data to generate output data, the data write pre-processing circuit and the data read post-processing circuit having a correcting function that corrects a difference that may occur between the input data and the output data.

18. 发明授权

US09455257B2 Semiconductor memory device and method of manufacturing the same 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US09455257B2
公开(公告)日：2016-09-27
申请号：US14593344
申请日：2015-01-09
申请人： Kabushiki Kaisha Toshiba
发明人： Kenichi Murooka
IPC分类号： H01L27/10 , H01L27/105 , H01L27/24 , H01L45/00
CPC分类号： H01L27/249 , G11C13/0026 , G11C13/0028 , H01L27/1052 , H01L27/2454 , H01L27/2463 , H01L45/04 , H01L45/1226 , H01L45/1233 , H01L45/146 , H01L45/147 , H01L45/16
摘要： A connection unit is provided adjacently to the cell array unit and electrically connected to a peripheral circuit unit positioned downwardly of the cell array unit. The cell array unit has a configuration in which a variable resistance layer is provided at intersections of a plurality of word lines extending in a horizontal direction and a plurality of bit lines extending in a vertical direction. The connection unit includes a lower wiring line layer in which a base portion bundling a plurality of the word lines is formed, and a middle wiring line layer and upper wiring line layer formed upwardly thereof. The lower wiring line layer includes: a first penetrating electrode connecting the plurality of word lines and the peripheral circuit unit; and a second penetrating electrode connecting at least one of the middle wiring line layer and upper wiring line layer and the peripheral circuit unit.
摘要翻译：连接单元靠近单元阵列单元设置并电连接到位于单元阵列单元下方的外围电路单元。电池阵列单元具有在水平方向上延伸的多个字线和在垂直方向上延伸的多个位线的交叉处设置可变电阻层的结构。连接单元包括形成有多个字线的基部的下布线层，以及向上形成的中间布线线层和上布线线层。下布线层包括：连接多条字线和外围电路单元的第一穿透电极; 以及连接中间布线层和上布线层和外围电路单元中的至少一个的第二贯穿电极。

19. 发明授权

US09368160B2 Memory device 有权
标题翻译：内存设备
公开(公告)号：US09368160B2
公开(公告)日：2016-06-14
申请号：US14472094
申请日：2014-08-28
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Kenichi Murooka
IPC分类号： G11C5/06 , G11C5/02 , G11C13/00 , G11C7/10
CPC分类号： H01L27/2481 , G11C5/02 , G11C5/06 , G11C5/063 , G11C7/1006 , G11C13/0002 , G11C13/0007 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/003 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C2213/31 , G11C2213/32 , G11C2213/35 , G11C2213/71 , G11C2213/78 , H01L21/768 , H01L27/2454 , H01L29/66666 , H01L45/1233 , H01L45/146 , H01L45/147 , H01L45/149 , H01L45/1608
摘要： According to one embodiment, a memory device includes first to third interconnects, memory cells, and selectors. The first to third interconnects are provided along first to third directions, respectively. The memory cells includes variable resistance layers formed on two side surfaces, facing each other in the first direction, of the third interconnects. The selectors couple the third interconnects with the first interconnects. One of the selectors includes a semiconductor layer provided between associated one of the third interconnects and associated one of the first interconnects, and gates formed on two side surfaces of the semiconductor layer facing each other in the first direction with gate insulating films interposed therebetween.
摘要翻译：根据一个实施例，存储器件包括第一至第三互连，存储器单元和选择器。第一至第三互连分别沿着第一至第三方向设置。存储单元包括形成在第三互连件的第一方向上彼此面对的两个侧表面上的可变电阻层。选择器将第三互连与第一互连耦合。其中一个选择器包括一个半导体层，该半导体层设置在相互连接的第三互连中的一个和第一互连中的相关一个之间，以及形成在半导体层的在第一方向上彼此相对的两个侧表面上的栅极之间的栅极绝缘膜。

20. 发明授权

US09349446B2 Semiconductor memory device and method of controlling the same 有权
标题翻译：半导体存储器件及其控制方法
公开(公告)号：US09349446B2
公开(公告)日：2016-05-24
申请号：US14593254
申请日：2015-01-09
申请人： Kabushiki Kaisha Toshiba
发明人： Kenichi Murooka
IPC分类号： G11C13/00 , G11C5/06 , G11C5/02
CPC分类号： G11C13/0021 , G11C13/0002 , G11C13/0004 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/003 , G11C13/004 , G11C13/0069 , G11C2213/71
摘要： A plurality of word lines extend in a first direction and are disposed in a second direction and a third direction. A plurality of bit lines extend in the third direction and are disposed in the first direction and the second direction. A global bit line is coupled in common to the plurality of bit lines. A selection elements is disposed between the bit line and the global bit line. A control circuit is able to perform respective operations of reading, writing, and deletion on the storage element. A resistive element is disposed on the global bit line side with respect to the selection element. The resistive element adjusts a magnitude of a voltage to be applied to the selection element according to a magnitude of a current flowing through the selection element.
摘要翻译：多个字线在第一方向上延伸并且沿第二方向和第三方向设置。多个位线在第三方向上延伸并且沿第一方向和第二方向设置。全局位线被共同地耦合到多个位线。选择元件设置在位线和全局位线之间。控制电路能够对存储元件执行读取，写入和删除的相应操作。电阻元件相对于选择元件设置在全局位线侧。电阻元件根据流过选择元件的电流的大小来调整要施加到选择元件的电压的大小。

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